JPH11220066A - Manufacture of laminated plate with metal core with both sides lined with metal foil for semiconductor plastic package - Google Patents

Manufacture of laminated plate with metal core with both sides lined with metal foil for semiconductor plastic package

Info

Publication number
JPH11220066A
JPH11220066A JP3423698A JP3423698A JPH11220066A JP H11220066 A JPH11220066 A JP H11220066A JP 3423698 A JP3423698 A JP 3423698A JP 3423698 A JP3423698 A JP 3423698A JP H11220066 A JPH11220066 A JP H11220066A
Authority
JP
Japan
Prior art keywords
metal
resin
printed wiring
wiring board
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3423698A
Other languages
Japanese (ja)
Inventor
Morio Take
杜夫 岳
Nobuyuki Ikeguchi
信之 池口
Kozo Yamane
康三 山根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Gas Chemical Co Inc
Original Assignee
Mitsubishi Gas Chemical Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Gas Chemical Co Inc filed Critical Mitsubishi Gas Chemical Co Inc
Priority to JP3423698A priority Critical patent/JPH11220066A/en
Priority to US09/207,115 priority patent/US6376908B1/en
Priority to EP98310022A priority patent/EP0926729A3/en
Priority to KR1019980054122A priority patent/KR19990062959A/en
Publication of JPH11220066A publication Critical patent/JPH11220066A/en
Priority to US10/036,385 priority patent/US6720651B2/en
Priority to US10/790,039 priority patent/US20040171189A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a laminated plate both whose sides are lined with metal foils for a semiconductor plastic package superior in thermal dissipation and heat resistance, after moisture absorption, etc. SOLUTION: This semiconductor plastic package with a metal core, and a manufacture of a laminated plate both sides of which are lined with metal foils for a package with such a structure that a part of the metal core is exposed at one part of the surface and a semiconductor chip is fixed thereon, and a circuit conductor are connected with each other by wire bonding and circuits on obverse on and reverse are wired with each other by through-hole conductors insulated from the metal core by thermosetting resin, at least one or more pieces of through-holes are connected directly with the metal core, and the semiconductor chip is resin encapsulated. At this time, for the side of a metal projection, a low-flow or a no-flow prepreg whose projection is hollowed out, and for the opposite side, a high-flow prepreg are used, and these are stacked and molded under heating and pressurization. Hereby, a laminated plate both sides of which are lined with metal foils for a semiconductor plastic package of new structure superior in thermal dissipation and heat resistance, after moisture absorption, etc., and suitable for mass production can be obtained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップを小
型プリント配線板に搭載した形の、新規な半導体プラス
チックパッケージに使用する両面銅張積層板の製造方法
に関する。特に、マイクロプロセッサー、マイクロコン
トローラー、ASIC、グラフィック等の比較的高ワット
で、多端子高密度の半導体プラスチックパッケージに使
用する両面銅張積層板の製造方法に関するものである。
本半導体プラスチックパッケージは、ワイヤボンディン
グで半導体チップとプリント配線板の回路導体を接続す
るものであり、ソルダーボールを用いてマザーボードプ
リント配線板に実装して電子機器として使用される。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a double-sided copper-clad laminate for use in a novel semiconductor plastic package in which a semiconductor chip is mounted on a small printed wiring board. In particular, the present invention relates to a method for manufacturing a double-sided copper-clad laminate used for a semiconductor plastic package having a relatively high wattage and a high density of terminals such as a microprocessor, a microcontroller, an ASIC, and a graphic.
The present semiconductor plastic package connects a semiconductor chip and a circuit conductor of a printed wiring board by wire bonding, and is mounted on a motherboard printed wiring board using solder balls and used as an electronic device.

【０００２】[0002]

【従来の技術】従来、半導体プラスチックパッケージと
して、プラスチックボールグリッドアレイ（P-BGA)やプ
ラスチックランドグリッドアレイ（P-LGA)等、プラスチ
ックプリント配線板の上面に半導体チップを固定し、該
半導体チップをプリント配線板上面に形成された導体回
路にワイヤボンディングで結合し、プリント配線板の下
面にはソルダーボールを用いて、マザーボードプリント
配線板と接続するための導体パッドを形成し、表裏回路
導体がメッキされたスルーホールで接続されて、半導体
チップが樹脂封止されている構造の半導体プラスチック
パッケージが公知である。本公知構造において、半導体
から発生する熱をマザーボードプリント配線板に拡散さ
せるため、半導体チップを固定するための上面の金属箔
から下面に接続するメッキされた熱拡散スルーホールが
形成されている。該スルーホールを通して水分が半導体
固定に使われている銀粉入り樹脂接着剤に吸湿され、マ
ザーボードへの実装時の加熱により、また、半導体部品
をマザーボードから取り外す際の加熱により、層間フク
レを発生する危険性があり、これはポップコーン現象と
呼ばれている。このポップコーン現象が生じた場合、パ
ッケージは使用不能となることが多く、この現象を大幅
に改善する必要がある。また、半導体の高機能化、高密
度化は、ますます発熱量の増大を意味し、熱放散用のた
めの半導体チップ直下のスルーホールのみでは熱の放射
は不十分となってきている。これらの半導体チップ搭載
用プリント配線板は、従来、中にガラス織布基材のプリ
プレグを使用し、両面に銅箔を用いて積層成形して得ら
れた両面銅張積層板を用いて作成しており、どうしても
上記構造とならざるを得ない。2. Description of the Related Art Conventionally, a semiconductor chip such as a plastic ball grid array (P-BGA) or a plastic land grid array (P-LGA) is fixed on a top surface of a plastic printed wiring board as a semiconductor plastic package. It is connected to the conductor circuit formed on the upper surface of the printed wiring board by wire bonding, and the lower surface of the printed wiring board is formed with conductor pads for connection with the motherboard printed wiring board using solder balls, and the front and back circuit conductors are plated 2. Description of the Related Art A semiconductor plastic package having a structure in which a semiconductor chip is sealed with a resin by connecting through a formed through hole is known. In the known structure, a plated heat diffusion through hole is formed from the upper metal foil for fixing the semiconductor chip to the lower surface in order to diffuse the heat generated from the semiconductor to the motherboard printed wiring board. Moisture is absorbed by the resin adhesive containing silver powder used for fixing the semiconductor through the through holes, causing danger of interlayer blisters due to heating during mounting on the motherboard and heating when removing the semiconductor components from the motherboard. This is called the popcorn phenomenon. When this popcorn phenomenon occurs, the package often becomes unusable, and it is necessary to greatly improve this phenomenon. In addition, higher functionality and higher density of semiconductors mean more and more heat generation, and heat radiation is becoming insufficient only with through holes directly below a semiconductor chip for heat dissipation. Conventionally, these printed wiring boards for mounting semiconductor chips are prepared using a double-sided copper-clad laminate obtained by laminating and molding using a prepreg of a glass woven fabric base material inside and copper foil on both sides. Therefore, the structure described above must be adopted.

【０００３】[0003]

【発明が解決しようする課題】本発明は、以上の問題点
を改善した半導体プラスチックパッケージ用のプリント
配線板を作成する両面銅張積層板を提供する。SUMMARY OF THE INVENTION The present invention provides a double-sided copper-clad laminate for producing a printed wiring board for a semiconductor plastic package which has solved the above problems.

【０００４】[0004]

【課題を解決するための手段】本発明は、プリント配線
板の厚さ方向のほぼ中央に、プリント配線板とほぼ同じ
大きさの金属板を配置し、プリント配線板の片面には金
属板の一部を突起状に露出し、この突起部上に半導体チ
ップを固定し、半導体チップをその周囲のプリント配線
板表面に形成された回路導体とワイヤボンディングで接
続し、少なくとも、プリント配線板表面上の信号伝播回
路導体を、プリント配線板の反対面に形成された回路導
体もしくは該ハンダボールの接続用導体パッドとメッキ
されたスルーホール導体で結線し、少なくとも半導体チ
ップ部を樹脂封止している構造の半導体プラスチックパ
ッケージ用両面金属箔張積層板の製造方法において、該
製造方法が、(1) 内層に使用する金属板を用意し、こ
の片面に半導体チップを接着する凸状の突起を形成し、
さらに表裏回路導体導通用スルーホールを形成するため
の、スルーホールの径より大きめのクリアランスホール
をあけ、(2) 金属突起部のある側に、突起部の位置に
突起部の面積よりやや大きめの孔をあけたローフロー、
又はノーフローのプリプレグシートもしくは樹脂層を配
置し、その反対側にはクリアランスホールを埋め込むに
十分な樹脂量と樹脂流れを有するハイフロープリプレグ
シートもしくは樹脂層を配置し、その両外側に金属箔或
いは片面金属箔張積層板を置き、(3) 加熱、加圧下に
積層成形して一体化することにより金属芯入り両面金属
箔張積層板を作成し、(4) この両面金属箔張積層板を
使用して、ドリル、レーザー等でクリアランスホールの
径よりやや小さいスルーホールをあけ、スルーホールの
孔壁と金属板とは樹脂組成物で絶縁し、かつ少なくとも
１個以上のスルーホールを金属板と接続させて熱放散用
に使用し、これに金属メッキを施した後、表裏に回路を
形成すると同時に金属板突起部上の金属箔をエッチング
除去し、少なくとも、ボンディングパッド、ハンダボー
ルパッド、半導体チップを固定する金属突起部以外の金
属板表面をメッキレジストで被覆し、ニッケル、金メッ
キを付着させてプリント配線板を作成し、このプリント
配線板の金属突起部に半導体チップを金属粉混合導電性
−熱伝導性接着剤で接着、固定し、ワイヤボンディン
グ、樹脂封止、ハンダボール付着を行ない、パッケージ
とする上記製造方法を提供する。本発明の製造方法によ
り得られた半導体プラスチックパッケージは、半導体下
面からの吸湿がなく、ポップコーン現象が大幅に改善で
きるとともに、多官能性シアン酸エステルのような熱硬
化性樹脂組成物を使用することにより、耐熱性、プレッ
シャークッカー処理後の電気絶縁性、耐マイグレーショ
ン性等に優れ、且つ、熱放散性をも大幅に改善でき、加
えて大量生産に適し、経済性の改善された、新規な構造
の半導体プラスチックパッケージを提供できることを見
いだし、本発明を完成するに至った。According to the present invention, a metal plate having substantially the same size as a printed wiring board is disposed substantially at the center in the thickness direction of the printed wiring board. A part is exposed in the form of a protrusion, the semiconductor chip is fixed on the protrusion, and the semiconductor chip is connected to the circuit conductor formed on the surface of the printed wiring board by wire bonding, and at least on the surface of the printed wiring board. Is connected to a circuit conductor formed on the opposite surface of the printed wiring board or a conductor pad for connection of the solder ball with a plated through-hole conductor, and at least the semiconductor chip portion is resin-sealed. In the method for producing a double-sided metal foil-clad laminate for a semiconductor plastic package having a structure, the production method comprises the steps of (1) preparing a metal plate to be used for an inner layer, To form a convex projection that adheres
In addition, make a clearance hole larger than the diameter of the through hole to form a through hole for conducting the front and back circuit conductors. (2) On the side with the metal protrusion, slightly larger than the area of the protrusion at the position of the protrusion Perforated low flow,
Or, place a no-flow prepreg sheet or resin layer, and on the opposite side, place a high-flow prepreg sheet or resin layer having a sufficient amount of resin and resin flow to fill the clearance holes, and place metal foil or single-sided metal on both outsides. Placing the foil-clad laminate, (3) laminating and forming under heat and pressure and integrating to create a double-sided metal-foil-clad laminate with a metal core, and (4) using this double-sided metal-foil-clad laminate Then, drill a through hole slightly smaller than the diameter of the clearance hole with a laser, insulate the hole wall of the through hole and the metal plate with a resin composition, and connect at least one or more through holes to the metal plate. After heat-dissipating and applying metal plating to this, a circuit is formed on the front and back, and at the same time, the metal foil on the metal plate protrusion is removed by etching. The surface of the metal plate other than the metal pad for fixing the padding, solder ball pad, and semiconductor chip is coated with a plating resist, and nickel and gold plating is applied to create a printed wiring board. The present invention provides the above-mentioned manufacturing method in which a semiconductor chip is bonded and fixed with a metal powder mixed conductive-thermal conductive adhesive, and is subjected to wire bonding, resin sealing, and solder ball attachment to form a package. The semiconductor plastic package obtained by the manufacturing method of the present invention does not absorb moisture from the lower surface of the semiconductor, can greatly improve the popcorn phenomenon, and uses a thermosetting resin composition such as a polyfunctional cyanate ester. The new structure has excellent heat resistance, electrical insulation after pressure cooker treatment, migration resistance, etc., and can greatly improve heat dissipation as well as being suitable for mass production and improved economy. It has been found that the semiconductor plastic package of the present invention can be provided, and the present invention has been completed.

【０００５】[0005]

【発明の実施の形態】本発明のプラスチックパッケージ
は、プリント配線板の厚み方向のほぼ中央に熱放散性の
良好な金属板を配置し、表裏の回路導体導通用のメッキ
されたスルーホールは、金属板にあけられた該スルーホ
ール径より大きめの径の孔とし、埋め込まれた樹脂のほ
ぼ中央に形成することにより、金属板との絶縁性を保持
する。BEST MODE FOR CARRYING OUT THE INVENTION In the plastic package of the present invention, a metal plate having good heat dissipation is arranged at substantially the center in the thickness direction of a printed wiring board. By forming a hole having a diameter larger than the diameter of the through hole formed in the metal plate and forming the hole substantially at the center of the embedded resin, the insulation with the metal plate is maintained.

【０００６】公知のスルーホールを有する金属芯プリン
ト配線板の上面に半導体チップを固定する方法において
は、従来のP-BGA パッケージと同様に半導体チップから
の熱は直下の熱放散用スルーホールに落として熱放散せ
ざるを得ず、ポップコーン現象は改善できない。本発明
で得られる両面銅張積層板を用いて作成した半導体プラ
スチックパッケージ用プリント配線板は、熱伝導性接着
剤で半導体チップを固定する金属突起部が、少なくと
も、１個以上表面に露出しており、スルーホールを形成
しようとする位置にスルーホール径より大きめのクリア
ランスホールがあけてあり、このクリアランスホールの
ほぼ中央に、クリアランスホール径より小さいスルーホ
ールを形成し、メッキで表裏回路が導通されており、ま
た、少なくとも、１個以上のスルーホールが内層金属板
と直接接続した構造となっているため、半導体チップを
固定し、ワイヤボンディング、樹脂封止したプラスチッ
クパッケージの、半導体から発生する熱は、直接搭載す
る金属部分から金属板全体に熱伝導されるために、半導
体チップ直下以外の場所から、この金属板に接続するス
ルーホールを通じて下面の金属パッドに伝達し、マザー
ボードプリント配線板に拡散する構造とする。In a known method of fixing a semiconductor chip on the upper surface of a metal-core printed wiring board having a through-hole, heat from the semiconductor chip is dropped to a heat-dissipating through-hole immediately below, similarly to a conventional P-BGA package. Heat must be dissipated and the popcorn phenomenon cannot be improved. The printed wiring board for a semiconductor plastic package prepared using the double-sided copper-clad laminate obtained by the present invention has at least one or more metal projections for fixing a semiconductor chip with a heat conductive adhesive exposed on the surface. There is a clearance hole larger than the through hole diameter at the position where the through hole is to be formed, and a through hole smaller than the clearance hole diameter is formed almost at the center of this clearance hole, and the front and back circuits are conducted by plating. In addition, since at least one or more through-holes are directly connected to the inner metal plate, the heat generated from the semiconductor in the plastic package in which the semiconductor chip is fixed, wire-bonded, and resin-sealed Is directly under the semiconductor chip because heat is transferred from the metal part directly mounted to the entire metal plate. From outside the location, and transmitted to the lower surface of the metal pad via a through hole connecting to the metal plate, a structure for diffusing the motherboard printed circuit board.

【０００７】本発明に用いる金属板は、特に限定しない
が、高弾性率、高熱伝導性で、厚さ30〜300μｍ のもの
が好適である。具体的には、純銅、無酸素銅、その他、
銅のFe、Sn、P 、Cr、Zr、Zn等との合金、或いは合金の
表面を銅メッキした金属板等が好適には使用される。Although the metal plate used in the present invention is not particularly limited, a metal plate having a high elastic modulus, a high thermal conductivity and a thickness of 30 to 300 μm is suitable. Specifically, pure copper, oxygen-free copper, and others,
An alloy of copper with Fe, Sn, P, Cr, Zr, Zn, or the like, or a metal plate whose surface is plated with copper is preferably used.

【０００８】本発明は、まず金属芯とする金属板をあら
かじめ公知のエッチング法、冷間機械加工法、圧延異型
条加工法等の方法で、少なくとも、１個以上の半導体チ
ップ固定用に、半導体チップとほぼ同じか小さい突起を
形成しておく。また、平滑な金属板の上に、半導体チッ
プとほぼ同等か、小さめの金属板を熱伝導の良好な接着
剤等で接着させて突起とすることも可能である。具体的
な形状例としては図２に示すが、これに限定されるもの
ではない。According to the present invention, at least one semiconductor chip is fixed on a metal plate serving as a metal core by a known etching method, cold machining method, rolling irregular shape processing method, or the like. A projection almost the same as or smaller than the chip is formed. It is also possible to form a protrusion on a smooth metal plate by bonding a metal plate approximately equal to or smaller than the semiconductor chip with an adhesive having good heat conductivity. Although a specific example of the shape is shown in FIG. 2, it is not limited to this.

【０００９】本発明の金属突起部の高さは、30〜200μm
が好適である。また、突起部をくり抜いたプリプレ
グ、或いはスクリーン印刷で形成する熱硬化性樹脂の高
さは、この突起と同じ高さか、やや高いことが好まし
い。突起部の面積は、半導体チップの面積とほぼ同等
か、小さめである。一般的には５〜20mm角である。The height of the metal projection of the present invention is 30 to 200 μm.
Is preferred. Further, it is preferable that the height of the prepreg formed by hollowing out the projection or the thermosetting resin formed by screen printing is the same as or slightly higher than the height of the projection. The area of the protrusion is substantially equal to or smaller than the area of the semiconductor chip. Generally, it is 5 to 20 mm square.

【００１０】金属板にはスルーホールよりやや大きめの
クリアランスホールを、エッチング、ドリル、打ち抜
き、UVレーザー等、公知の方法であける。具体的には、
該スルーホール壁と金属板クリアランスホール壁とは、
50μm以上の距離が、熱硬化性樹脂で絶縁されているこ
とが好ましい。一般には、70〜200μm である。表裏回
路導通用スルーホール径については、特に限定はない
が、クリアランスホールより小さい径で、一般には50〜
300μm である。A clearance hole slightly larger than the through hole is formed in the metal plate by a known method such as etching, drilling, punching, and UV laser. In particular,
The through hole wall and the metal plate clearance hole wall are:
It is preferable that the distance of 50 μm or more is insulated by a thermosetting resin. Generally, it is 70 to 200 μm. Although there is no particular limitation on the diameter of the through-hole for conducting the front and back circuits, the diameter is smaller than the clearance hole, generally 50 to
300 μm.

【００１１】金属板全体には、好適には積層成形前に表
面化学処理を施す。具体的には、黒色酸化処理、褐色処
理、薬品による表面粗化処理等、一般に公知の処理が行
なわれ得る。[0011] The entire metal plate is preferably subjected to a surface chemical treatment before lamination molding. Specifically, a generally known treatment such as a black oxidation treatment, a brown treatment, or a surface roughening treatment with a chemical may be performed.

【００１２】本発明で使用される熱硬化性樹脂組成物の
樹脂としては、一般に公知の熱硬化性樹脂が使用され
る。具体的には、エポキシ樹脂、多官能性シアン酸エス
テル樹脂、多官能性マレイミド−シアン酸エステル樹
脂、多官能性マレイミド樹脂、不飽和基含有ポリフェニ
レンエーテル樹脂等が挙げられ、１種或いは２種類以上
が組み合わせて使用される。耐熱性、耐湿性、耐マイグ
レーション性、吸湿後の電気的特性等の点から多官能性
シアン酸エステル樹脂組成物が好適である。As the resin of the thermosetting resin composition used in the present invention, generally known thermosetting resins are used. Specific examples include an epoxy resin, a polyfunctional cyanate ester resin, a polyfunctional maleimide-cyanate ester resin, a polyfunctional maleimide resin, and an unsaturated group-containing polyphenylene ether resin. Are used in combination. Polyfunctional cyanate ester resin compositions are preferred from the viewpoints of heat resistance, moisture resistance, migration resistance, electrical properties after moisture absorption, and the like.

【００１３】本発明の好適な熱硬化性樹脂分である多官
能性シアン酸エステル化合物とは、分子内に２個以上の
シアナト基を有する化合物である。具体的に例示する
と、1,3-又は1,4-ジシアナトベンゼン、1,3,5-トリシア
ナトベンゼン、1,3-、1,4-、1,6-、1,8-、2,6-又は2,7-
ジシアナトナフタレン、1,3,6-トリシアナトナフタレ
ン、4,4-ジシアナトビフェニル、ビス( 4-ジシアナトフ
ェニル) メタン、2,2-ビス（4-シアナトフェニル）プロ
パン、2,2-ビス( 3,5-ジブロモ-4- シアナトフェニル）
プロパン、ビス（4-シアナトフェニル）エーテル、ビス
（4-シアナトフェニル）チオエーテル、ビス（4-シアナ
トフェニル）スルホン、トリス（4-シアナトフェニル）
ホスファイト、トリス（4-シアナトフェニル）ホスフェ
ート、およびノボラックとハロゲン化シアンとの反応に
より得られるシアネート類などである。The polyfunctional cyanate compound which is a preferred thermosetting resin component of the present invention is a compound having two or more cyanato groups in a molecule. Specific examples include 1,3- or 1,4-dicyanatobenzene, 1,3,5-tricyanatobenzene, 1,3-, 1,4-, 1,6-, 1,8-, 2 , 6- or 2,7-
Dicyanatonaphthalene, 1,3,6-tricyanatonaphthalene, 4,4-dicyanatobiphenyl, bis (4-dicyanatophenyl) methane, 2,2-bis (4-cyanatophenyl) propane, 2,2- Bis (3,5-dibromo-4-cyanatophenyl)
Propane, bis (4-cyanatophenyl) ether, bis (4-cyanatophenyl) thioether, bis (4-cyanatophenyl) sulfone, tris (4-cyanatophenyl)
Phosphite, tris (4-cyanatophenyl) phosphate, and cyanates obtained by reacting novolak with cyanogen halide.

【００１４】これらのほかに特公昭41-1928 、同43-184
68、同44-4791 、同45-11712、同46-41112、同47-26853
及び特開昭51-63149等に記載の多官能性シアン酸エステ
ル化合物類も用いられ得る。また、これら多官能性シア
ン酸エステル化合物のシアナト基の三量化によって形成
されるトリアジン環を有する分子量400 〜6,000 のプレ
ポリマーが使用される。このプレポリマーは、上記の多
官能性シアン酸エステルモノマーを、例えば鉱酸、ルイ
ス酸等の酸類；ナトリウムアルコラート等、第三級アミ
ン類等の塩基；炭酸ナトリウム等の塩類等を触媒として
重合させることにより得られる。このプレポリマー中に
は一部未反応のモノマーも含まれており、モノマーとプ
レポリマーとの混合物の形態をしており、このような原
料は本発明の用途に好適に使用される。一般にはプレポ
リマーが可溶な有機溶剤に溶解させて使用する。In addition to these, Japanese Patent Publication Nos. 41-1928 and 43-184
68, 44-4791, 45-11712, 46-41112, 47-26853
And polyfunctional cyanate compounds described in JP-A-51-63149 and the like can also be used. In addition, a prepolymer having a molecular weight of 400 to 6,000 and having a triazine ring formed by trimerizing a cyanato group of these polyfunctional cyanate compounds is used. This prepolymer is obtained by polymerizing the above-mentioned polyfunctional cyanate ester monomer using, for example, an acid such as a mineral acid or a Lewis acid; a base such as a sodium alcoholate or a tertiary amine; a salt such as sodium carbonate as a catalyst. It can be obtained by: The prepolymer also contains some unreacted monomers and is in the form of a mixture of the monomer and the prepolymer, and such a raw material is suitably used for the purpose of the present invention. Generally, it is used by dissolving it in an organic solvent in which the prepolymer is soluble.

【００１５】エポキシ樹脂としては、一般に公知のもの
が使用できる。具体的には、液状或いは固形のビスフェ
ノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ
樹脂、フェノールノボラック型エポキシ樹脂、クレゾー
ルノボラック型エポキシ樹脂、脂環式エポキシ樹脂；ブ
タジエン、ペンタジエン、ビニルシクロヘキセン、ジシ
クロペンチルエーテル等の二重結合をエポキシ化したポ
リエポキシ化合物類；ポリオール、水酸基含有シリコン
樹脂類とエポハロヒドリンとの反応によって得られるポ
リグリシジル化合物類等が挙げられる。これらは１種或
いは２種類以上が組み合わせて使用され得る。As the epoxy resin, a generally known epoxy resin can be used. Specifically, liquid or solid bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, alicyclic epoxy resin; butadiene, pentadiene, vinylcyclohexene, dicyclopentyl ether, etc. And polyglycidyl compounds obtained by reacting a polyol, a hydroxyl group-containing silicone resin with an ephalohydrin, and the like. These may be used alone or in combination of two or more.

【００１６】ポリイミド樹脂としては、一般に公知のも
のが使用され得る。具体的には、多官能性マレイミド類
とポリアミン類との反応物、特公昭57-005406 に記載の
末端三重結合のポリイミド類が挙げられる。As the polyimide resin, generally known ones can be used. Specific examples include a reaction product of a polyfunctional maleimide and a polyamine, and a polyimide having a terminal triple bond described in JP-B-57-005406.

【００１７】これらの熱硬化性樹脂は、単独でも使用さ
れるが、特性のバランスを考え、適宜組み合わせて使用
するのが良い。These thermosetting resins may be used alone, but it is preferable to use them in an appropriate combination in consideration of the balance of properties.

【００１８】本発明の熱硬化性樹脂組成物には、組成物
本来の特性が損なわれない範囲で、所望に応じて種々の
添加物を配合することができる。これらの添加物として
は、不飽和ポリエステル等の重合性二重結合含有モノマ
ー類及びそのプレポリマー類；ポリブタジエン、エポキ
シ化ブタジエン、マレイン化ブタジエン、ブタジエン−
アクリロニトリル共重合体、ポリクロロプレン、ブタジ
エン−スチレン共重合体、ポリイソプレン、ブチルゴ
ム、フッ素ゴム、天然ゴム等の低分子量液状〜高分子量
のelastic なゴム類；ポリエチレン、ポリプロピレン、
ポリブテン、ポリ-4- メチルペンテン、ポリスチレン、
AS樹脂、ABS 樹脂、MBS 樹脂、スチレン−イソプレンゴ
ム、ポリエチレン−プロピレン共重合体、4-フッ化エチ
レン-6- フッ化エチレン共重合体類；ポリカーボネー
ト、ポリフェニレンエーテル、ポリスルホン、ポリエス
テル、ポリフェニレンサルファイド等の高分子量プレポ
リマー若しくはオリゴマー；ポリウレタン等が例示さ
れ、適宜使用される。また、その他、公知の無機或いは
有機の充填剤、染料、顔料、増粘剤、滑剤、消泡剤、分
散剤、レベリング剤、光増感剤、光沢剤、重合禁止剤、
チキソ性付与剤等の各種添加剤が、所望に応じて適宜組
み合わせて用いられる。必要により、反応基を有する化
合物は硬化剤、触媒が適宜配合される。Various additives can be added to the thermosetting resin composition of the present invention, if desired, as long as the inherent properties of the composition are not impaired. These additives include polymerizable double bond-containing monomers such as unsaturated polyesters and prepolymers thereof; polybutadiene, epoxidized butadiene, maleated butadiene, butadiene-
Low molecular weight liquid to high molecular weight elastic rubbers such as acrylonitrile copolymer, polychloroprene, butadiene-styrene copolymer, polyisoprene, butyl rubber, fluoro rubber, natural rubber; polyethylene, polypropylene,
Polybutene, poly-4-methylpentene, polystyrene,
AS resin, ABS resin, MBS resin, styrene-isoprene rubber, polyethylene-propylene copolymer, 4-fluoroethylene-6-fluoroethylene copolymers; polycarbonate, polyphenylene ether, polysulfone, polyester, polyphenylene sulfide, etc. High molecular weight prepolymers or oligomers; polyurethanes and the like are exemplified, and are appropriately used. In addition, other known inorganic or organic fillers, dyes, pigments, thickeners, lubricants, defoamers, dispersants, leveling agents, photosensitizers, brighteners, polymerization inhibitors,
Various additives such as a thixotropy-imparting agent are appropriately used in combination as needed. If necessary, the compound having a reactive group is appropriately blended with a curing agent and a catalyst.

【００１９】本発明の熱硬化性樹脂組成物は、それ自体
は加熱により硬化するが硬化速度が遅く、作業性、経済
性等に劣るため使用した熱硬化性樹脂に対して公知の熱
硬化触媒を用い得る。使用量は、熱硬化性樹脂100重量
部に対して0.005〜10重量部、好ましくは0.01〜５重量
部である。The thermosetting resin composition of the present invention can be cured by heating itself, but has a low curing rate and is inferior in workability and economic efficiency. Can be used. The amount used is 0.005 to 10 parts by weight, preferably 0.01 to 5 parts by weight, based on 100 parts by weight of the thermosetting resin.

【００２０】プリプレグの補強基材として、一般に公知
の無機或いは有機の織布、不織布が使用される。具体的
には、Ｅガラス、Ｓガラス、Ｄガラス等の公知のガラス
繊維布、全芳香族ポリアミド繊維布、液晶ポリエステル
繊維布等が挙げられる。これらは、混抄でも良い。ま
た、ポリイミドフィルム等のフィルムの表裏に熱硬化性
樹脂組成物を塗布、加熱して半硬化状態にしたものも使
用できる。As a reinforcing base material of the prepreg, generally known inorganic or organic woven or nonwoven fabric is used. Specific examples include known glass fiber cloths such as E glass, S glass, and D glass, wholly aromatic polyamide fiber cloths, and liquid crystal polyester fiber cloths. These may be mixed. Alternatively, a thermosetting resin composition applied to the front and back of a film such as a polyimide film and heated to a semi-cured state can be used.

【００２１】最外層の金属箔は、一般に公知のものが使
用できる。好適には厚さ３〜100μｍの銅箔、ニッケル
箔等が使用される。As the outermost metal foil, a generally known metal foil can be used. Preferably, a copper foil, nickel foil or the like having a thickness of 3 to 100 μm is used.

【００２２】本発明の多層プリント配線板用プリプレグ
を作成する場合、基材に熱硬化性樹脂組成物を含浸、乾
燥し、半硬化状態の積層材料とする。また基材を使用し
ない半硬化状態とした樹脂シート、銅箔に樹脂を塗布、
乾燥して半硬化したものも使用できる。或いは塗料も使
用できる。この場合、半硬化状態の程度により、ハイフ
ロー化、ローフロー化、或いはノーフロー化とする。ノ
ーフローとした場合、加熱、加圧して積層成形した時、
樹脂の流れ出しが100μｍ以下、好ましくは50μm以下と
する。また、この際、銅板、銅箔とは接着し、ボイドが
発生しないことが肝要である。ハイフローとした場合、
加熱、加圧して積層成形した場合の樹脂流れ出しが、２
mm以上、好ましくは10mm以上である。この中間の樹脂流
れは、ローフローと称する。加熱温度は一般的には100
〜180℃である。時間は5〜60分であり、目的とするフロ
ーの程度により、適宜選択する。When preparing a prepreg for a multilayer printed wiring board of the present invention, a base material is impregnated with a thermosetting resin composition and dried to obtain a semi-cured laminated material. In addition, resin is applied to semi-cured resin sheet and copper foil without using base material,
Dry and semi-cured products can also be used. Alternatively, paints can be used. In this case, depending on the degree of the semi-cured state, high flow, low flow, or no flow is used. In case of no flow, when heating and pressurizing and laminating,
The flow of the resin is 100 μm or less, preferably 50 μm or less. At this time, it is important that the copper plate and the copper foil adhere to each other and no void is generated. In the case of high flow,
Resin outflow when laminating by heating and pressing is 2
mm or more, preferably 10 mm or more. This intermediate resin flow is referred to as low flow. The heating temperature is generally 100
~ 180 ° C. The time is 5 to 60 minutes, and is appropriately selected depending on the desired flow rate.

【００２３】本発明の金属芯の入った半導体プラスチッ
クパッケージ用プリント配線板に用いる両面金属箔張積
層板の製造方法は以下（図１）の方法による。 (1) まず、内層となる金属板の片面に、半導体チップを
搭載する凸状の突起を形成する。突起の作成方法は前述
したが、いずれの方法でも良い。具体的には、全面を液
状エッチングレジストで被覆し、加熱して溶剤を除去し
た後、表面は半導体チップを固定する突起部のレジスト
が残るように作成したネガフィルムを被せ、裏面は全体
紫外線照射後、１％炭酸ナトリウム水溶液で未露光部分
を溶解除去し、エッチングにて金属板を所定厚み溶解し
てから、エッチングレジストを溶解除去する。再び液状
エッチングレジストで上下を被覆し、上側は金属突起部
をくり抜き、下側はくりぬきのないクリアランスホール
部以外の部分の光が遮断できるように作成したネガフィ
ルムをあて、紫外線で露光する。クリアランスホール部
のエッチングレジストを溶解除去してから、エッチング
法にて両側からエッチングし、クリアランスホールを作
成する。 (2) エッチングレジストを除去後、金属板全面を化学表
面処理し、金属突起部の部分よりやや大きめに孔をあけ
たノーフロー、又はローフローのプリプレグシートもし
くは樹脂層を上側に配置し、下側にはくりぬきのないハ
イフローのプリプレグシートもしくは樹脂層を配置して
から上下に金属箔を置く。 (3) 加熱、加圧、真空下に積層成形して金属芯入り両面
金属箔張積層板を作成する。この両面金属箔張積層板を
用いてプリント配線板を作成し、半導体チップを銀ペー
スト等の熱伝導性接着剤で固定し、ワイヤボンディン
グ、樹脂封止、ハンダボール付けを行なう。その工程
は、以下のように行なう。 (4) 所定の位置にドリル、或いはレーザー等でスルーホ
ールを内層金属箔に接触しないようにあけ、熱放散用ス
ルーホールは金属板に接続するようにあけ、デスミア処
理を施した後、金属メッキを行なう。公知の方法にて上
下に回路を作成すると同時に、好適には金属板突起部上
の金属箔を除去し、貴金属メッキを施し、内層金属板の
突起部の表面に半導体チップを接着する。その後、樹脂
封止を行ない、必要によりハンダボールを接着する。The method of manufacturing a double-sided metal foil-clad laminate used for a printed wiring board for a semiconductor plastic package having a metal core according to the present invention is as follows (FIG. 1). (1) First, a convex protrusion for mounting a semiconductor chip is formed on one surface of a metal plate serving as an inner layer. The method of forming the protrusions is described above, but any method may be used. Specifically, after coating the entire surface with a liquid etching resist and heating to remove the solvent, the front surface is covered with a negative film created so that the resist of the protrusion fixing the semiconductor chip remains, and the entire back surface is irradiated with ultraviolet rays. Thereafter, the unexposed portion is dissolved and removed with a 1% aqueous sodium carbonate solution, the metal plate is dissolved to a predetermined thickness by etching, and then the etching resist is dissolved and removed. The upper and lower portions are again covered with a liquid etching resist, the upper side is hollowed out by metal projections, and the lower side is exposed to ultraviolet light by applying a negative film formed so as to block light in the portions other than the clearance hole portion having no hollow. After dissolving and removing the etching resist in the clearance hole, etching is performed from both sides by an etching method to form a clearance hole. (2) After removing the etching resist, the entire surface of the metal plate is chemically surface-treated, and a no-flow or low-flow prepreg sheet or resin layer with holes slightly larger than the metal protrusions is placed on the upper side, and After placing a high-flow prepreg sheet or resin layer with no hollow, place metal foil on the top and bottom. (3) Laminate under heat, pressure and vacuum to form a double-sided metal foil-clad laminate with a metal core. A printed wiring board is prepared using the double-sided metal foil-clad laminate, the semiconductor chip is fixed with a heat conductive adhesive such as silver paste, and wire bonding, resin sealing, and soldering are performed. The process is performed as follows. (4) Use a drill or laser or the like to drill through holes at predetermined positions so that they do not come into contact with the inner metal foil, and drill through holes for heat dissipation so that they are connected to the metal plate. Perform At the same time as forming the upper and lower circuits by a known method, preferably, the metal foil on the metal plate protrusion is removed, noble metal plating is applied, and the semiconductor chip is bonded to the surface of the protrusion of the inner metal plate. Thereafter, resin sealing is performed, and solder balls are bonded as necessary.

【００２４】半導体から発生する熱は、直接搭載する金
属部分から金属板全体に熱伝導されるために、半導体チ
ップ直下以外の場所から、少なくとも該金属芯と下面の
金属パッドに接続するようにメッキされたスルーホール
を１個以上形成し、半導体チップからの熱がマザーボー
ドプリント配線板に拡散する構造とする。Since heat generated from the semiconductor is conducted from the metal part directly mounted to the entire metal plate, plating is performed from a location other than immediately below the semiconductor chip so as to connect at least to the metal core and the metal pad on the lower surface. One or more through holes are formed so that heat from the semiconductor chip is diffused to the motherboard printed wiring board.

【００２５】該突起とスルーホールが形成された金属板
の表面を公知の方法で酸化処理、微細凹凸形成、皮膜形
成等の接着性や電気絶縁性向上のための表面処理を必要
に応じて施す。該表面処理され、突起部とクリアランス
ホールが形成された金属板の、半導体チップを直接固定
する面以外は、すべて熱硬化性樹脂組成物で絶縁部を形
成する。熱硬化性樹脂組成物による絶縁部の形成は、基
材に熱硬化性樹脂組成物を含浸、乾燥し、積層成形した
時に、樹脂流れによって金属突起部に樹脂が流れ込まな
いように半硬化状態にしたローフロープリプレグ、フィ
ルム状シート等を用い、半導体チップを直接固定する突
起のある金属部分を、あらかじめプリプレグの部分を突
起部分よりやや大きめの孔を打ち抜き等によってあけて
おいたものを配置し、金属板の反対面には全面を覆うよ
うに、積層成形時にクリアランスホール内に樹脂が流れ
込んで、十分充填できる樹脂量、樹脂流れのハイフロー
プリプレグシート、樹脂シートを重ね、その外側に必要
により金属箔、或いは片面銅張積層板を置き、加熱、加
圧下に積層成形する。表面のプリプレグシート、フィル
ム状シートの厚みは金属突起の高さよりやや高めになる
ように作成する。加熱、加圧工程中に、熱により１度熔
融した半硬化状態の熱硬化性樹脂を、表面からは少な
く、裏面からは多く金属板のクリアランスホール内に流
し込んでクリアランスホールの中を埋め込むと同時に、
金属突起物の表面以外は熱硬化性樹脂組成物で一体化す
る。The surface of the metal plate on which the projections and the through holes are formed is subjected to a surface treatment for improving adhesiveness and electric insulation such as oxidation treatment, formation of fine irregularities, and formation of a film by a known method as necessary. . Except for the surface of the metal plate on which the projections and the clearance holes are formed and on which the semiconductor chip is directly fixed, the insulating portion is formed of a thermosetting resin composition. The formation of the insulating part by the thermosetting resin composition is performed by impregnating the base material with the thermosetting resin composition, drying, and forming the semi-cured state so that the resin does not flow into the metal protrusions due to the resin flow when the laminate is molded. Using a low-flow prepreg, a film-like sheet, etc., place a metal part with a protrusion that directly fixes the semiconductor chip, and punch a slightly larger hole in the prepreg part in advance than the protrusion part, etc. The resin flows into the clearance holes during lamination molding to cover the entire surface on the opposite side of the metal plate, and the amount of resin that can be sufficiently filled, a high-flow prepreg sheet with resin flow, and a resin sheet are stacked. Alternatively, a single-sided copper-clad laminate is placed and laminated under heat and pressure. The thickness of the prepreg sheet and the film-like sheet on the surface is made slightly higher than the height of the metal projections. During the heating and pressurizing steps, a small amount of the thermosetting resin that has been melted once by heat is poured from the front surface into the clearance hole of the metal plate with a small amount from the front surface and a large amount from the back surface. ,
Other than the surface of the metal protrusion is integrated with the thermosetting resin composition.

【００２６】また、無溶剤或いは溶剤タイプの熱硬化性
樹脂組成物を用い、スクリーン印刷等で該金属板突起場
所以外に塗布し、更には裏面も同様に塗布してから加熱
して半硬化状態とした後、このまま加熱して硬化する
か、加熱、加圧下に積層成形して一体化する。金属突起
部側の樹脂の半硬化状態は、積層成形した場合、ローフ
ロー或いはノーフローとなるように加熱して調整する。
裏面はハイフローとする。両外側に金属箔、或いは片面
銅張積層板を置き、加熱、加圧下に、好適には真空下に
積層成形する時に、上記と同様にクリアランスホール内
に樹脂を流し込むと同時に熱硬化させる。塗布、熱硬化
する場合、低圧にてクリアランスホールの中に樹脂を流
し込み、溶剤或いは空気を加熱しながら抜き、半硬化あ
るいは硬化させる。溶剤が入っている場合、クリアラン
スホール内の未充填が起こり易いため、あらかじめ無溶
剤液状の熱硬化性樹脂組成物クリアランスホールに流し
込み、硬化しておく方法が一般的である。いずれの方法
においても、金属板のクリアランスホール内を熱硬化性
樹脂組成物で充填されるように加工する。Further, using a non-solvent or solvent type thermosetting resin composition, apply by screen printing or the like to the portions other than the projections of the metal plate, and further apply the same on the back surface, and then heat to a semi-cured state. Then, it is cured by heating as it is, or is laminated and formed under heat and pressure to be integrated. The semi-cured state of the resin on the metal protrusion side is adjusted by heating so as to have a low-flow or no-flow when laminated and formed.
The back surface is high flow. A metal foil or a single-sided copper-clad laminate is placed on both outer sides, and when laminating under heat and pressure, preferably under vacuum, the resin is poured into the clearance holes and thermally cured at the same time as described above. In the case of application and thermal curing, a resin is poured into a clearance hole at a low pressure, and a solvent or air is removed while heating, and semi-cured or cured. When a solvent is contained, unfilling in the clearance hole is likely to occur. Therefore, a method of pouring into a solvent-free liquid thermosetting resin composition clearance hole in advance and curing the solvent is generally used. In either method, processing is performed so that the inside of the clearance hole of the metal plate is filled with the thermosetting resin composition.

【００２７】金属板の側面については、熱硬化性樹脂組
成物で埋め込まれている形、露出している形、いずれの
形でも良い。The side surface of the metal plate may be either a shape embedded with a thermosetting resin composition or an exposed shape.

【００２８】表裏回路形成時に、半導体チップ固定部分
の金属突起部分の表面にある金属箔も除去される。次い
で、ワイヤボンディング用の貴金属メッキを、少なくと
もワイヤボンディングパッド表面に形成してプリント配
線板を完成させる。この場合、貴金属メッキの必要のな
い箇所は、事前にメッキレジストで被覆しておく。ま
た、メッキ後に、必要により公知の熱硬化性樹脂組成
物、或いは光選択熱硬化性樹脂組成物で表面に被膜を形
成する。At the time of forming the front and back circuits, the metal foil on the surface of the metal projection portion of the semiconductor chip fixing portion is also removed. Next, a noble metal plating for wire bonding is formed on at least the surface of the wire bonding pad to complete the printed wiring board. In this case, a portion that does not require noble metal plating is covered with a plating resist in advance. After plating, if necessary, a film is formed on the surface with a known thermosetting resin composition or a photo-selective thermosetting resin composition.

【００２９】該プリント配線板の金属突起部分の表面に
接着剤や金属粉混合接着剤を用いて、半導体チップを固
定し、さらに半導体チップとプリント配線板回路のボン
ディングパッドとをワイヤボンディング法で接続し、少
なくとも、半導体チップ、ボンディングワイヤ、及びボ
ンディングパッドを公知の封止樹脂で封止する。A semiconductor chip is fixed to the surface of the metal projection portion of the printed wiring board using an adhesive or a metal powder mixed adhesive, and the semiconductor chip is connected to a bonding pad of a printed wiring board circuit by a wire bonding method. Then, at least the semiconductor chip, the bonding wires, and the bonding pads are sealed with a known sealing resin.

【００３０】半導体チップと反対面のソルダーボール接
続用導体パッドに、ソルダーボールを接続してP-BGA を
作り、マザーボードプリント配線板上の回路にソルダー
ボールを重ね、熱によってボールを熔融接続するか、ま
たはパッケージにソルダーボールをつけずにP-LGA を作
り、マザーボードプリント配線板に実装する時に、マザ
ーボードプリント配線板面に形成されたソルダーボール
接続用導体パッドとP-LGA 用のソルダーボール用導体パ
ッドとを、ソルダーボールを加熱熔融することにより接
続する。A solder ball is connected to the solder ball connecting conductor pad on the opposite side of the semiconductor chip to form a P-BGA, and the solder ball is superimposed on a circuit on a motherboard printed wiring board, and the ball is melt-connected by heat. When the P-LGA is made without attaching solder balls to the package, and mounted on the motherboard printed wiring board, the solder ball connection conductor pads formed on the motherboard printed wiring board surface and the solder ball conductors for the P-LGA The pads are connected by heating and melting the solder balls.

【００３１】[0031]

【実施例】以下に実施例、比較例で本発明を具体的に説
明する。尚、特に断らない限り『部』は重量部を表す。The present invention will be specifically described below with reference to examples and comparative examples. Unless otherwise specified, “parts” indicates parts by weight.

【００３２】実施例１ 2,2-ビス（4-シアナトフェニル）プロパン900部、ビス
（4-マレイミドフェニル）メタン100部を150℃に熔融さ
せ、攪拌しながら４時間反応させ、プレポリマーを得
た。これをメチルエチルケトンとジメチルホルムアミド
の混合溶剤に溶解した。これにビスフェノールＡ型エポ
キシ樹脂（商品名：エピコート1001、油化シェルエポキ
シ＜株＞製）400部、クレゾールノボラック型エポキシ
樹脂（商品名：ESCN- 220F、住友化学工業＜株＞製）60
0部を加え、均一に溶解混合した。更に触媒としてオク
チル酸亜鉛0.4部を加え、溶解混合し、これに無機充填
剤（商品名：焼成タルクBST-200 、日本タルク＜株＞
製）500部を加え、均一攪拌混合してワニスＡを得た。
このワニスを厚さ100μｍのガラス織布に含浸し150℃で
乾燥して、ゲル化時間（at170℃）７秒、170℃、20kgf/
cm2 、５分間での樹脂流れ110μm となるように作成し
た。厚さ105μｍの半硬化状態のローフロープリプレグ
（プリプレグＢ）を得た。また、145℃で乾燥し、ゲル
化時間（at170℃）120秒、樹脂流れ13mm、厚さ107μｍ
のハイフロープリプレグ（プリプレグＣ）を作成した。
一方、内層金属板となる厚さ200μｍのCu：97/3％ 、F
e:2.5％ 、P:0.1 ％、Zn:0.07 ％、Pb:0.03 ％よりな
る合金を用意し、大きさ50mm角のパッケージの中央に13
mm角、高さ100μｍの突起をエッチング法にて形成し
た。その後、該金属板の全面に液状エッチングレジスト
を厚さ25μm塗布し、乾燥して溶剤を飛ばした後、突起
部をくり抜いたネガフィルムを重ね、さらに下側には全
面ネガフィルムをあて、クリアランスホール以外を紫外
線照射してからクリアランスホール部のレジスト膜を1
％炭酸ナトリウム水溶液で除去した後、両側からエッチ
ングによって0.6mmφのクリアランスホールをあけた。
金属板全面に黒色酸化銅処理を施し、この上面には、突
起部分に相当する位置に、突起部より50μm 大きめの孔
をパンチングにてあけた上記プリプレグＢを被せ、下側
にはプリプレグＣを置き、その両外側に厚さ12μmの電
解銅箔を配置し、200℃、20kgf/cm2 、30mmHg以下の真
空下で２時間積層形成し、一体化して両面銅張積層板を
得た。クリアランスホール箇所は、クリアランスホール
部の金属に接触しないように、中央に孔径0.25mmのスル
ーホールをレーザーにてあけ、熱放散箇所は、４隅に金
属板に直接接触するように孔径0.25mmのスルーホールを
あけ、デスミア処理後、銅メッキを無電解、電解メッキ
で行ない、孔内に18μmの銅メッキ層を形成した。表裏
に液状エッチングレジストを塗布、乾燥してからポジフ
ィルムを重ねて露光、現像し、表裏回路を形成するとと
もに、突起部上の銅箔も同時にエッチング除去した。突
起部、ボンディングパッド及びボールパッド以外にメッ
キレジストを形成し、ニッケル、金メッキを施してプリ
ント配線板を完成した。突起部に大きさ13mm角の半導体
チップを銀ペーストで接着固定した後、ワイヤボンディ
ングを行ない、次いでシリカ入りエポキシ封止用コンパ
ウンドを用い、トランスファーモールドにて樹脂封止
し、ハンダボールを付けて半導体パッケージを作成した
（図１）。これをエポキシ樹脂マザーボードプリント配
線板にハンダボールを熔融して接続した。評価結果を表
１に示す。Example 1 900 parts of 2,2-bis (4-cyanatophenyl) propane and 100 parts of bis (4-maleimidophenyl) methane were melted at 150 ° C., and reacted with stirring for 4 hours to prepare a prepolymer. Obtained. This was dissolved in a mixed solvent of methyl ethyl ketone and dimethylformamide. 400 parts of bisphenol A type epoxy resin (trade name: Epicoat 1001, Yuka Shell Epoxy Co., Ltd.) and cresol novolac type epoxy resin (trade name: ESCN-220F, Sumitomo Chemical Co., Ltd.) 60
0 parts were added and uniformly dissolved and mixed. Further, 0.4 part of zinc octylate is added as a catalyst, and the mixture is dissolved and mixed, and an inorganic filler (trade name: calcined talc BST-200, Nippon Talc Co., Ltd.) is added.
Varnish A was obtained by mixing uniformly with stirring.
This varnish is impregnated with a glass woven fabric having a thickness of 100 μm and dried at 150 ° C., and the gel time (at 170 ° C.) is 7 seconds, 170 ° C., 20 kgf /
The resin was formed so as to have a resin flow of 110 μm in 5 minutes in cm 2 . A semi-cured low-flow prepreg (prepreg B) having a thickness of 105 μm was obtained. Also dried at 145 ° C, gel time (at 170 ° C) 120 seconds, resin flow 13mm, thickness 107μm
Was prepared (prepreg C).
On the other hand, a 200 μm thick Cu serving as an inner metal plate: 97/3%, F
Prepare an alloy consisting of e: 2.5%, P: 0.1%, Zn: 0.07%, Pb: 0.03%, in the center of a 50mm square package.
A protrusion of mm square and a height of 100 μm was formed by an etching method. After that, a liquid etching resist having a thickness of 25 μm was applied to the entire surface of the metal plate, dried, and the solvent was blown off. Irradiate the resist film in the clearance hole with 1
After removal with an aqueous sodium carbonate solution, a clearance hole of 0.6 mmφ was made from both sides by etching.
A black copper oxide treatment is applied to the entire surface of the metal plate, and the prepreg B, which is formed by punching a hole 50 μm larger than the protrusion at the position corresponding to the protrusion, is placed on the upper surface, and the prepreg C is placed on the lower side. Then, a 12 μm-thick electrolytic copper foil was placed on both outer sides thereof, and laminated at 200 ° C., 20 kgf / cm 2 , and a vacuum of 30 mmHg or less for 2 hours, and integrated to obtain a double-sided copper-clad laminate. In the clearance hole area, a 0.25 mm through hole with a hole diameter of 0.25 mm is drilled with a laser so that it does not come into contact with the metal in the clearance hole, and the heat dissipation point is 0.25 mm in diameter so that the four corners are in direct contact with the metal plate. A through hole was opened, and after desmearing, copper plating was performed by electroless and electrolytic plating to form a copper plating layer of 18 μm in the hole. After applying and drying a liquid etching resist on the front and back, a positive film was overlaid and exposed and developed to form a front and back circuit, and the copper foil on the protruding portions was simultaneously etched away. A plating resist was formed on the portions other than the protruding portions, the bonding pads and the ball pads, and nickel and gold plating were applied to complete the printed wiring board. After bonding a semiconductor chip with a size of 13 mm on the protruding part with silver paste, wire bonding is performed, then using a compound for epoxy sealing with silica, resin-sealing with transfer molding, and attaching a solder ball. A package was created (Figure 1). This was connected to an epoxy resin mother board printed wiring board by melting solder balls. Table 1 shows the evaluation results.

【００３３】実施例２ プリプレグＣを１枚用い、片面に12μmの電解銅箔、片
面に離型フィルムを配置し、200℃、20kgf/cm2 にて２
時間積層成形して片面銅張積層板を作成した。内層とな
る、厚さ200μｍ の圧延銅板を実施例１と同様に加工し
て、片面に同じ大きさ、高さの突起を作成した。更に0.
6mmφのクリアランスホールをあけ、実施例１のワニス
Ａをスクリーン印刷にて、金属突起部に樹脂が付着しな
いようにし、表裏に交互に塗布、乾燥を３回繰り返し、
厚さ105μｍの樹脂層を形成した。表層の樹脂層のゲル
化時間は5〜10秒(at170℃）でローフロー状態とし、裏
側の樹脂層のゲル化時間は60■70秒でハイフローとし
た。この両側に上記で得た片面銅張積層板を置き、同一
条件で積層成形して両面銅張積層板を作成した。クリア
ランスホール箇所は、クリアランスホール部の金属に接
続しないように、ドリルにて中央に孔径0.20mmのスルー
ホールをドリルであけ、熱放散箇所は、４隅に内層銅板
に直接接触するように同様にドリルであけ、デスミア
後、銅メッキを無電解、電解メッキにて行ない、孔内に
17μmの銅メッキ層を形成した。表裏に液状エッチング
レジストを塗布、乾燥して溶剤を除去してからポジフィ
ルムを重ねて、露光、現像してから、表裏回路を形成し
た。突起部上の積層板部、ボンディングパッド及びボー
ルパッド部以外にメッキレジストを形成し、ニッケル、
金メッキを施してから、中央銅板突起部上の積層板部の
基材をルーターで切削除去し、プリント配線板を完成し
た。ルーターで切削除去した金属突起部の上への樹脂流
れ込みを見たが、20μｍ以下であった。また、クリアラ
ンスホールの断面を見たが、ボイドは見られなかった。
その後、同様に半導体チップを接着、樹脂封止、ハンダ
ボールを接続して半導体パッケージとした。これを同様
にマザーボードプリント配線板に接続した。評価結果を
表１に示す。[0033] Example 2 using 1 prepregs C, placing the release film electrodeposited copper foil of 12μm on one side, on one side, 200 ° C., 20 kgf / cm 2 at 2
A single-sided copper-clad laminate was prepared by lamination molding for a time. A rolled copper plate having a thickness of 200 μm as an inner layer was processed in the same manner as in Example 1 to form a protrusion having the same size and height on one surface. 0.
A clearance hole of 6 mmφ was made, and the varnish A of Example 1 was screen-printed to prevent the resin from adhering to the metal protrusions, and alternately applied and dried three times on both sides,
A resin layer having a thickness of 105 μm was formed. The gelling time of the surface resin layer was in a low flow state at 5 to 10 seconds (at 170 ° C.), and the gelling time of the resin layer on the back side was in a high flow state of 60 to 70 seconds. The single-sided copper-clad laminate obtained above was placed on both sides and laminated and formed under the same conditions to prepare a double-sided copper-clad laminate. Drill a through hole with a hole diameter of 0.20 mm in the center with a drill so that the clearance hole part is not connected to the metal of the clearance hole part, and the heat dissipation point is also so as to directly contact the inner copper plate at the four corners Drill, desmear, copper plating by electroless and electrolytic plating
A 17 μm copper plating layer was formed. After applying a liquid etching resist on the front and back and drying to remove the solvent, a positive film was overlaid, exposed and developed, and then a front and back circuit was formed. A plating resist is formed on a portion other than the laminated plate portion, the bonding pad and the ball pad portion on the protrusion, and nickel,
After gold plating, the base material of the laminated board portion on the central copper plate projection was cut and removed by a router to complete a printed wiring board. It was observed that the resin flowed into the metal projections cut and removed by the router, but it was 20 μm or less. When the cross section of the clearance hole was viewed, no void was found.
Thereafter, similarly, the semiconductor chip was bonded, resin-sealed, and solder balls were connected to form a semiconductor package. This was similarly connected to a motherboard printed wiring board. Table 1 shows the evaluation results.

【００３２】比較例１ 実施例１のプリプレグＣを２枚使用し、上下に18μｍの
電解銅箔を配置し、200℃、20kgf/cm2、真空下に２時間
積層成形し、両面銅張積層板を得た。所定の位置に孔径
0.25mmφのスルーホールをドリルであけ、デスミア処理
後に銅メッキを施した。この板の上下に公知の方法で回
路を形成し、メッキレジストを施し、ニッケルメッキ、
金メッキを付けた。これは半導体チップを搭載する箇所
の下に放熱用のスルーホールが形成されており、この上
に銀ペーストで半導体チップを接着し、ワイヤボンディ
ング後、エポキシ封止用コンパウンドで実施例１と同様
に樹脂封止し、ハンダボールを付けた（図３）。また同
様にマザーボードに接続した。この半導体プラスチック
パッケージの評価結果を表１に示す。Comparative Example 1 Two prepregs C of Example 1 were used, and 18 μm electrolytic copper foils were arranged on the upper and lower sides, and were laminated and molded at 200 ° C., 20 kgf / cm 2 under vacuum for 2 hours, and then double-sided copper-clad laminated I got a board. Hole diameter in place
A 0.25 mmφ through-hole was drilled and copper plated after desmearing. Circuits are formed on the top and bottom of this plate by a known method, plating resist is applied, nickel plating,
Gold plated. This has a through hole for heat radiation formed under the place where the semiconductor chip is mounted. The semiconductor chip is bonded with a silver paste on this, the wire bonding is performed, and the epoxy sealing compound is used as in the first embodiment. It was sealed with resin and solder balls were attached (FIG. 3). Also connected to the motherboard in the same way. Table 1 shows the evaluation results of the semiconductor plastic package.

【００３５】比較例２ エポキシ樹脂（商品名：エピコート1045）500部、及び
エポキシ樹脂（商品名：ESCN220F）500部、ジシアンジ
アミド300部、2-エチルイミダゾール２部をメチルエチ
ルケトンとジメチルホルムアミドの混合溶剤に溶解し、
これを厚さ100μｍのガラス織布に含浸させて、ゲル化
時間（at170℃）10秒、樹脂流れ98μmのノーフロープリ
プレグ（プリプレグＤ）、ゲル化時間150 秒、樹脂流れ
18mmのハイフロープリプレグ（プリプレグＥ）を作成し
た。プリプレグＥを２枚使用し、170℃、20kgf/cm2 、3
0mmHgの真空下で２時間積層成形して両面銅張積層板を
作成した。後は比較例１と同様にプリント配線板を作成
し、半導体チップ搭載部分をザグリマシーンにてくり抜
いてから、裏面に厚さ200μｍの銅板を、上記ノーフロ
ープリプレグＤを打ち抜いたものを使用して、加熱、加
圧下に同様に接着させ、放熱板付きプリント配線板を作
成した。これはややソリが発生した。この放熱板に直接
銀ペーストで半導体チップを接着させ、ワイヤボンディ
ングで接続後、液状エポキシ樹脂で封止し、金属張り合
わせ面とは反対側の面にハンダボールを付けた（図
４）。同様にハンダボールを用いてマザーボードに接続
した。この半導体プラスチックパッケージの評価結果を
表１に示す。Comparative Example 2 500 parts of an epoxy resin (trade name: Epikote 1045), 500 parts of an epoxy resin (trade name: ESCN220F), 300 parts of dicyandiamide, and 2 parts of 2-ethylimidazole were dissolved in a mixed solvent of methyl ethyl ketone and dimethylformamide. And
This is impregnated with a glass woven fabric having a thickness of 100 μm, gelling time (at 170 ° C.) for 10 seconds, no-flow prepreg (prepreg D) having a resin flow of 98 μm, gelling time of 150 seconds, resin flowing
An 18 mm high flow prepreg (prepreg E) was prepared. Using two prepregs E, 170 ° C, 20kgf / cm 2 , 3
Laminate molding was performed for 2 hours under a vacuum of 0 mmHg to prepare a double-sided copper-clad laminate. After that, a printed wiring board was prepared in the same manner as in Comparative Example 1, and a semiconductor chip mounting portion was cut out with a counterbore machine, and a copper plate having a thickness of 200 μm was punched out on the back surface using the above-mentioned no-flow prepreg D. Then, they were similarly bonded under heat and pressure to prepare a printed wiring board with a heat sink. This slightly warped. A semiconductor chip was directly bonded to the heat sink with a silver paste, connected by wire bonding, sealed with a liquid epoxy resin, and a solder ball was attached to the surface opposite to the metal bonding surface (FIG. 4). Similarly, it was connected to the motherboard using solder balls. Table 1 shows the evaluation results of the semiconductor plastic package.

【００３６】＜測定方法＞ １）吸湿後の耐熱性・ JEDEC STANDARD TEST METHOD A113-A LEVEL3:30℃・60
％RHで所定時間処理後、220℃リフローソルダー３サイ
クル後の基板の異常の有無について、断面観察及び電気
的チェックによって確認した。 ２）吸湿後の電気絶縁性・ JEDEC STANDARD TEST METHOD A113-A LEVEL2:85℃・60
％RHで所定時間(Max.168hrs.) 処理後、220℃リフロー
ソルダー３サイクル後の基板の異常の有無を断面観察及
び電気的チェックによって確認した。 ３）ガラス転移温度 DMA 法にて測定した。 ４）プレッシャークッカー処理後の絶縁抵抗値 端子間（ライン／スペース＝70/70μｍ）の櫛形パター
ンを作成し、この上に、それぞれ使用したプリプレグを
配置して同様に積層成形したものを、121℃・２気圧で
所定時間処理した後、25℃・60％RHにて２時間後処理を
行い、500VDC印加60秒後に、その端子間の絶縁抵抗値を
測定した。 ５）耐マイグレーション性 上記4)の試験片を用い、85℃・85％RHにて、50VDC印加
して端子間の絶縁抵抗値を測定した。 ６）放熱性 パッケージを同一マザーボードプリント配線板にハンダ
ボールで接続させ、1000時間連続使用してから、パッケ
ージの温度を測定した。<Measurement method> 1) Heat resistance after moisture absorption ・ JEDEC STANDARD TEST METHOD A113-A LEVEL3: 30 ° C ・ 60
After the treatment at% RH for a predetermined time, the presence or absence of abnormality in the substrate after three cycles of reflow soldering at 220 ° C. was confirmed by cross-sectional observation and electrical check. 2) Electric insulation after moisture absorption ・ JEDEC STANDARD TEST METHOD A113-A LEVEL2: 85 ℃ ・ 60
After processing at% RH for a predetermined time (Max. 168 hrs.), The presence or absence of abnormality in the substrate after three cycles of reflow soldering at 220 ° C. was confirmed by cross-sectional observation and electrical check. 3) Glass transition temperature Measured by the DMA method. 4) Insulation resistance value after pressure cooker treatment A comb-shaped pattern between terminals (line / space = 70/70 μm) was prepared, and the prepregs used were arranged on each of them and laminated and molded in the same manner at 121 ° C. After the treatment at 2 atm for a predetermined time, the post-treatment was performed at 25 ° C. and 60% RH for 2 hours, and the insulation resistance value between the terminals was measured after application of 500 VDC for 60 seconds. 5) Migration resistance Using the test piece of the above 4), 50 VDC was applied at 85 ° C. and 85% RH, and the insulation resistance value between the terminals was measured. 6) Heat dissipation The package was connected to the same motherboard printed wiring board with solder balls and used continuously for 1000 hours, and then the temperature of the package was measured.

【００３７】[0037]

【表１】 [Table 1]

【００３８】[0038]

【発明の効果】プリント配線板の厚さ方向のほぼ中央
に、プリント配線板とほぼ同じ大きさの金属板を配置
し、プリント配線板の片面に、少なくとも、１個以上の
金属板の突起を露出させ、この上に半導体チップを固定
し、半導体回路導体をその周囲のプリント配線板表面に
形成された回路導体とワイヤボンディングで接続し、少
なくとも、該表面のプリント配線板上の信号伝播回路導
体が、プリント配線板の反対面に形成された回路導体も
しくは該ハンダボールでの接続用導体パッドとスルーホ
ール導体で結線し、半導体チップが樹脂封止されている
構造の半導体プラスチックパッケージ用プリント配線板
に用いる両面銅張積層板の製造方法において、（１）
内層に用いる金属板の片面に半導体チップを搭載する凸
状の突起を形成し、表裏回路導体導通用スルーホールを
形成するための、スルーホールよりも大きめのクリアラ
ンスホールをあけ、（２） 金属突起部のある側のプリ
プレグシートは、突起の位置に、その面積よりやや大き
めの孔を形成したローフロー、又はノーフローのプリプ
レグシートもしくは樹脂層を配置し、その反対側にはク
リアランスホールを埋め込むに十分な樹脂量と樹脂流れ
を有するハイフローのプリプレグシートもしくは樹脂層
を配置し、その両外側に金属箔、或いは片面銅張積層板
を配置して、（３） 加熱、加圧下に、好ましくは真空
下に一体化し、金属芯入り両面銅張積層板を作成する。
プリプレグシート或いは塗布する樹脂層に使用する熱硬
化性樹脂として多官能性シアン酸エステル樹脂組成物を
用いることにより、得られた両面銅張積層板を用いて作
成されたプリント配線板に半導体チップを固定し、ワイ
ヤボンディング、樹脂封止して製造されたパッケージ
は、半導体チップの下面からの吸湿がなく、吸湿後の耐
熱性、すなわちポップコーン現象が大幅に改善できると
ともに、信頼性も良好で、熱放散性も改善でき、加えて
大量生産にも適しており、経済性の改善された、新規な
構造の半導体プラスチックパッケージを得ることができ
た。According to the present invention, a metal plate having substantially the same size as the printed wiring board is disposed substantially at the center of the printed wiring board in the thickness direction, and at least one metal plate projection is formed on one side of the printed wiring board. A semiconductor chip is fixed thereon, and the semiconductor circuit conductor is connected to the circuit conductor formed on the surface of the printed wiring board by wire bonding, and at least the signal propagation circuit conductor on the printed wiring board on the surface is fixed. Is connected to a circuit conductor formed on the opposite surface of the printed wiring board or a conductor pad for connection with the solder ball through a through-hole conductor, and the semiconductor chip is sealed with resin. The method for producing a double-sided copper-clad laminate used for (1)
A convex protrusion for mounting a semiconductor chip is formed on one surface of a metal plate used as an inner layer, and a clearance hole larger than the through hole is formed for forming a through hole for conducting a front and back circuit conductor. (2) Metal protrusion The prepreg sheet on the side where the part is located is provided with a low-flow or no-flow prepreg sheet or resin layer in which holes slightly larger than the area of the prepreg sheet are formed at the positions of the protrusions, and the opposite side is sufficient to embed clearance holes. A high-flow prepreg sheet or resin layer having a resin flow and a resin flow is disposed, and a metal foil or a single-sided copper-clad laminate is disposed on both outer sides of the prepreg sheet or a resin layer. (3) Under heat and pressure, preferably under vacuum Integrated into a double-sided copper-clad laminate with a metal core.
By using a polyfunctional cyanate resin composition as a thermosetting resin used for a prepreg sheet or a resin layer to be applied, a semiconductor chip can be formed on a printed wiring board prepared using the obtained double-sided copper-clad laminate. The package manufactured by fixing, wire bonding, and resin sealing does not absorb moisture from the lower surface of the semiconductor chip, and can significantly improve the heat resistance after moisture absorption, that is, the popcorn phenomenon, and has good reliability and heat resistance. It was possible to obtain a semiconductor plastic package having a novel structure, which has improved heat dissipation, is suitable for mass production, and has improved economy.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の両面金属箔張積層板の製造工程及びそ
れを用いた半導体プラスチックパッケージを示す説明図
である。FIG. 1 is an explanatory view showing a manufacturing process of a double-sided metal foil-clad laminate of the present invention and a semiconductor plastic package using the same.

【図２】いろいろな片面凸形状の内層金属板を示す説明
図である。FIG. 2 is an explanatory view showing various inner-layer metal plates having a convex shape on one side.

【図３】比較例１の半導体プラスチックパッケージ製造
工程を示す説明図である。FIG. 3 is an explanatory view showing a semiconductor plastic package manufacturing process of Comparative Example 1.

【図４】比較例２の半導体プラスチックパッケージ製造
工程を示す説明図である。FIG. 4 is an explanatory view showing a semiconductor plastic package manufacturing process of Comparative Example 2.

【符号の説明】[Explanation of symbols]

(a) 金属板 (b) 金属箔 (c) ローフロープリプレグシートＢ (d) ハイフロープリプレグシートＣ (e) 封止樹脂 (f) 金ワイヤ (g) 半導体チップ (h) 熱伝導性ペースト (i) ハンダボール (j) 表裏回路導通スルーホール (k) メッキレジスト (l) 熱放散用スルーホール (m) ノーフロープリプレグシートＤ (a) Metal plate (b) Metal foil (c) Low flow prepreg sheet B (d) High flow prepreg sheet C (e) Encapsulation resin (f) Gold wire (g) Semiconductor chip (h) Thermal conductive paste (i ) Solder ball (j) Front and back circuit conduction through hole (k) Plating resist (l) Heat dissipation through hole (m) No-flow prepreg sheet D

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 プリント配線板の厚さ方向のほぼ中央
に、プリント配線板とほぼ同じ大きさの内層金属板を配
置し、プリント配線板の片面に、少なくとも、１個以上
の金属板の突起を露出し、この上に半導体チップを固定
し、半導体チップをその周囲のプリント配線板表面に形
成された回路導体とワイヤボンディングで接続し、少な
くとも、該表面のプリント配線板上の信号伝播回路導体
を、プリント配線板の反対面に形成された回路導体もし
くは該ハンダボールでの接続用導体パッドとメッキされ
たスルーホール導体で結線し、半導体チップを樹脂封止
している構造の半導体プラスチックパッケージ用両面金
属箔張積層板の製造方法において、 (1) 内層に用いる金属板を用意し、金属板の片面に半
導体チップを搭載する凸状の突起を形成し、表裏回路導
体導通用スルーホールを形成するための、スルーホール
の径よりも大きいクリアランスホールをあけ、 (2) 金属突起部のある側のプリプレグシートは、突起
の位置に、その面積よりやや大きめの孔を形成したロー
フロー、又はノーフローのプリプレグシートもしくは樹
脂層を配置し、その反対側にはクリアランスホールを埋
め込むに十分な樹脂量と樹脂流れを有するハイフローの
プリプレグシートもしくは樹脂層を配置し、その両外側
に金属箔、或いは片面金属箔張積層板を配置して、 （3) 加熱、加圧下に、好ましくは真空下に積層成形
して一体化し、金属芯入り両面金属箔張積層板とする、
ことを特徴とする半導体プラスチックパッケージ用両面
金属箔張積層板の製造方法。An inner-layer metal plate having substantially the same size as the printed wiring board is disposed at substantially the center in the thickness direction of the printed wiring board, and at least one metal plate projection is provided on one surface of the printed wiring board. Is exposed, a semiconductor chip is fixed thereon, and the semiconductor chip is connected to a circuit conductor formed on the surface of the printed wiring board by wire bonding, and at least a signal propagation circuit conductor on the printed wiring board on the surface is fixed. Is connected to a circuit conductor formed on the opposite surface of the printed wiring board or a conductor pad for connection with the solder ball and a plated through-hole conductor, and the semiconductor chip is sealed with a resin for a semiconductor plastic package. In the method for manufacturing a double-sided metal foil-clad laminate, (1) preparing a metal plate used for the inner layer, forming a convex projection for mounting a semiconductor chip on one surface of the metal plate, Drill a clearance hole larger than the diameter of the through-hole to form a through-hole for conducting the back circuit conductor. (2) The prepreg sheet on the side with the metal protrusion is slightly larger than the area of the prepreg sheet at the position of the protrusion. A low-flow or no-flow prepreg sheet or resin layer with holes formed is arranged, and a high-flow prepreg sheet or resin layer having a sufficient amount of resin and resin flow to bury the clearance holes is arranged on the opposite side, and both of them are arranged. A metal foil or a single-sided metal foil-clad laminate is disposed on the outside, and (3) a laminate is formed by laminating under heat and pressure, preferably under vacuum, and integrated to form a double-sided metal foil-clad laminate with a metal core.
A method for producing a double-sided metal foil-clad laminate for a semiconductor plastic package. 【請求項２】 該金属板及び表層の回路用金属が銅の含
有率95％以上の合金、或いは純銅である請求項１記載の
両面金属箔張積層板の製造方法。2. The method for producing a double-sided metal foil-clad laminate according to claim 1, wherein the metal plate and the circuit metal of the surface layer are an alloy having a copper content of 95% or more, or pure copper. 【請求項３】 該絶縁樹脂組成物が、多官能性シアン酸
エステル、該シアン酸エステルプレポリマーを必須成分
とする熱硬化性樹脂組成物である請求項１記載の両面金
属箔張積層板の製造方法。3. The double-sided metal foil-clad laminate according to claim 1, wherein the insulating resin composition is a thermosetting resin composition containing a polyfunctional cyanate ester and the cyanate ester prepolymer as essential components. Production method.
JP3423698A 1997-12-10 1998-01-30 Manufacture of laminated plate with metal core with both sides lined with metal foil for semiconductor plastic package Pending JPH11220066A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP3423698A JPH11220066A (en) 1998-01-30 1998-01-30 Manufacture of laminated plate with metal core with both sides lined with metal foil for semiconductor plastic package
US09/207,115 US6376908B1 (en) 1997-12-10 1998-12-08 Semiconductor plastic package and process for the production thereof
EP98310022A EP0926729A3 (en) 1997-12-10 1998-12-08 Semiconductor plastic package and process for the production thereof
KR1019980054122A KR19990062959A (en) 1997-12-10 1998-12-10 Semiconductor plastic package and manufacturing method thereof
US10/036,385 US6720651B2 (en) 1997-12-10 2002-01-07 Semiconductor plastic package and process for the production thereof
US10/790,039 US20040171189A1 (en) 1997-12-10 2004-03-02 Semiconductor plastic package and process for the production thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3423698A JPH11220066A (en) 1998-01-30 1998-01-30 Manufacture of laminated plate with metal core with both sides lined with metal foil for semiconductor plastic package

Publications (1)

Publication Number Publication Date
JPH11220066A true JPH11220066A (en) 1999-08-10

Family

ID=12408532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3423698A Pending JPH11220066A (en) 1997-12-10 1998-01-30 Manufacture of laminated plate with metal core with both sides lined with metal foil for semiconductor plastic package

Country Status (1)

Country Link
JP (1) JPH11220066A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7394491B2 (en) 2003-01-13 2008-07-01 Magnachip Semiconductor, Ltd. Image sensor having clamp circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7394491B2 (en) 2003-01-13 2008-07-01 Magnachip Semiconductor, Ltd. Image sensor having clamp circuit

Similar Documents

Publication Publication Date Title
WO1999059205A1 (en) Semiconductor plastic package and method for producing printed wiring board
JPH11176973A (en) Semiconductor plastic package
JPH11214572A (en) Manufacture of double-sided metal-clad multi-layer board with metal core
JP3985342B2 (en) Semiconductor plastic package
JP3852510B2 (en) Semiconductor plastic package
JPH11220066A (en) Manufacture of laminated plate with metal core with both sides lined with metal foil for semiconductor plastic package
JP2000150714A (en) Printed wiring board for semiconductor plastic package
JP4022972B2 (en) Semiconductor plastic package
JP2001007533A (en) Manufacture of ball grid array printed wiring board excellent in heat dissipating property
JPH11195745A (en) Multi-chip plastic package
JPH11220064A (en) Small-sized semiconductor plastic package
JPH11220068A (en) Manufacture of laminated plate with metal core with both sides lined with metal foil for semiconductor plastic package
JPH11238827A (en) Manufacture of metal core
JPH11220063A (en) Outer-periphery lower part heat dissipating semiconductor plastic package
JPH11220061A (en) Cavity-type semiconductor plastic package
JP2000260901A (en) Multilayer printed wiring board for metal core semiconductor plastic package
JP2000150715A (en) Manufacture of copper clad plate for metallic plate- loaded printed wiring board
JP2005085783A (en) Ball-grid-array plastic semiconductor package
JPH11214574A (en) Manufacture of double-sided metal-cald laminated board with metallic core
JP2000077567A (en) Manufacture of printed wiring board
JPH11220062A (en) Periphery heat dissipation type of semiconductor plastic package
JPH11204686A (en) Semiconductor plastic package
JPH11220065A (en) Semiconductor plastic package
JP2000315749A (en) Printed wiring board for metal core-containing ball grid array type semiconductor plastic package
JPH11214563A (en) Semiconductor plastic package