JPH11195745A - Multi-chip plastic package - Google Patents

Multi-chip plastic package

Info

Publication number
JPH11195745A
JPH11195745A JP10000975A JP97598A JPH11195745A JP H11195745 A JPH11195745 A JP H11195745A JP 10000975 A JP10000975 A JP 10000975A JP 97598 A JP97598 A JP 97598A JP H11195745 A JPH11195745 A JP H11195745A
Authority
JP
Japan
Prior art keywords
semiconductor chip
metal plate
metal
wiring board
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10000975A
Other languages
Japanese (ja)
Inventor
Kozo Yamane
康三 山根
Morio Take
杜夫 岳
Nobuyuki Ikeguchi
信之 池口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Gas Chemical Co Inc
Original Assignee
Mitsubishi Gas Chemical Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Gas Chemical Co Inc filed Critical Mitsubishi Gas Chemical Co Inc
Priority to JP10000975A priority Critical patent/JPH11195745A/en
Priority to EP98310022A priority patent/EP0926729A3/en
Priority to US09/207,115 priority patent/US6376908B1/en
Priority to KR1019980054122A priority patent/KR19990062959A/en
Priority to TW87120501A priority patent/TW401723B/en
Publication of JPH11195745A publication Critical patent/JPH11195745A/en
Priority to US10/036,385 priority patent/US6720651B2/en
Priority to US10/790,039 priority patent/US20040171189A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve popcorn phenomenon and heat dissipation characteristics by insulating a metal plate, wherein one or more through-hole diameters are opened and hole walls with resin composition material, exposing a part of the inner-layer metal, which has the approximately same size as a semiconductor chip thereby fixing the semiconductor chip on the surface and exposing the protruding surface of the metal plate in thermal diffusion at a part of of the surface of the opposite side. SOLUTION: The surface of a metal plate, in which through-holes are formed, is oxidized, and the surface processing for improving the bonding in the formation of minute irregularity and films and electrical insulating property are performed. All insulting parts other than the protruding part of the surface and the opposite surface for directly fixing a semiconductor chip of the metal part, except the protruding part and a cleramcp hole, are formed by using thermosetting resin composition. A larger hole is opened beforehand at the part of pre prepreg, corresponding to the metal part having the protrusion or protrusion at the opposite surface for directly fixing the semiconductor chip. The fused semi-hardened resin is made to flow into the clearance hole of the metal plate, and the material other than the metal protruding material are made to form an integral body with the thermosetting resin composition.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体チップを複数個
小型プリント配線板に搭載した形の、新規な半導体マル
チチッププラスチックパッケージに関する。特に、マイ
クロプロセッサー、マイクロコントローラー、ASIC、グ
ラフィック等の比較的高ワットで、多端子高密度の半導
体プラスチックパッケージに関する。本半導体プラスチ
ックパッケージは、ソルダーボールを用いてマザーボー
ドプリント配線板に実装して電子機器として使用され
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel semiconductor multi-chip plastic package in which a plurality of semiconductor chips are mounted on a small printed wiring board. In particular, it relates to relatively high wattage, multi-terminal, high-density semiconductor plastic packages such as microprocessors, microcontrollers, ASICs, and graphics. This semiconductor plastic package is mounted on a motherboard printed wiring board using solder balls and used as an electronic device.

【０００２】[0002]

【従来の技術】従来、半導体プラスチックパッケージと
して、プラスチックボールグリッドアレイ（P-BGA)やプ
ラスチックランドグリッドアレイ（P-LGA)等、プラスチ
ックプリント配線板の上面に半導体チップを固定し、こ
のチップを、プリント配線板上面に形成された導体回路
にワイヤボンディングで結合し、プリント配線板の下面
にはソルダーボールを用いて、マザーボードプリント配
線板と接続するための導体パッドを形成し、表裏回路導
体がメッキされたスルーホールで接続されて、半導体チ
ップが樹脂封止されている構造の半導体プラスチックパ
ッケージが公知である。2. Description of the Related Art Conventionally, a semiconductor chip is fixed on the upper surface of a plastic printed wiring board such as a plastic ball grid array (P-BGA) or a plastic land grid array (P-LGA) as a semiconductor plastic package. It is connected to the conductor circuit formed on the upper surface of the printed wiring board by wire bonding, and the lower surface of the printed wiring board is formed with conductor pads for connection with the motherboard printed wiring board using solder balls, and the front and back circuit conductors are plated 2. Description of the Related Art A semiconductor plastic package having a structure in which a semiconductor chip is sealed with a resin by connecting through a formed through hole is known.

【０００３】本公知構造において、半導体から発生する
熱をマザーボードプリント配線板に拡散させるため、半
導体チップを固定するための上面の金属箔から下面に接
続するメッキされた熱拡散スルーホールが形成されてい
る。該スルーホールを孔を通して、水分が半導体固定に
使われている銀粉入り樹脂接着剤に吸湿され、マザーボ
ードへの実装時の加熱により、または、半導体部品をマ
ザーボードから取り外す際の加熱により、層間フクレを
生じる危険性があり、これはポップコーン現象と呼ばれ
ている。このポップコーン現象が生じた場合、パッケー
ジが使用不能となることが多く、この現象を大幅に改善
する必要がある。また、半導体の高機能化、高密度化
は、ますます発熱量の増大を意味し、熱放散用のための
半導体チップ直下のスルーホールのみでは熱の放散は不
十分となってきている。In the known structure, a plated heat diffusion through hole is formed to connect a lower surface to a lower surface of a metal foil for fixing a semiconductor chip in order to diffuse heat generated from a semiconductor to a motherboard printed wiring board. I have. Through the holes, moisture is absorbed by the resin adhesive containing silver powder used for fixing the semiconductor, and the interlayer blister is removed by heating at the time of mounting on the motherboard or by heating when removing the semiconductor component from the motherboard. There is a risk of this occurring, called the popcorn phenomenon. When this popcorn phenomenon occurs, the package often becomes unusable, and it is necessary to greatly improve this phenomenon. In addition, higher functionality and higher density of semiconductors mean more and more heat generation, and heat dissipation is insufficient with only through holes directly below the semiconductor chip for heat dissipation.

【０００４】[0004]

【発明が解決しようとする課題】本発明は、以上の問題
点を改善したプラスチックパッケージを提供するもので
ある。SUMMARY OF THE INVENTION The present invention is to provide a plastic package which solves the above problems.

【０００５】[0005]

【課題を解決するための手段】すなわち、本発明は、プ
リント配線板の片面に、少なくとも２個以上の半導体チ
ップが固定され、半導体回路導体がその周囲のプリント
配線板表面に形成された回路導体とワイヤボンディング
で接続されており、少なくとも、該表面のプリント配線
板上の信号伝播回路導体が、プリント配線板の反対面に
形成された回路導体もしくは該ハンダボールでの接続用
導体パッドとスルーホール導体で結線されており、半導
体チップが樹脂封止されている構造の半導体プラスチッ
クパッケージであって、該プリント配線板とほぼ同じ大
きさの金属板がプリント配線板の厚さ方向のほぼ中央に
配置され、表裏回路導体と耐熱性樹脂組成物で絶縁され
ており、金属板に少なくとも１個以上のスルーホール径
より大きい径のクリアランスホールがあけられ、孔壁と
金属板とは樹脂組成物で絶縁されており、半導体チップ
とほぼ同じ大きさの内層の金属の一部が突起で表面に少
なくとも２箇所以上露出されており、該露出金属板の表
面に半導体チップが固定され、且つ、半導体チップの固
定用の金属板突起面とは反対側の表面の一部分に熱放散
用の金属板突起面が露出してなることを特徴とするマル
チチッププラスチックパッケージである。That is, according to the present invention, there is provided a circuit conductor comprising at least two semiconductor chips fixed to one surface of a printed wiring board, and a semiconductor circuit conductor formed on the surface of the surrounding printed wiring board. At least the signal propagation circuit conductor on the printed wiring board on the surface is connected to the circuit conductor formed on the opposite surface of the printed wiring board or the conductor pad for connection with the solder ball. A semiconductor plastic package having a structure in which a semiconductor chip is sealed with a resin and connected by a conductor, and a metal plate having substantially the same size as the printed wiring board is disposed substantially at the center in the thickness direction of the printed wiring board. The metal plate is insulated from the front and back circuit conductors by the heat-resistant resin composition, and the metal plate has a diameter larger than at least one through hole. An aperture hole is drilled, the hole wall and the metal plate are insulated with a resin composition, and at least two or more portions of the metal of the inner layer having substantially the same size as the semiconductor chip are exposed on the surface by protrusions, A semiconductor chip is fixed to the surface of the exposed metal plate, and a metal plate projection surface for heat dissipation is exposed on a part of the surface opposite to the fixing metal plate projection surface of the semiconductor chip. Is a multi-chip plastic package.

【０００６】発生した熱は熱放散用の金属板突起を通し
て逃げる。また、半導体チップの下面からの吸湿がな
く、吸湿後の耐熱性、すなわちポップコーン現象が大幅
に改善できるとともに、熱放散性を大幅に改善できた。
加えて大量生産性にも適しており、経済性の改善され
た、新規な構造のマルチチッププラスチックパッケージ
を得ることができた。[0006] The generated heat escapes through the metal plate projections for heat dissipation. In addition, there was no moisture absorption from the lower surface of the semiconductor chip, and the heat resistance after moisture absorption, that is, the popcorn phenomenon was significantly improved, and the heat dissipation was also significantly improved.
In addition, a multi-chip plastic package having a novel structure that is suitable for mass production and has improved economic efficiency was obtained.

【０００７】[0007]

【発明の実施の形態】本発明のプラスチックパッケージ
は、プリント配線板の厚み方向のほぼ中央に熱放散性の
良好な金属板を配置し、表裏の回路導体導通用のメッキ
されたスルーホールは、金属板にあけられた該クリアラ
ンスホール径より小さめの径の孔とし、埋め込まれた樹
脂のほぼ中央に形成することにより、金属板との絶縁性
を保持する。BEST MODE FOR CARRYING OUT THE INVENTION In the plastic package of the present invention, a metal plate having good heat dissipation is arranged at substantially the center in the thickness direction of a printed wiring board. A hole having a diameter smaller than the diameter of the clearance hole formed in the metal plate is formed substantially at the center of the embedded resin, thereby maintaining the insulation with the metal plate.

【０００８】公知のスルーホールを有する金属芯プリン
ト配線板の上面に半導体チップを固定する方法において
は、従来の P-BGAパッケージと同様に半導体チップから
の熱は直下の熱放散用スルーホールに落として熱放散せ
ざるを得ず、ポップコーン現象は改善できない。本発明
は、まず金属芯とする金属板をあらかじめ公知のエッチ
ング法、冷間機械加工、圧延異型条加工法等の方法で、
少なくとも２個以上の半導体チップ固定用に、半導体チ
ップとほぼ同等の大きさの突起を形成しておく。次い
で、表裏の導通スルーホールを形成可能なように、スル
ーホールを形成しようとする位置にスルーホール径より
大きめのクリアランスホールを、公知のエッチング法、
打ち抜き法、ドリル、レーザー等で金属芯に孔を形成し
ておく。半導体から発生する熱は、直接搭載する金属部
分から金属板全体に熱伝導されるために、反対面に形成
された、表面に露出した金属板突起部から、熱をマザー
ボードプリント配線板に拡散する構造とする。In a known method of fixing a semiconductor chip on the upper surface of a metal-core printed wiring board having a through hole, heat from the semiconductor chip is dropped to a heat-dissipating through hole immediately below, similarly to a conventional P-BGA package. Heat must be dissipated and the popcorn phenomenon cannot be improved. The present invention is a method in which a metal plate serving as a metal core is firstly known in advance by a known etching method, cold machining, rolling irregular strip processing, and the like.
For fixing at least two or more semiconductor chips, a projection having a size substantially equal to that of the semiconductor chip is formed. Then, a clearance hole larger than the diameter of the through hole is formed at a position where the through hole is to be formed by a known etching method so that a conductive through hole on both sides can be formed.
A hole is formed in the metal core by a punching method, a drill, a laser, or the like. The heat generated from the semiconductor is conducted from the directly mounted metal portion to the entire metal plate, so that the heat is diffused to the motherboard printed wiring board from the metal plate protrusion formed on the opposite surface and exposed on the surface. Structure.

【０００９】該突起とスルーホールが形成された金属板
の表面を公知の方法で酸化処理、微細凹凸形成、皮膜形
成等の接着性や電気絶縁性向上のための表面処理を必要
に応じて施す。該表面処理され、突起部とクリアランス
ホールが形成された金属板の、半導体チップを直接固定
する面及び反対面の突起部以外は、すべて熱硬化性樹脂
組成物で絶縁部を形成する。熱硬化性樹脂組成物による
絶縁部の形成は、半硬化状態の熱硬化性樹脂組成物を含
浸、乾燥したプリプレグ等を用い、半導体チップを直接
固定する突起或いは反対面の突起のある金属部分に相当
するプリプレグの部分を、あらかじめ突起部分の面積よ
りやや大きめの孔を打ち抜き等によってあけておき、こ
れを両面に配置し、加熱、加圧下に積層成形する。プリ
プレグの厚みは金属突起の高さよりやや高めになるよう
に作成する。加熱、加圧工程中に、熱により１度熔融し
た半硬化状態の熱硬化性樹脂を金属板のクリアランスホ
ールに流し込んでクリアランスホールの中を埋め込むと
同時に、金属突起物の表面以外は熱硬化性樹脂組成物で
一体化する。The surface of the metal plate on which the projections and the through holes are formed is subjected to a surface treatment for improving adhesiveness and electric insulation such as oxidation treatment, formation of fine irregularities, and formation of a film as necessary. . The surface of the metal plate on which the protrusions and the clearance holes are formed, except for the surface on which the semiconductor chip is directly fixed and the protrusions on the opposite surface, are all formed of an insulating portion with a thermosetting resin composition. The formation of the insulating portion by the thermosetting resin composition is performed by impregnating the thermosetting resin composition in a semi-cured state, using a dried prepreg, or the like, and directly fixing the semiconductor chip to the metal portion having the projection on the opposite surface or the projection on the opposite surface. A corresponding prepreg portion is previously punched with a hole slightly larger than the area of the projection portion by punching or the like, and these are arranged on both surfaces, and laminated and formed under heat and pressure. The thickness of the prepreg is made slightly higher than the height of the metal projection. During the heating and pressurizing steps, a semi-cured thermosetting resin that has been melted once by heat is poured into the clearance holes of the metal plate to fill the clearance holes, and at the same time, the thermosetting resin except for the surface of the metal protrusions Integrate with a resin composition.

【００１０】また、無溶剤或いは溶剤タイプの熱硬化性
樹脂組成物を用い、スクリーン印刷等で該金属板突起場
所以外に塗布し、更には裏面も同様に塗布してから加熱
して半硬化状態とした後、このまま加熱して硬化する
か、加熱、加圧下に積層成形して一体化する。積層成形
する場合、上記と同様にクリアランスホール内に樹脂を
流し込むと同時に熱硬化させる。塗布、半硬化する場
合、低圧にてクリアランスホールの中に樹脂を流し込
み、溶剤或いは空気を加熱しながら抜き、半硬化する。
溶剤が入っている場合、クリアランスホール内の未充填
が起こり易いため、あらかじめ無溶剤液状の熱硬化性樹
脂組成物クリアランスホールに流し込み、硬化しておく
方法が一般的であるが、いずれの方法においても、金属
板のクリアランスホール内を熱硬化性樹脂組成物で充填
されるように加工する。A non-solvent or solvent-type thermosetting resin composition is applied by screen printing or the like to portions other than the metal plate projections. Then, it is cured by heating as it is, or is laminated and formed under heat and pressure to be integrated. In the case of laminating and molding, the resin is poured into the clearance holes and thermosetting at the same time as described above. In the case of coating and semi-curing, a resin is poured into the clearance hole at a low pressure, and the solvent or air is removed while heating, and semi-cured.
When the solvent is contained, since unfilling in the clearance hole is likely to occur, a method of pouring the solvent-free liquid thermosetting resin composition into the clearance hole in advance and curing is generally used. Also, processing is performed such that the clearance holes of the metal plate are filled with the thermosetting resin composition.

【００１１】金属板の側面については、熱硬化性樹脂組
成物で埋め込まれている形、露出している形、いずれの
形でも良い。[0011] The side surface of the metal plate may be any of a shape embedded with a thermosetting resin composition and an exposed shape.

【００１２】また、サブトラクティブ法によるスルーホ
ールプリント配線板の形成のためには、積層成形時に、
表裏の最外層に、プリント配線板よりやや大きめの金属
箔、或いは片面銅張積層板を配置して、加熱、加圧下に
積層成形することににより、外層回路形成用の金属箔で
表裏が覆われた金属箔張多層板が形成される。Further, in order to form a through-hole printed wiring board by a subtractive method, it is necessary to
A metal foil slightly larger than the printed wiring board or a single-sided copper-clad laminate is placed on the outermost layer on the front and back sides, and the front and back sides are covered with metal foil for forming an outer layer circuit by laminating and molding under heat and pressure. A laminated metal foil clad multilayer board is formed.

【００１３】表裏層に金属箔を使用しないで積層成形す
る場合、公知のアディティブ法にて回路を形成し、プリ
ント配線板を作る。When laminating and molding without using a metal foil for the front and back layers, a circuit is formed by a known additive method to produce a printed wiring board.

【００１４】上記サブトラクティブ法、アディティブ法
で作成した板の、半導体を固定する部分以外の箇所に表
裏の回路を導通するスルーホール用孔をドリル、レーザ
ー或いはプラズマ等、公知の方法にて小径の孔をあけ
る。[0014] In a plate made by the subtractive method or the additive method, a hole for a through hole for conducting a circuit between the front and back is formed in a portion other than a portion for fixing a semiconductor by a known method such as drilling, laser or plasma. Drill holes.

【００１５】表裏信号回路用のスルーホール用孔は、樹
脂の埋め込まれた金属板クリアランスホールのほぼ中央
に、金属板と接触しないように形成する。次いで、無電
解メッキや電解メッキによりスルーホール内部の金属層
を形成して、メッキされたスルーホールを形成するとと
もに、フルアディティブ法では、同時に表裏にワイヤボ
ンディング用端子、信号回路、ソルダーボール用パッ
ド、導体回路等を形成する。The through hole for the front and back signal circuits is formed substantially at the center of the metal plate clearance hole in which the resin is embedded so as not to contact the metal plate. Next, a metal layer inside the through hole is formed by electroless plating or electrolytic plating, and a plated through hole is formed. In the full additive method, wire bonding terminals, signal circuits, solder ball pads are simultaneously formed on the front and back. To form a conductive circuit and the like.

【００１６】セミアディティブ法では、スルーホールを
メッキすると同時に、表裏も全面メッキされ、その後、
公知の方法にて上下に回路を形成する。また、表裏金属
箔を使用して積層成形されたものは、表裏の回路形成工
程で、半導体チップ固定部分の金属突起部分及び反対面
突起部の表面にある金属箔も除去される。次いで、ワイ
ヤボンディング用の貴金属メッキを、少なくともワイヤ
ボンディングパッド表面に形成してプリント配線板を完
成させる。この場合、貴金属メッキの必要のない箇所
は、事前にメッキレジストで被覆しておく。また、メッ
キ後に、必要により公知の熱硬化性樹脂組成物、或いは
光選択熱硬化性樹脂組成物で、少なくともボンディング
パッド、及び反対面のハンダボール接続用パッド以外の
表面に皮膜を形成する。片面銅張積層板を使用した場
合、回路形成後、或いは貴金属メッキ後にルータ等で半
導体チップ搭載箇所金属板の上の基材を切除する。In the semi-additive method, the front and back surfaces are plated at the same time as the through holes are plated.
Circuits are formed above and below by a known method. In the case of lamination molding using the front and back metal foils, the metal protrusions on the semiconductor chip fixing portion and the metal foil on the surface of the opposite protrusion are also removed in the circuit forming process on the front and back surfaces. Next, a noble metal plating for wire bonding is formed on at least the surface of the wire bonding pad to complete the printed wiring board. In this case, a portion that does not require noble metal plating is covered with a plating resist in advance. After plating, if necessary, a coating is formed on at least the surface other than the bonding pad and the solder ball connection pad on the opposite surface with a known thermosetting resin composition or a photo-selective thermosetting resin composition. When a single-sided copper-clad laminate is used, after forming a circuit or after plating a noble metal, the base material on the metal plate on which the semiconductor chip is to be mounted is cut off using a router or the like.

【００１７】該プリント配線板の半導体を接着する金属
突起部分の表面に接着剤や金属粉混合接着剤を用いて、
半導体チップを固定し、さらに半導体チップとプリント
配線板回路のボンディングパッドとをワイヤボンディン
グ法で接続し、少なくとも、半導体チップ、ボンディン
グワイヤ、及びボンディングパッドを公知の封止樹脂で
封止する。An adhesive or a metal powder mixed adhesive is used on the surface of the metal projection portion of the printed wiring board for bonding the semiconductor,
The semiconductor chip is fixed, and the semiconductor chip and the bonding pads of the printed wiring board circuit are connected by a wire bonding method, and at least the semiconductor chip, the bonding wires, and the bonding pads are sealed with a known sealing resin.

【００１８】半導体チップと反対面のソルダーボール接
続用導体パッドに、ソルダーボールを接続してP-BGA を
作り、マザーボードプリント配線板上の回路にソルダー
ボールを重ね、熱によってボールを熔融接続するか、ま
たはパッケージにソルダーボールをつけずにP-LGA を作
り、マザーボードプリント配線板に実装する時に、マザ
ーボードプリント配線板面に形成されたソルダーボール
接続用導体パッドとP-LGA 用のソルダーボール用導体パ
ッドとを、ソルダーボールを加熱熔融することにより接
続する。A solder ball is connected to the solder ball connecting conductor pad on the opposite side of the semiconductor chip to form a P-BGA, and the solder ball is superimposed on a circuit on a motherboard printed wiring board, and the ball is melt-connected by heat. When the P-LGA is made without attaching solder balls to the package, and mounted on the motherboard printed wiring board, the solder ball connection conductor pads formed on the motherboard printed wiring board surface and the solder ball conductors for the P-LGA The pads are connected by heating and melting the solder balls.

【００１９】本発明に用いる金属板は、特に限定しない
が、高弾性率、高熱伝導性で、厚さ30〜300 μｍのもの
が好適である。具体的には、純銅、無酸素銅、その他、
銅が95重量％以上のFe、Sn、Ｐ、Cr、Zr、Zn等との合
金、或いは合金の表面を銅メッキした金属板等が好適に
使用される。Although the metal plate used in the present invention is not particularly limited, a metal plate having a high elastic modulus, a high thermal conductivity and a thickness of 30 to 300 μm is preferable. Specifically, pure copper, oxygen-free copper, and others,
An alloy of 95% by weight or more of copper with Fe, Sn, P, Cr, Zr, Zn, or the like, or a metal plate having an alloy surface plated with copper is preferably used.

【００２０】本発明の金属突起部の高さは、30〜200 μ
ｍが好適である。また、突起部をくり抜いたプリプレ
グ、或いはスクリーン印刷で形成する熱硬化性樹脂の高
さは、この突起と同じ高さか、やや高いことが好まし
い。突起部の面積は、半導体チップの面積と同等以上で
あり、僅かに大きめが好ましい。一般的には５〜20mm角
である。金属突起部は、エッチング、冷間機械加工、或
いは圧延異型条等の一般に公知の方法で作成できる。ま
た、平滑な金属板の上に、所定の大きさの同質、或いは
異質の金属板を、熱伝導の良好な銅ペースト等、一般に
公知の接着方法にて接着させることも可能である。The height of the metal projection of the present invention is 30 to 200 μm.
m is preferred. Further, it is preferable that the height of the prepreg formed by hollowing out the projection or the thermosetting resin formed by screen printing is the same as or slightly higher than the height of the projection. The area of the projection is equal to or greater than the area of the semiconductor chip, and is preferably slightly larger. Generally, it is 5 to 20 mm square. The metal projection can be formed by a generally known method such as etching, cold machining, or rolling irregular strip. It is also possible to bond a homogeneous or heterogeneous metal plate of a predetermined size on a smooth metal plate by a generally known bonding method such as a copper paste having good heat conductivity.

【００２１】本発明で使用される熱硬化性樹脂組成物の
樹脂としては、一般に公知の熱硬化性樹脂が使用され
る。具体的には、エポキシ樹脂、多官能性シアン酸エス
テル樹脂、多官能性マレイミド−シアン酸エステル樹
脂、多官能性マレイミド樹脂、不飽和ポリエステル樹
脂、不飽和基含有ポリフェニレンエーテル樹脂等が挙げ
られ、１種或いは２種類以上が組み合わせて使用され
る。耐熱性、耐湿性、耐マイグレーション性、吸湿後の
電気的特性等の点から多官能性シアン酸エステル樹脂組
成物が好適である。As the resin of the thermosetting resin composition used in the present invention, generally known thermosetting resins are used. Specific examples include an epoxy resin, a polyfunctional cyanate resin, a polyfunctional maleimide-cyanate resin, a polyfunctional maleimide resin, an unsaturated polyester resin, and an unsaturated group-containing polyphenylene ether resin. Species or two or more kinds are used in combination. Polyfunctional cyanate ester resin compositions are preferred from the viewpoints of heat resistance, moisture resistance, migration resistance, electrical properties after moisture absorption, and the like.

【００２２】本発明の好適な熱硬化性樹脂分である多官
能性シアン酸エステル化合物とは、分子内に２個以上の
シアナト基を有する化合物である。具体的に例示する
と、1,3-又は1,4-ジシアナトベンゼン、1,3,5-トリシア
ナトベンゼン、1,3-、1,4-、1,6-、1,8-、2,6-又は2,7-
ジシアナトナフタレン、1,3,6-トリシアナトナフタレ
ン、4,4-ジシアナトビフェニル、ビス（4-ジシアナトフ
ェニル）メタン、2,2-ビス（4-シアナトフェニル）プロ
パン、2,2-ビス（3,5-ジブロモ-4- シアナトフェニル）
プロパン、ビス（4-シアナトフェニル）エーテル、ビス
（4-シアナトフェニル）チオエーテル、ビス（4-シアナ
トフェニル）スルホン、トリス（4-シアナトフェニル）
ホスファイト、トリス（4-シアナトフェニル）ホスフェ
ート、およびノボラックとハロゲン化シアンとの反応に
より得られるシアネート類などである。The polyfunctional cyanate compound which is a preferred thermosetting resin component of the present invention is a compound having two or more cyanato groups in a molecule. Specific examples include 1,3- or 1,4-dicyanatobenzene, 1,3,5-tricyanatobenzene, 1,3-, 1,4-, 1,6-, 1,8-, 2 , 6- or 2,7-
Dicyanatonaphthalene, 1,3,6-tricyanatonaphthalene, 4,4-dicyanatobiphenyl, bis (4-dicyanatophenyl) methane, 2,2-bis (4-cyanatophenyl) propane, 2,2- Bis (3,5-dibromo-4-cyanatophenyl)
Propane, bis (4-cyanatophenyl) ether, bis (4-cyanatophenyl) thioether, bis (4-cyanatophenyl) sulfone, tris (4-cyanatophenyl)
Phosphite, tris (4-cyanatophenyl) phosphate, and cyanates obtained by reacting novolak with cyanogen halide.

【００２３】これらのほかに特公昭41-1928 、同43-184
68、同44-4791 、同45-11712、同46-41112、同47-26853
及び特開昭51-63149等に記載の多官能性シアン酸エステ
ル化合物類も用いられ得る。また、これら多官能性シア
ン酸エステル化合物のシアナト基の三量化によって形成
されるトリアジン環を有する分子量400 〜6,000 のプレ
ポリマーが使用される。このプレポリマーは、上記の多
官能性シアン酸エステルモノマーを、例えば鉱酸、ルイ
ス酸等の酸類；ナトリウムアルコラート等、第三級アミ
ン類等の塩基；炭酸ナトリウム等の塩類等を触媒として
重合させることにより得られる。このプレポリマー中に
は一部未反応のモノマーも含まれており、モノマーとプ
レポリマーとの混合物の形態をしており、このような原
料は本発明の用途に好適に使用される。一般には可溶な
有機溶剤に溶解させて使用する。In addition to these, Japanese Patent Publication Nos. 41-1928 and 43-184
68, 44-4791, 45-11712, 46-41112, 47-26853
And polyfunctional cyanate compounds described in JP-A-51-63149 and the like can also be used. In addition, a prepolymer having a molecular weight of 400 to 6,000 and having a triazine ring formed by trimerizing a cyanato group of these polyfunctional cyanate compounds is used. This prepolymer is obtained by polymerizing the above-mentioned polyfunctional cyanate ester monomer using, for example, an acid such as a mineral acid or a Lewis acid; a base such as a sodium alcoholate or a tertiary amine; a salt such as sodium carbonate as a catalyst. It can be obtained by: The prepolymer also contains some unreacted monomers and is in the form of a mixture of the monomer and the prepolymer, and such a raw material is suitably used for the purpose of the present invention. Generally, it is used after being dissolved in a soluble organic solvent.

【００２４】エポキシ樹脂としては、一般に公知のもの
が使用できる。具体的には、液状或いは固形のビスフェ
ノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ
樹脂、フェノールノボラック型エポキシ樹脂、クレゾー
ルノボラック型エポキシ樹脂、脂環式エポキシ樹脂；ブ
タジエン、ペンタジエン、ビニルシクロヘキセン、ジシ
クロペンチルエーテル等の二重結合をエポキシ化したポ
リエポキシ化合物類；ポリオール、水酸基含有シリコン
樹脂類とエポハロヒドリンとの反応によって得られるポ
リグリシジル化合物類等が挙げられる。これらは１種或
いは２種類以上が組み合わせて使用され得る。As the epoxy resin, generally known epoxy resins can be used. Specifically, liquid or solid bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, alicyclic epoxy resin; butadiene, pentadiene, vinylcyclohexene, dicyclopentyl ether, etc. And polyglycidyl compounds obtained by reacting a polyol, a hydroxyl group-containing silicone resin with an ephalohydrin, and the like. These may be used alone or in combination of two or more.

【００２５】ポリイミド樹脂としては、一般に公知のも
のが使用され得る。具体的には、多官能性マレイミド類
とポリアミン類との反応物、特公昭57-005406 に記載の
末端三重結合のポリイミド類が挙げられる。As the polyimide resin, generally known ones can be used. Specific examples include a reaction product of a polyfunctional maleimide and a polyamine, and a polyimide having a terminal triple bond described in JP-B-57-005406.

【００２６】これらの熱硬化性樹脂は、単独でも使用さ
れるが、特性のバランスを考え、適宜組み合わせて使用
するのが良い。These thermosetting resins may be used alone, but it is preferable to use them in an appropriate combination in consideration of the balance of properties.

【００２７】本発明の熱硬化性樹脂組成物には、組成物
本来の特性が損なわれない範囲で、所望に応じて種々の
添加物を配合することができる。これらの添加物として
は、不飽和ポリエステル等の重合性二重結合含有モノマ
ー類及びそのプレポリマー類；ポリブタジエン、エポキ
シ化ブタジエン、マレイン化ブタジエン、ブタジエン−
アクリロニトリル共重合体、ポリクロロプレン、ブタジ
エン−スチレン共重合体、ポリイソプレン、ブチルゴ
ム、フッ素ゴム、天然ゴム等の低分子量液状〜高分子量
のelastic なゴム類；ポリエチレン、ポリプロピレン、
ポリブテン、ポリ-4- メチルペンテン、ポリスチレン、
AS樹脂、ABS 樹脂、MBS 樹脂、スチレン−イソプレンゴ
ム、ポリエチレン−プロピレン共重合体、4-フッ化エチ
レン-6- フッ化エチレン共重合体類；ポリカーボネー
ト、ポリフェニレンエーテル、ポリスルホン、ポリエス
テル、ポリフェニレンサルファイド等の高分子量プレポ
リマー若しくはオリゴマー；ポリウレタン等が例示さ
れ、適宜使用される。また、その他、公知の無機或いは
有機の充填剤、染料、顔料、増粘剤、滑剤、消泡剤、分
散剤、レベリング剤、光増感剤、難燃剤、光沢剤、重合
禁止剤、チキソ性付与剤等の各種添加剤が、所望に応じ
て適宜組み合わせて用いられる。必要により、反応基を
有する化合物は硬化剤、触媒が適宜配合される。Various additives can be added to the thermosetting resin composition of the present invention, if desired, as long as the inherent properties of the composition are not impaired. These additives include polymerizable double bond-containing monomers such as unsaturated polyesters and prepolymers thereof; polybutadiene, epoxidized butadiene, maleated butadiene, butadiene-
Low molecular weight liquid to high molecular weight elastic rubbers such as acrylonitrile copolymer, polychloroprene, butadiene-styrene copolymer, polyisoprene, butyl rubber, fluoro rubber, natural rubber; polyethylene, polypropylene,
Polybutene, poly-4-methylpentene, polystyrene,
AS resin, ABS resin, MBS resin, styrene-isoprene rubber, polyethylene-propylene copolymer, 4-fluoroethylene-6-fluoroethylene copolymers; polycarbonate, polyphenylene ether, polysulfone, polyester, polyphenylene sulfide, etc. High molecular weight prepolymers or oligomers; polyurethanes and the like are exemplified, and are appropriately used. Other known inorganic or organic fillers, dyes, pigments, thickeners, lubricants, defoamers, dispersants, leveling agents, photosensitizers, flame retardants, brighteners, polymerization inhibitors, thixotropic Various additives such as imparting agents are used in combination as needed. If necessary, the compound having a reactive group is appropriately blended with a curing agent and a catalyst.

【００２８】本発明の熱硬化性樹脂組成物は、それ自体
は加熱により硬化するが硬化速度が遅く、作業性、経済
性等に劣るため使用した熱硬化性樹脂に対して公知の熱
硬化触媒を用い得る。使用量は、熱硬化性樹脂 100重量
部に対して 0.005〜10重量部、好ましくは0.01〜５重量
部である。The thermosetting resin composition of the present invention can be cured by heating itself, but has a low curing rate and is inferior in workability and economic efficiency. Can be used. The amount used is 0.005 to 10 parts by weight, preferably 0.01 to 5 parts by weight, per 100 parts by weight of the thermosetting resin.

【００２９】プリプレグの補強基材としては、一般に公
知の無機或いは有機の織布、不織布が使用される。具体
的には、Ｅガラス、Ｓガラス、Ｄガラス等の公知のガラ
ス繊維布、全芳香族ポリアミド繊維布、液晶ポリエステ
ル繊維布等が挙げられる。これらは、混抄でも良い。ま
た、ポリイミドフィルム等のフィルムの表裏に熱硬化性
樹脂組成物を塗布、加熱して半硬化状態にしたものも使
用できる。As a reinforcing base material of the prepreg, generally known inorganic or organic woven or nonwoven fabric is used. Specific examples include known glass fiber cloths such as E glass, S glass, and D glass, wholly aromatic polyamide fiber cloths, and liquid crystal polyester fiber cloths. These may be mixed. Alternatively, a thermosetting resin composition applied to the front and back of a film such as a polyimide film and heated to a semi-cured state can be used.

【００３０】最外層の金属箔は、一般に公知のものが使
用できる。好適には厚さ３〜100 μｍの銅箔、アルミニ
ウム箔、ニッケル箔等が使用される。As the outermost metal foil, generally known ones can be used. Preferably, a copper foil, aluminum foil, nickel foil or the like having a thickness of 3 to 100 μm is used.

【００３１】金属板に形成するクリアランスホールの径
は、表裏導通用スルーホール径よりやや大きめに形成す
る。具体的には、該スルーホール壁と金属板クリアラン
スホール壁とは50μｍ以上の距離が、熱硬化性樹脂組成
物で絶縁されていることが好ましい。表裏導通用スルー
ホール径については、特に限定はないが、50〜300 μｍ
が好適である。The diameter of the clearance hole formed in the metal plate is slightly larger than the diameter of the through hole for front and back conduction. Specifically, it is preferable that a distance of 50 μm or more between the through hole wall and the metal plate clearance hole wall is insulated by the thermosetting resin composition. The diameter of the through hole for front / back conduction is not particularly limited, but is 50 to 300 μm.
Is preferred.

【００３２】本発明の多層プリント配線板用プリプレグ
を作成する場合、基材に熱硬化性樹脂組成物を含浸、乾
燥し、半硬化状態の積層材料とする。また基材を使用し
ない半硬化状態とした樹脂シートも使用できる。或いは
塗料も使用できる。この場合、半硬化状態の程度によ
り、ハイフロー化、ノーフロー化する。ノーフローとし
た場合、加熱、加圧して積層成形した時、樹脂の流れ出
しが 100μｍ以下、好ましくは50μｍ以下とする。ま
た、この際、金属板、金属箔とは接着し、ボイドの発生
しないことが肝要である。プリプレグを作成する温度は
一般的には 100〜180 ℃である。時間は５〜60分であ
り、目的とするフローの程度により、適宜選択する。When preparing a prepreg for a multilayer printed wiring board of the present invention, a substrate is impregnated with a thermosetting resin composition and dried to obtain a semi-cured laminated material. Also, a resin sheet in a semi-cured state without using a base material can be used. Alternatively, paints can be used. In this case, depending on the degree of the semi-cured state, high flow or no flow is achieved. In the case of no flow, the flow of the resin is set to 100 μm or less, preferably 50 μm or less when laminating by heating and pressing. At this time, it is important that the metal plate and the metal foil adhere to each other and no void is generated. The temperature at which the prepreg is made is generally between 100 and 180 ° C. The time is 5 to 60 minutes, and is appropriately selected depending on the desired flow rate.

【００３３】本発明の金属芯の入った半導体プラスチッ
クパッケージを作成する方法は特に限定しないが、例え
ば以下（図１）の方法による。 (1) まず、内層となる金属板全面を液状エッチングレジ
ストで被覆し、加熱して溶剤を除去した後、半導体チッ
プを固定する突起部及び反対面の熱放散用突起部のレジ
ストが残るように作成したネガフィルムを被せ、紫外線
照射後、１％炭酸ナトリウム水溶液で未露光部分を溶解
除去する。 (2) エッチングにて金属板を所定厚み溶解してから、エ
ッチングレジストを溶解除去する。 (3) 再び液状エッチングレジストで上下を被覆し、両面
の金属突起部をくり抜き、クリアランスホール部以外の
部分の光が遮断できるように作成したネガフィルムをそ
の上にあて、紫外線で露光する。The method of producing the semiconductor plastic package containing the metal core of the present invention is not particularly limited. For example, the following method (FIG. 1) is used. (1) First, the entire surface of the metal plate serving as the inner layer is coated with a liquid etching resist, and after heating to remove the solvent, the protrusions for fixing the semiconductor chip and the resist for the heat dissipation protrusions on the opposite surface are left. After covering the prepared negative film and irradiating with ultraviolet rays, unexposed portions are dissolved and removed with a 1% aqueous solution of sodium carbonate. (2) After the metal plate is dissolved to a predetermined thickness by etching, the etching resist is dissolved and removed. (3) Cover the top and bottom again with the liquid etching resist, cut out the metal projections on both sides, apply a negative film made so as to block the light in the parts other than the clearance holes, and expose it to ultraviolet light.

【００３４】(4) クリアランスホール部のエッチングレ
ジストを溶解除去してから、エッチング法にて両側から
エッチングし、金属板にクリアランスホールを作成す
る。 (5) エッチングレジストを除去後、金属板全面を化学表
面処理し、金属突起部の部分よりやや大きめに孔をあけ
たプリプレグを両側に配置し、上下に金属箔を置く。 (6) 加熱、加圧、真空下に積層成形した後、所定の位置
にドリル、或いはレーザー等でスルーホールを内層金属
箔に接触しないようにあけ、デスミア処理を施した後、
金属メッキを行う。 (7) 公知の方法にて上下に回路を作成すると同時に、金
属板突起部の金属箔を除去し、貴金属メッキを施し、内
層金属板の半導体チップ搭載部である突起部の表面に半
導体チップを接着する。その後、樹脂封止を行い、必要
によりハンダボールを接着する。(4) After the etching resist in the clearance hole portion is dissolved and removed, etching is performed from both sides by an etching method to form a clearance hole in the metal plate. (5) After removing the etching resist, the entire surface of the metal plate is subjected to chemical surface treatment, prepregs having holes slightly larger than the metal projections are arranged on both sides, and metal foil is placed on the upper and lower sides. (6) After laminating under heat, pressure and vacuum, drill through a predetermined position with a laser or laser etc. so that the through hole does not come into contact with the inner metal foil, and after desmearing,
Perform metal plating. (7) At the same time as forming circuits above and below by a known method, remove the metal foil of the metal plate protrusion, apply noble metal plating, and place the semiconductor chip on the surface of the protrusion that is the semiconductor chip mounting part of the inner layer metal plate. Glue. After that, resin sealing is performed, and a solder ball is bonded if necessary.

【００３５】[0035]

【実施例】以下に実施例、比較例で本発明を具体的に説
明する。尚、特に断らない限り、『部』は重量部を表
す。 実施例１ 2,2-ビス（4-シアナトフェニル）プロパン 900部、ビス
（4-マレイミドフェニル）メタン 100部を 150℃に熔融
させ、撹拌しながら４時間反応させ、プレポリマーを得
た。これをメチルエチルケトンとジメチルホルムアミド
の混合溶剤に溶解した。これにビスフェノールＡ型エポ
キシ樹脂（商品名：エピコート1001、油化シェルエポキ
シ＜株＞製）400 部、クレゾールノボラック型エポキシ
樹脂（商品名:ESCN-220F、住友化学工業＜株＞製） 600
部を加え、均一に溶解混合した。更に触媒としてオクチ
ル酸亜鉛 0.4部を加え、溶解混合し、これに無機充填剤
（商品名：タルクP-3 、日本タルク＜株＞製) 500部を
加え、均一撹拌混合してワニスＡを得た。The present invention will be specifically described below with reference to examples and comparative examples. Unless otherwise specified, “parts” indicates parts by weight. Example 1 900 parts of 2,2-bis (4-cyanatophenyl) propane and 100 parts of bis (4-maleimidophenyl) methane were melted at 150 ° C. and reacted with stirring for 4 hours to obtain a prepolymer. This was dissolved in a mixed solvent of methyl ethyl ketone and dimethylformamide. 400 parts of bisphenol A type epoxy resin (trade name: Epicoat 1001, Yuka Shell Epoxy Co., Ltd.) and cresol novolak type epoxy resin (trade name: ESCN-220F, Sumitomo Chemical Co., Ltd.) 600
Was added and uniformly dissolved and mixed. Further, 0.4 part of zinc octylate was added as a catalyst, and the mixture was dissolved and mixed. To this, 500 parts of an inorganic filler (trade name: talc P-3, manufactured by Nippon Talc Co., Ltd.) was added, followed by uniform stirring and mixing to obtain Varnish A. Was.

【００３６】このワニスＡを厚さ 100μｍのガラス織布
に含浸し150 ℃で乾燥して、ゲル化時間(at170℃) ０
秒,170℃,20kgf/cm2,5分間での樹脂流れ60μｍとなるよ
うに作成した厚さ 105μｍの半硬化状態のプリプレグ
（プリプレグＢ）を得た。また、ゲル化時間 114秒、樹
脂流れ14mmのプリプレグＣを得た。This varnish A is impregnated in a glass woven cloth having a thickness of 100 μm, dried at 150 ° C., and subjected to gelation time (at 170 ° C.).
A semi-cured prepreg (prepreg B) having a thickness of 105 μm and a resin flow of 60 μm in 5 seconds at 170 ° C., 20 kgf / cm 2 for 5 minutes was obtained. Further, a prepreg C having a gelling time of 114 seconds and a resin flow of 14 mm was obtained.

【００３７】一方、内層金属板となる厚さ 250μｍの銅
板を用意し、大きさ50mm角のパッケージの中央に13mm
角、高さ 100μｍの突起を２個作成した。反対面には５
mm角、高さ 100μｍの突起をエッチング法にて形成し
た。その後、該金属板の全面に液状エッチングレジスト
を厚さ20μm 塗布し、乾燥して溶剤を飛ばした後、突起
部をくり抜いたネガフィルムを両面にそれぞれ重ね、ク
リアランスホール以外を紫外線照射してからクリアラン
スホール部のレジスト膜を１％炭酸ナトリウム水溶液で
除去した後、両側からエッチングによって 0.6mmφのク
リアランスホールをあけた。On the other hand, a copper plate having a thickness of 250 μm serving as an inner metal plate was prepared, and 13 mm was placed at the center of a 50 mm square package.
Two protrusions having a corner and a height of 100 μm were formed. 5 on the other side
A protrusion of mm square and a height of 100 μm was formed by an etching method. After that, a liquid etching resist of 20 μm in thickness is applied to the entire surface of the metal plate, dried, and the solvent is blown off. Then, a negative film in which the protrusions are cut out is superposed on both surfaces, and ultraviolet light is applied to portions other than the clearance holes, and then the clearance is applied. After removing the resist film in the hole portion with a 1% aqueous solution of sodium carbonate, a clearance hole of 0.6 mmφ was opened from both sides by etching.

【００３８】金属板全面に黒色酸化銅処理を施し、この
両面には、突起部分に相当する位置に、突起部より50μ
ｍ大きめの孔をルーターにてあけた上記プリプレグＢを
被せ、その両外側に厚さ18μm の電解銅箔を配置し、 2
00℃,20kgf/cm2,30mmHg 以下の真空下で２時間積層成形
し、一体化した。A black copper oxide treatment is applied to the entire surface of the metal plate.
Cover the prepreg B with a hole larger by m with a router, and place 18μm thick electrolytic copper foil on both outer sides.
The laminate was formed by lamination under a vacuum of 00 ° C., 20 kgf / cm 2 , 30 mmHg or less for 2 hours and integrated.

【００３９】クリアランスホール箇所は、クリアランス
ホール部の金属に接触しないように、中央に孔径0.25mm
のスルーホールをレーザーにてあけ、デスミア処理後、
銅メッキを無電解、電解メッキで行い、孔内に18μｍの
銅メッキ層を形成した。表裏に液状エッチングレジスト
を塗布、乾燥してからポジフィルムを重ねて露光、現像
し、表裏回路を形成するとともに、突起部上の銅箔も同
時にエッチング除去した。突起部、ボンディングパッド
及びボールパッド以外にメッキレジストを形成し、ニッ
ケル、金メッキを施してプリント配線板を完成した。上
面突起部に大きさ13mm角の半導体チップを銀ペーストで
接着固定した後、ワイヤボンディングを行い、次いでシ
リカ入りエポキシ封止用コンパウンドを用い、トランス
ファーモールドにて樹脂封止して半導体パッケージを作
成した（図１）。このパッケージの評価結果を表１に示
す。The clearance hole has a hole diameter of 0.25 mm at the center so as not to come into contact with the metal in the clearance hole.
Drill the through hole with laser and after desmearing,
Copper plating was performed by electroless and electrolytic plating, and a copper plating layer of 18 μm was formed in the holes. After applying and drying a liquid etching resist on the front and back, a positive film was overlaid and exposed and developed to form a front and back circuit, and the copper foil on the protruding portions was simultaneously etched away. A plating resist was formed on the portions other than the protruding portions, the bonding pads and the ball pads, and nickel and gold plating were applied to complete the printed wiring board. A semiconductor chip having a size of 13 mm square was bonded and fixed to the protrusion on the upper surface with a silver paste, then wire-bonded, and then resin-encapsulated by transfer molding using a silica-containing epoxy encapsulating compound to prepare a semiconductor package. (FIG. 1). Table 1 shows the evaluation results of this package.

【００４０】実施例２ 一方、プリプレグＣを用い、片面に18μm の電解銅箔、
片面に離型フィルムを配置し、 200℃,20kgf/cm2にて２
時間積層成形して片面銅張積層板を作成した。内層とな
る、厚さ 250μｍのCu：99.86 重量％、Fe：0.11重量
％、Ｐ：0.03重量％の合金板を実施例１と同様に加工し
て、両面に実施例１と同じ大きさ、高さ、個数の突起を
作成した。更に 0.6mmφのクリアランスホールをあけ、
同様に上下にプリプレグＢを配置し、その両側に上記で
得た片面銅張積層板を置き、同一条件で積層成形した。Example 2 On the other hand, using prepreg C, an 18 μm electrolytic copper foil
Place a release film on one side and apply 2 at 200 ° C, 20kgf / cm 2
A single-sided copper-clad laminate was prepared by lamination molding for a time. A 250 μm thick alloy plate of Cu: 99.86% by weight, Fe: 0.11% by weight, and P: 0.03% by weight as an inner layer was processed in the same manner as in Example 1, and the same size and height as in Example 1 were formed on both surfaces. Well, the number of protrusions was created. Drill a 0.6mmφ clearance hole,
Similarly, the prepreg B was placed on the upper and lower sides, and the single-sided copper-clad laminate obtained above was placed on both sides thereof, and laminated and formed under the same conditions.

【００４１】クリアランスホール箇所は、クリアランス
ホール部の金属に接触しないように、ドリルにて中央に
孔径0.20mmのスルーホールをドリルであけ、デスミア処
理後、銅メッキを無電解、電解メッキにて行い、孔内に
17μm の銅メッキ層を形成した。表裏に液状エッチング
レジストを塗布、乾燥して溶剤を除去してからポジフィ
ルムを重ねて、露光、現像してから、表裏回路を形成し
た。突起部上の積層板部、ボンディングパッド及びボー
ルパッド部以外にメッキレジストを形成し、ニッケル、
金メッキを施してから、中央銅板突起部上の積層板部の
基材をルーターで切削除去し、プリント配線板を完成し
た。その後、同様に半導体チップを接着、樹脂封止して
半導体パッケージとした。特性評価結果を表１に示す。In the clearance hole, a through hole having a hole diameter of 0.20 mm was drilled at the center with a drill so as not to come into contact with the metal in the clearance hole. After desmearing, copper plating was performed by electroless and electrolytic plating. In the hole
A 17 μm copper plating layer was formed. After applying a liquid etching resist on the front and back and drying to remove the solvent, a positive film was overlaid, exposed and developed, and then a front and back circuit was formed. A plating resist is formed on a portion other than the laminated plate portion, the bonding pad and the ball pad portion on the protrusion, and nickel,
After gold plating, the base material of the laminated board portion on the central copper plate projection was cut and removed by a router to complete a printed wiring board. Thereafter, the semiconductor chip was similarly bonded and resin-sealed to obtain a semiconductor package. Table 1 shows the characteristic evaluation results.

【００４２】比較例１ 実施例１のプリプレグＣを２枚使用し、上下に電解銅箔
を配置し、 200℃, 20kgf/cm2,真空下に２時間積層成形
し、両面銅張積層板を得た。所定の位置に孔径0.25mmφ
のスルーホールをドリルであけ、デスミア処理後に銅メ
ッキを施した。この板の上下に公知の方法で回路を形成
し、ニッケルメッキ、金メッキを施した。これは半導体
チップを搭載する箇所に放熱用のスルーホールが形成さ
れており、この上に銀ペーストで半導体チップを接着
し、ワイヤボンディング後、エポキシ封止用コンパウン
ドで実施例１と同様に樹脂封止した（図２）。このパッ
ケージの試験結果を表１に示す。Comparative Example 1 Two prepregs C of Example 1 were used, and electrolytic copper foils were arranged on the upper and lower sides, and laminated and formed at 200 ° C., 20 kgf / cm 2 , and vacuum for 2 hours. Obtained. 0.25mmφ hole diameter at specified position
Was drilled and copper plated after desmear treatment. Circuits were formed on and under the plate by a known method, and nickel plating and gold plating were performed. This has a through hole for heat dissipation formed at the place where the semiconductor chip is mounted. The semiconductor chip is adhered on this with a silver paste, and after wire bonding, it is sealed with a resin for epoxy sealing in the same manner as in Example 1. Stopped (FIG. 2). Table 1 shows the test results of this package.

【００４３】比較例２ 比較例１のプリント配線板の半導体チップ搭載部分をザ
グリマシーンにて上下くり抜いてから、裏面に厚さ 200
μｍの銅板を、上記ノーフロープリプレグを打ち抜いた
ものを使用して、加熱、加圧下に同様に接着させ、放熱
板付きプリント配線板を作成した。これはややソリが発
生した。この放熱板に直接銀ペーストで半導体チップを
接着させ、ワイヤボンディングで接続後、液状エポキシ
樹脂で封止した（図３）。このパッケージの試験結果を
表１に示す。COMPARATIVE EXAMPLE 2 A semiconductor chip mounting portion of the printed wiring board of Comparative Example 1 was hollowed up and down with a counterbore machine.
A μm copper plate was similarly adhered under heat and pressure using a punched-out no-flow prepreg to prepare a printed wiring board with a heat sink. This slightly warped. A semiconductor chip was directly bonded to the heat sink with a silver paste, connected by wire bonding, and sealed with a liquid epoxy resin (FIG. 3). Table 1 shows the test results of this package.

【００４４】[0044]

【表１】 実施例１ 実施例２ 比較例１ 比較例２ 吸湿後の耐熱性(1) 常態 異常なし 異常なし 異常なし 異常なし 120hrs 異常なし 異常なし 異常なし 異常なし 144hrs 異常なし 異常なし 一部剥離 異常なし 168hrs 異常なし 異常なし 一部剥離 一部剥離 吸湿後の耐熱性(2) 常態 異常なし 異常なし 異常なし 異常なし 24hrs 異常なし 異常なし 一部剥離 異常なし 48hrs 異常なし 異常なし 剥離大 一部剥離 72hrs 異常なし 異常なし 剥離大 剥離大 96hrs 異常なし 異常なし ワイヤ 切れ 剥離大 120hrs 異常なし 異常なし ワイヤ 切れ ワイヤ 切れ 144hrs 異常なし 一部剥離 − ワイヤ 切れ 168hrs 一部剥離 一部剥離 − − ガラス転移温度 (℃) ２３３ − − − プレッシャークッ 常態 ４×1014 − − − カー処理後の絶縁 200hrs ３×1012 抵抗値 （Ω） 500hrs ３×1011 700hrs ５×1010 1000hrs ２×1010 耐マイグレーシ 常態 ５×1013 − − − ョン性 200hrs ６×1011 （Ω） 500hrs ３×1011 700hrs ５×1010 1000hrs ３×1010 放熱性 (℃) ３５ ３７ ５４ ４６ [Table 1] Example 1 Example 2 Comparative example 1 Comparative example 2 Heat resistance after moisture absorption (1) Normal condition No abnormality No abnormality No abnormality No abnormality 120hrs No abnormality No abnormality No abnormality No abnormality 144hrs No abnormality No abnormality Partial peeling No abnormalities 168hrs No abnormalities No abnormalities Partial peeling Partial peeling Heat resistance after moisture absorption (2) Normal No abnormalities No abnormalities No abnormalities No abnormalities 24hrs No abnormalities No abnormalities Partial peeling No abnormalities 48hrs No abnormalities No abnormalities Large peeling Partial peeling 72hrs No abnormality No abnormality Large peeling Large peeling 96hrs No abnormality No abnormality Wire breakage Large 120hrs No abnormality No abnormality Wire breakage Wire breakage 144hrs No abnormality Partial peeling-Wire breakage 168hrs Partial peeling Partial peeling-- Glass transition temperature (℃ ) 233 - - - pressure cookie normal 4 × 10 14 - - - car processing after the insulating 200hrs 3 × 10 12 resistance (Ω) 500hrs 3 × 10 11 700hrs 5 × 10 10 1000hrs × 10 10 resistance migrated normally 5 × 10 13 - - - tio emission properties 200hrs 6 × 10 11 (Ω) 500hrs 3 × 10 11 700hrs 5 × 10 10 1000hrs 3 × 10 10 heat radiation (℃) 35 37 54 46

【００４５】＜測定方法＞ 1)吸湿後の耐熱性 JEDEC STANDARD TEST METHOD A113-A LEVEL3：30℃・60
％RHで所定時間処理後、220 ℃リフローソルダー３サイ
クル後の基板の異常の有無について、断面観察及び電気
的チェックによって確認した。 2)吸湿後の電気絶縁性 JEDEC STANDARD TEST METHOD A113-A LEVEL2：85℃・60
％RHで所定時間（Max.168hrs.)処理後、220 ℃リフロー
ソルダー３サイクル後の基板の異常の有無を断面観察及
び電気的チェックによって確認した。 3)ガラス転移温度 DMA 法にて測定した。 4)プレッシャークッカー処理後の絶縁抵抗値 端子間（ライン／スペース=70/70μm)の櫛型パターンを
作成し、この上に、それぞれ使用したプリプレグを配置
して同様に積層成形したものを、 121℃・２気圧で所定
時間処理した後、25℃・60％RHで２時間後処理し、500V
DCを印加60秒で、その端子間の絶縁抵抗値を測定した。 5)耐マイグレーション性 4)の試験片を用い、85℃・85％RH、50VDC 印加して端子
間の絶縁抵抗値を測定した。 6)放熱性 パッケージを同一マザーボードプリント配線板にハンダ
ボールで接着させ、800 時間連続使用してから、パッケ
ージの温度を測定した。<Measurement method> 1) Heat resistance after moisture absorption JEDEC STANDARD TEST METHOD A113-A LEVEL3: 30 ℃ ・ 60
After the treatment at% RH for a predetermined time, the presence or absence of abnormality in the substrate after three cycles of reflow soldering at 220 ° C. was confirmed by cross-sectional observation and electrical check. 2) Electric insulation after moisture absorption JEDEC STANDARD TEST METHOD A113-A LEVEL2: 85 ℃ ・ 60
After treatment at% RH for a predetermined time (Max. 168 hrs.), The presence or absence of abnormality in the substrate after three cycles of reflow soldering at 220 ° C. was confirmed by cross-sectional observation and electrical check. 3) Glass transition temperature Measured by the DMA method. 4) Insulation resistance value after pressure cooker treatment A comb-shaped pattern between terminals (line / space = 70/70 μm) was created, and the prepregs used were placed on each of them and laminated and molded in the same manner. After processing at 2 ℃ for 2 hours at 25 ℃ and 60% RH, 500V
After applying DC for 60 seconds, the insulation resistance value between the terminals was measured. 5) Migration resistance Using the test piece of 4), the insulation resistance between terminals was measured by applying 50 VDC at 85 ° C and 85% RH. 6) Heat dissipation The package was adhered to the same motherboard printed wiring board with solder balls and used continuously for 800 hours, and then the temperature of the package was measured.

【００４６】[0046]

【発明の効果】プリント配線板の片面に、半導体チップ
が固定され、半導体回路導体がその周囲のプリント配線
板表面に形成された回路導体とワイヤボンディングで接
続されており、少なくとも、該表面のプリント配線板上
の信号伝播回路導体が、プリント配線板の反対面に形成
された回路導体もしくは該ハンダボールでの接続用導体
パッドとスルーホール導体で結線されており、半導体チ
ップが樹脂封止されている構造の半導体プラスチックパ
ッケージであって、該プリント配線板とほぼ同じ大きさ
の金属板がプリント配線板の厚さ方向のほぼ中央に配置
され、表裏回路導体と多官能性シアン酸エステル樹脂組
成物といった耐熱性樹脂組成物で絶縁されており、金属
板に少なくとも１個以上のスルーホール径より大きい径
のクリアランスホールがあけられ、孔壁と金属板とは樹
脂組成物で絶縁されており、半導体チップとほぼ同じ大
きさの内層の金属突起の一部が、少なくとも２個以上表
面に露出されており、該露出金属板の表面に半導体チッ
プが固定され、裏面には金属板の突起が露出しており、
発生した熱はこの金属板を通して逃げるようにしたマル
チチップモジュール用プラスチックパッケージとするこ
とにより、半導体チップの下面からの吸湿がなく、吸湿
後の耐熱性、すなわちポップコーン現象が大幅に改善で
きるとともに、熱放散性も改善でき、加えて大量生産性
にも適しており、経済性の改善された、新規な構造の半
導体プラスチックパッケージを得ることができた。According to the present invention, a semiconductor chip is fixed to one surface of a printed wiring board, and a semiconductor circuit conductor is connected by wire bonding to a circuit conductor formed on the surface of the printed wiring board around the semiconductor chip. The signal propagation circuit conductor on the wiring board is connected to the circuit conductor formed on the opposite surface of the printed wiring board or the conductor pad for connection with the solder ball with a through-hole conductor, and the semiconductor chip is sealed with resin. Wherein a metal plate having substantially the same size as the printed wiring board is disposed at substantially the center in the thickness direction of the printed wiring board, and the front and back circuit conductors and the polyfunctional cyanate resin composition are provided. The metal plate is insulated with a heat-resistant resin composition such as The hole wall and the metal plate are insulated with the resin composition, and at least two or more of the inner layer metal protrusions having substantially the same size as the semiconductor chip are exposed on the surface. The semiconductor chip is fixed on the surface of the exposed metal plate, and the projection of the metal plate is exposed on the back surface,
By using a plastic package for a multi-chip module that allows the generated heat to escape through this metal plate, there is no moisture absorption from the lower surface of the semiconductor chip, and the heat resistance after moisture absorption, i.e., the popcorn phenomenon, can be significantly improved. It was possible to obtain a semiconductor plastic package having a novel structure, which has improved heat dissipation, is suitable for mass production, and has improved economy.

【図面の簡単な説明】[Brief description of the drawings]

【図１】実施例１の半導体プラスチックパッケージの製
造工程。FIG. 1 shows a manufacturing process of a semiconductor plastic package according to a first embodiment.

【図２】比較例１の半導体プラスチックパッケージの製
造工程。FIG. 2 shows a manufacturing process of the semiconductor plastic package of Comparative Example 1.

【図３】比較例２の半導体プラスチックパッケージの製
造工程。FIG. 3 shows a manufacturing process of the semiconductor plastic package of Comparative Example 2.

【符号の説明】[Explanation of symbols]

(a) 液状エッチングレジスト、(b) 金属板、(c) ネガフ
ィルム、(d) クリアランスホール、(e) 金属箔、(f) プ
リプレグＢ、(g) 上下回路導通用スルーホール、(h) プ
リプレグＣ、(i) 封止樹脂、(j) 金ワイヤ、(k) 半導体
チップ、(l) 銀ペースト、(m) メッキレジスト、(n) ハ
ンダボール、(o) 熱放散用スルーホール(a) Liquid etching resist, (b) metal plate, (c) negative film, (d) clearance hole, (e) metal foil, (f) prepreg B, (g) through-hole for vertical circuit conduction, (h) Prepreg C, (i) sealing resin, (j) gold wire, (k) semiconductor chip, (l) silver paste, (m) plating resist, (n) solder ball, (o) through-hole for heat dissipation

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 プリント配線板の片面に、半導体チップ
が固定され、半導体回路導体がその周囲のプリント配線
板表面に形成された回路導体とワイヤボンディングで接
続されており、少なくとも、該表面のプリント配線板上
の信号伝播回路導体が、プリント配線板の反対面に形成
された回路導体もしくは該ハンダボールでの接続用導体
パッドとスルーホール導体で結線されており、少なくと
も半導体チップが樹脂封止されている構造の半導体プラ
スチックパッケージであって、該プリント配線板とほぼ
同じ大きさの金属板がプリント配線板の厚さ方向のほぼ
中央に配置され、表裏回路導体と熱硬化性樹脂組成物で
絶縁されており、且つ、金属板に少なくとも１個以上の
スルーホール径より大きい径のクリアランスホールが形
成され、孔壁と金属板とは樹脂組成物で絶縁されてお
り、半導体チップとほぼ同じ大きさの内層の金属突起の
一部が片面に少なくとも２箇所以上表面に露出してお
り、この露出金属表面に半導体チップが固定されてい
て、且つ、半導体チップの固定用の金属板突起面とは反
対側の表面の一部分に熱放散用の金属板突起面が露出し
てなることを特徴とするマルチチッププラスチックパッ
ケージ。A semiconductor chip is fixed to one side of a printed wiring board, and a semiconductor circuit conductor is connected by wire bonding to a circuit conductor formed on the surface of the printed wiring board around the semiconductor chip. A signal propagation circuit conductor on the wiring board is connected to a circuit conductor formed on the opposite surface of the printed wiring board or a conductor pad for connection with the solder ball by a through-hole conductor, and at least the semiconductor chip is resin-sealed. A semiconductor plastic package having the structure described above, wherein a metal plate having substantially the same size as the printed wiring board is disposed substantially at the center in the thickness direction of the printed wiring board, and is insulated from the front and back circuit conductors by a thermosetting resin composition. And at least one or more clearance holes having a diameter larger than the diameter of the through hole are formed in the metal plate. The board is insulated with a resin composition, and at least two or more inner metal protrusions of the same size as the semiconductor chip are exposed on one surface, and the semiconductor chip is fixed to the exposed metal surface. A multi-chip plastic package, wherein a metal plate projection surface for heat dissipation is exposed on a part of a surface of the semiconductor chip opposite to the metal plate projection surface for fixing. 【請求項２】 該金属板が銅95重量％以上の銅合金、或
いは純銅である請求項１に記載のマルチチッププラスチ
ックパッケージ。2. The multi-chip plastic package according to claim 1, wherein the metal plate is made of a copper alloy containing 95% by weight or more of copper or pure copper. 【請求項３】 該絶縁樹脂組成物が、多官能性シアン酸
エステル、該シアン酸エステルプレポリマーを必須成分
とする熱硬化性樹脂組成物である請求項１に記載のマル
チチッププラスチックパッケージ。3. The multi-chip plastic package according to claim 1, wherein the insulating resin composition is a thermosetting resin composition containing a polyfunctional cyanate ester and the cyanate ester prepolymer as essential components.
JP10000975A 1997-12-10 1998-01-06 Multi-chip plastic package Pending JPH11195745A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP10000975A JPH11195745A (en) 1998-01-06 1998-01-06 Multi-chip plastic package
EP98310022A EP0926729A3 (en) 1997-12-10 1998-12-08 Semiconductor plastic package and process for the production thereof
US09/207,115 US6376908B1 (en) 1997-12-10 1998-12-08 Semiconductor plastic package and process for the production thereof
KR1019980054122A KR19990062959A (en) 1997-12-10 1998-12-10 Semiconductor plastic package and manufacturing method thereof
TW87120501A TW401723B (en) 1997-12-10 1998-12-10 Semiconductor plastic package and process for the production thereof
US10/036,385 US6720651B2 (en) 1997-12-10 2002-01-07 Semiconductor plastic package and process for the production thereof
US10/790,039 US20040171189A1 (en) 1997-12-10 2004-03-02 Semiconductor plastic package and process for the production thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10000975A JPH11195745A (en) 1998-01-06 1998-01-06 Multi-chip plastic package

Publications (1)

Publication Number Publication Date
JPH11195745A true JPH11195745A (en) 1999-07-21

Family

ID=11488628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10000975A Pending JPH11195745A (en) 1997-12-10 1998-01-06 Multi-chip plastic package

Country Status (1)

Country Link
JP (1) JPH11195745A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010018944A (en) * 1999-08-24 2001-03-15 마이클 디. 오브라이언 Semiconductor package
EP2259668A1 (en) * 2008-03-27 2010-12-08 Ibiden Co., Ltd. Method for manufacturing multilayer printed wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010018944A (en) * 1999-08-24 2001-03-15 마이클 디. 오브라이언 Semiconductor package
EP2259668A1 (en) * 2008-03-27 2010-12-08 Ibiden Co., Ltd. Method for manufacturing multilayer printed wiring board
EP2259668A4 (en) * 2008-03-27 2011-12-14 Ibiden Co Ltd Method for manufacturing multilayer printed wiring board
US8237060B2 (en) 2008-03-27 2012-08-07 Ibiden Co., Ltd. Method for manufacturing multilayer printed wiring board

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