JPH11238801A - Multi-layer structure of semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a decline of wiring reliability arising from a stress, in an area between upper and lower plugs in a multi-layer wiring structure of a semiconductor device having a stack structure. SOLUTION: In a multi-layer wiring structure causing a resistance variation due to long time storage at high temperature, a void 40 is observed in wiring 4 between an upper plug 3 and a lower plug 6. Parts 43, 44 between upper and lower plugs 3, 6 have crystal grains of smaller size than that of other parts, and have different plane orientation from that of other parts. For this reason, in order to raise wiring reliability, a wiring stress is lessened by shifting a center of contact surfaces between upper and lower plugs, or sputtering temperature is set so as not to give rise to crystal grain boundaries between upper and lower plugs, when a wiring layer of aluminum or an aluminum alloy is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multilayer wiring structure of a semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, there has been a problem that wiring reliability is reduced due to miniaturization of wiring in VLSI. In particular, due to the progress of multilayer wiring, a structure in which plugs made of a high melting point metal such as W (tungsten) or TiN or a compound thereof are provided on the upper and lower surfaces of the wiring so as to face each other with the wiring therebetween, that is, a stack. Although the structure is used in a multilayer wiring structure, in this stack structure, there is a problem that the wiring at a portion sandwiched between plugs has low reliability.

As a method of improving the reliability of wiring, for example, as a first conventional example, in order to prevent stress migration in which wiring is disconnected due to stress from a protective film, a region having a large grain size is provided in a region where most of the current flows. While forming a wiring layer, a wiring layer having a small grain size is formed at a position where stress is relatively likely to be applied, such as around a wiring (particularly, a side wall or an upper end) (Japanese Patent Laid-Open No. 5-275426). Gazette).

Further, as a second conventional example, in a stack structure, the width of a wiring is made smaller than the width of a lower connection hole,
In addition, it has been proposed to extend the bottom of the upper-layer connection hole to the lower-layer connection hole and to reinforce it so as to surround the wiring (see JP-A-8-167609).

[0005]

However, in the first conventional example, since the wiring is formed by forming a wiring layer having a small grain size on the side wall of the wiring layer having a large grain size, the width of the wiring becomes too large. It is not suitable for miniaturization.

In the second conventional example, first, it is indispensable that the width of the upper and lower connection holes is larger than the width of the wiring, so that this is not suitable for miniaturization. Further, the wiring is surrounded by the high melting point metal or its compound, but no consideration is given to the stress caused by the high melting point metal or its compound around the wiring.

In view of the above problems, the present invention provides a multilayer wiring structure for a semiconductor device having a stack structure, which reduces the reliability of wiring, particularly, the stress in a region sandwiched between an upper plug and a lower plug. It is an object to suppress a decrease in reliability of wiring due to the problem.

[0008]

Means for Solving the Problems To solve the above-mentioned problems, a solution taken by the invention of claim 1 is to provide a multi-layer wiring structure of a semiconductor device, a substrate and a two-layer structure formed on the substrate. The above-mentioned wiring layer, an upper-layer plug for electrically connecting the wiring formed on one of the two or more wiring layers and the upper-layer wiring, and sandwiching the upper-layer plug and the wiring And a lower-layer plug for electrically connecting the wiring and the lower-layer wiring or the substrate. When viewed from a direction perpendicular to the substrate surface, contact between the upper-layer plug and the wiring is provided. The distance between the center of the surface and the center of the contact surface between the lower plug and the wiring is set to be approximately 2/3 or more of the diameter of the upper and lower plugs.

According to a second aspect of the present invention, there is provided a semiconductor device having a multi-layer wiring structure including a substrate, two or more wiring layers formed on the substrate, and the two or more wiring layers. An upper-layer plug electrically connecting the wiring formed on one of the wiring layers and the upper-layer wiring, and the upper-layer plug and the lower-layer plug provided opposite to each other with the wiring interposed therebetween; A lower-layer plug electrically connecting the wiring or the substrate; and a lower portion of the one wiring layer is formed with a protruding portion that protrudes toward the lower layer and is in contact with the lower-layer plug. The height protruding from the lower surface of the one wiring layer is set to be approximately 1/3 or less of the diameter of the upper and lower plugs.

According to a third aspect of the present invention, there is provided a semiconductor device having a multi-layer wiring structure, a substrate, two or more wiring layers formed on the substrate, and the two or more wiring layers. An upper-layer plug electrically connecting the wiring formed on one of the wiring layers and the upper-layer wiring, and the upper-layer plug and the lower-layer plug provided opposite to each other with the wiring interposed therebetween; A lower-layer plug electrically connecting the wiring or the substrate, wherein the wiring is configured so as not to have a crystal grain boundary in a region sandwiched between the opposed upper-layer and lower-layer plugs. It is.

According to a fourth aspect of the present invention, there is provided a semiconductor device having a multi-layer wiring structure, a substrate, two or more wiring layers formed on the substrate, and the two or more wiring layers. An upper-layer plug for electrically connecting a wiring formed in one wiring layer and the upper-layer wiring, and the upper-layer plug and the lower-layer wiring provided opposite to each other with the upper-layer plug interposed therebetween. Or a lower plug electrically connected to the substrate, wherein a depression is formed on the upper surface of the one wiring layer, the depression being in contact with the upper layer plug. The depth of depression from the upper surface is set to be approximately 1/3 or less of the diameter of the upper and lower plugs.

[0012] Further, according to a fifth aspect of the present invention, there is provided a semiconductor device comprising: a substrate; two or more wiring layers formed on the substrate; and one of the two or more wiring layers. An upper-layer-side plug for electrically connecting the formed wiring and the upper-layer wiring, and an upper-layer plug provided opposite to the upper-layer plug with the wiring therebetween, and electrically connecting the wiring to the lower-layer wiring or the substrate. A lower-layer plug connected to the wiring, and a difference in thermal expansion coefficient of a material between the wiring and at least one of the upper-layer and lower-layer plugs is sandwiched between the upper-layer and lower-layer plugs of the wiring. The size is so small that voids do not occur in the region that has been removed.

According to a sixth aspect of the present invention, in the semiconductor device of the fifth aspect, the wiring and at least one of the upper and lower plugs are formed of the same material. .

According to a seventh aspect of the present invention, in the semiconductor device of the sixth aspect, the wiring and at least one of the upper and lower plugs are made of aluminum or an aluminum alloy. Alternatively, it has a laminated structure of aluminum or an aluminum alloy and a high melting point metal, a high melting point metal alloy, or a composite layer thereof.

According to another aspect of the present invention, there is provided a semiconductor device having a multi-layer wiring structure, a substrate, two or more wiring layers formed on the substrate, and the two or more wiring layers. An upper-layer plug electrically connecting the wiring formed on one of the wiring layers and the upper-layer wiring, and the upper-layer plug and the lower-layer plug provided opposite to each other with the wiring interposed therebetween; A lower-layer plug for electrically connecting a wiring or the substrate, wherein the one wiring layer has a film of a high-melting-point metal or a high-melting-point metal alloy formed on an upper surface thereof; The upper plug is in contact with this high melting point metal or high melting point metal alloy film.

According to a ninth aspect of the present invention, there is provided a semiconductor device having a multi-layer wiring structure, a substrate, two or more wiring layers formed on the substrate, and the two or more wiring layers. An upper-layer plug electrically connecting the wiring formed on one of the wiring layers and the upper-layer wiring, and the upper-layer plug and the lower-layer plug provided opposite to each other with the wiring interposed therebetween; A wiring or a lower-layer plug for electrically connecting the wiring to the substrate, wherein the one wiring layer has a refractory metal film formed on the lower surface thereof, and the thickness of the refractory metal film is 10 nm. It is set to be equal to or less than 80 nm.

According to a tenth aspect of the present invention, as a method of manufacturing a multilayer wiring structure of a semiconductor device, a first opening is formed in a first insulating film formed on a substrate.
Forming a lower-layer plug in the first opening; forming a wiring on the first insulating film and the lower-layer plug; forming a second insulating film on the wiring; 2
Forming a second opening facing the first opening in the insulating film, and forming an upper-layer plug in the second opening. The distance between the upper surface of the lower plug and the upper surface of the first insulating film is made to be approximately 1/3 or less of the diameter of the upper plug and the lower plug by using a method or an etch-back method. It is.

According to another aspect of the present invention, there is provided a method of manufacturing a multilayer wiring structure of a semiconductor device, comprising: forming a first opening in a first insulating film formed on a substrate;
Forming a lower plug in the first opening, forming a wiring having at least a layer made of aluminum or an aluminum alloy on the first insulating film and the lower plug, Forming a second insulating film, forming a second opening in the second insulating film facing the first opening, and forming an upper-layer plug in the second opening; And forming the wiring by sputtering the aluminum or aluminum alloy layer of the wiring so that the wiring does not have a crystal grain boundary in a region sandwiched between the opposed upper and lower plugs. Is formed at a deposition temperature of about 200 ° C. or more.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a multilayer wiring structure of a semiconductor device, comprising the steps of: forming a first opening in a first insulating film formed on a substrate; Forming a lower plug in the first opening, and forming a wiring on the first insulating film;
A second insulating film is formed on the wiring, a second opening facing the first opening is formed in the second insulating film, and an upper-layer plug is formed in the second opening. Forming the lower plug and the wiring.
Aluminum or an aluminum alloy is deposited in the first opening and on the first insulating film by a method D or by a CVD method and sputtering to form a lower plug and a wiring.

[0020]

FIG. 1 is a diagram showing a structure of a sample for electrically detecting the influence of a stack structure in a multilayer wiring structure of a semiconductor device.

FIG. 1A is a sectional view of this sample. In FIG. 1A, 1 is a semiconductor substrate, 2 is a first insulating film, 3 is a contact buried metal (lower plug) made of W (tungsten) formed on a two-layer film of Ti and TiN, Reference numeral 4 denotes a Cu-containing Al formed on a two-layer film of Ti and TiN and having a TiN film thereon.
A first wiring made of an alloy, 5 is a second insulating film, 6 is a through-hole burying metal (upper-layer plug) having the same metal structure as the contact burying metal 3, and 7 is a metal similar to the first wiring 4. A second wiring as an upper layer wiring having a film configuration, 8 is a silicon nitride film as a protective film, and 9 is a polyimide film coated with an LSI chip.

FIG. 1B is a perspective view of a portion of the sample of FIG. 1A including the first wiring 4 and the contact buried metal 3 and the through-hole buried metal 6 connected above and below it. In this sample, the wiring length of the first wiring 4 is 31 mm, and 1000 contact holes and 1000 through holes are provided respectively. The wiring width of the first wiring 4 of each sample is various sizes of 0.4 μm to 1.0 μm, and the diameter of the contact hole and the through hole is equal to the wiring width.

Voltage / current characteristics are measured between pad portions 4A and 4B provided at both ends of the first wiring 4. The measurement of the voltage / current characteristics corresponds to measuring the resistance value of the first wiring 4 having the contact hole burying metal 3 and the through hole burying metal 6 on the upper and lower sides. I mean,
Since the semiconductor substrate 1 electrically connected to the contact buried metal 3 is made of Si, the resistance value is higher than that of the first wiring 4 made of metal, and the through hole buried metal 6
This is because each of the second wirings 7 electrically connected to each other has an electrically independent structure in the wiring layer.

FIG. 2 shows the sample shown in FIG.
FIG. 9 is a diagram showing a result of measuring a voltage-current characteristic between pad portions 4A and 4B, that is, a change in resistance of a first wiring 4 before and after high-temperature storage in the vicinity. In the figure, (a) is a graph showing the relationship between the time when the sample was stored at 250 ° C. and the defect rate of the wiring, wherein the ordinate is the defect rate (%) and the abscissa is the 250%.
Storage time in ° C. (h). Here, the resistance variation is 2
Wiring exceeding 0% is determined to be defective, and the defect rate is determined. Also, (b) is a graph showing the relationship between the wiring width and its resistance variation after the sample was stored at 250 ° C. for 1000 hours, where the vertical axis represents the resistance variation (%) and the horizontal axis represents the wiring width (μ).
m).

FIG. 3 is a graph showing the relationship between the storage temperature and the time until the cumulative failure rate reaches 0.1%, that is, the cumulative failure arrival time, for the sample shown in FIG. here,
As in FIG. 2, a wiring in which the resistance variation exceeds 20% is determined to be defective. The vertical axis represents the cumulative failure arrival time (h), and the horizontal axis represents 1000 / storage temperature (1 / K). FIG. 3 shows that when the storage temperature is around 250 ° C., the cumulative failure arrival time is the shortest. From FIG. 3, it can be seen that the resistance variation of the wiring is caused by a failure due to migration of the Al alloy due to stress, that is, a so-called stress migration failure.

FIG. 4 is a diagram showing the relationship between the wiring structure and the yield rate. FIG. 4 shows a wiring structure A in which opposing upper layer plugs and lower layer plugs are formed as shown in FIG. 1, a wiring structure B in which only lower layer plugs are formed, and only an upper layer plug formed. The percentage of non-defective products after storage at 200 ° C. for 1000 hours is shown for three types of wiring structures, namely, wiring structure C. Again, the resistance variation is 20
% Is determined as defective, and the non-defective rate is determined.
FIG. 4 shows that the problem to be solved by the present invention is a characteristic problem in the wiring structure in which the upper plug and the lower plug opposed to each other are formed.

FIG. 5 shows a wiring structure in which upper and lower plugs opposed to each other as shown in FIG. 1 are formed, and the resistance variation of which exceeds 20% after storage at 200 ° C. for 1000 hours. FIG. 3 is a cross-sectional view showing the result of observation with a transmission electron microscope. FIG. 5 also shows the result of measuring the crystallinity of the Al alloy of the first wiring 4 by X-ray diffraction.

As shown in FIG. 5, a void 40 was observed in the first wiring 4 sandwiched between the contact hole burying metal 3 as the lower layer plug and the through hole burying metal 6 as the upper layer plug. . Further, wiring portions 41 and 42 sandwiched between the first insulating film 2 and the second insulating film 5.
The plane orientation of the Al alloy in (3) is (111), whereas the plane orientation of the Al alloy in the wiring portions 43 and 44 sandwiched between the contact hole burying metal 3 and the through hole burying metal 6 is (311) or (022). )Met. Further, a crystal grain boundary 45 is provided in a region sandwiched between the contact hole burying metal 3 and the through hole burying metal 6, and the size of the crystal grains of the wiring portions 43 and 44 is reduced by the crystal in the wiring portions 41 and 42. Smaller than a grain.

FIG. 6 shows that, in the wiring structure of FIG. 5, the temperature was changed from 400 ° C. to 25 ° C. in the right half region X of the portion sandwiched between the contact hole burying metal 3 and the through hole burying metal 6. FIG. 9 is a diagram illustrating a result of simulating an internal stress that sometimes occurs by a finite element method.

The stress applied to the flat portion of the first wiring 4 is 200 to 300 MPa (megapascal). On the other hand, the stress generated in the portion where the through-hole buried metal 6 has entered the first wiring 4 is much higher, and the upper surface of the contact buried metal 3 is lower than the upper surface of the first insulating film 2 ( 6 (a)) was 457 MPa, and when the upper surface of the contact burying metal 3 was flush with the upper surface of the first insulating film 2 (FIG. 6 (b)), it was 449 MPa.

From these experiments and simulations, it is considered that the stress migration failure in the multilayer wiring structure of the semiconductor device according to the present invention is caused by the following factors. That is, (1) strong stress is applied to the wiring portion sandwiched between the upper layer plug and the lower layer plug, particularly (2) in the case where the upper layer plug enters the wiring, and (3) the wiring portion The crystal grains are small and the crystal plane orientation is (311) or (0
It is assumed that stress migration occurs when stored at high temperature due to the plane orientation weak against stress as in 22).

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) A first embodiment of the present invention relates to a wiring structure having opposing upper-layer plugs and lower-layer plugs. And the degree of overlap between the lower plug and the lower plug is reduced to reduce the stress applied to the wiring.

FIG. 7 is a diagram showing the relationship between the degree of overlap between the upper plug and the lower plug and the yield rate in a wiring structure having upper and lower plugs facing each other. Here, the diameter of the upper and lower plugs is 0.6
μm, and the degree of overlap is 0.6 μm, 0.3 μm, 0.
2 μm (that is, the center of the contact surface between the upper plug and the wiring when viewed from the direction perpendicular to the substrate surface,
The distance between the lower plug and the center of the contact surface with the wiring
0 μm, 0.3 μm, 0.4 μm).
In addition, the non-defective product rate is as follows:
When the resistance was changed over 20% when stored for a long time, it was determined to be defective and determined.

As shown in FIG. 7, the degree of overlap is 0.2 μm.
m, the non-defective rate is 100%, and the degree of overlap is 0.
It was found that stress migration failure did not occur when the thickness was 2 μm or less. Therefore, the distance between the center of the contact surface between the upper plug and the wiring and the center of the contact surface between the lower plug and the wiring is 0.4 μm or more, that is, approximately 2/3 or more of the diameter of the upper and lower plugs. This makes it possible to form a good multilayer wiring structure in which stress migration failure hardly occurs.

(Second Embodiment) FIG. 8A is a sectional view showing a multilayer wiring structure of a semiconductor device according to a second embodiment of the present invention.

The multilayer wiring structure of the semiconductor device shown in FIG. 8A is manufactured as follows. First, a contact opening as a first opening is provided in a first insulating film 2 on a semiconductor substrate by dry etching, a two-layer film of Ti and TiN is formed by a sputtering method or the like, and then W is deposited by a CVD method. Embed. And W and Ti and Ti
The N-layer film is etched back to form a contact buried metal 3 (lower plug) in the contact opening. A two-layer film of Ti and TiN is formed thereon, an Al alloy containing Cu is formed on the two-layer film, and a TiN film is further formed thereon to form the first wiring 4. . A second insulating film 5 is formed on the first wiring 4, and a through hole buried metal 6 (upper layer side) is formed in a through hole opening as a second opening in the same manner as the formation of the contact buried metal 3. Plug).

In the multilayer wiring structure of the semiconductor device shown in FIG. 8A, the amount of over-etching when etching back the two-layer film of W and Ti and TiN when forming the lower layer side plug is changed to change the recess d1. Different samples were produced. The recess d <b> 1 is formed on the lower surface of the wiring layer on which the first wiring 4 is formed, and projects to the lower layer side and has a height of the protrusion 4 </ b> H with which the contact embedded metal 3 comes into contact with the lower surface of the wiring layer. That is. FIG. 8B is a graph showing the percentage defective when these samples were stored at 250 ° C. for 168 hours. In this case as well, those having a resistance variation exceeding 20% are determined to be defective, and the defect rate is determined. FIG.
In (b), the vertical axis represents the defect rate (%), and the horizontal axis represents the recess (μm). The diameter of the upper and lower plugs is 0.6 μm.

As apparent from FIG. 8B, the recess d
When 1 is 0.2 μm or less, the failure rate becomes 0%, and no stress migration failure occurs. When the cross section of the sample after the measurement of the defect rate was observed with a scanning electron microscope, the following was found. In the sample in which the recess d1 is larger than 0.2 μm, a crystal grain boundary almost always exists in a region on the contact buried metal 3 in the first wiring 4.
On the other hand, in the sample in which the recess d1 is 0.2 μm or less, almost no crystal grain boundary exists in the region on the contact buried metal 3 in the first wiring 4, and the crystal grain in this region does not exist. Was almost the same size as the other regions.

From these results, the recess d1 was 0.2
It is considered that the case of μm is a boundary of whether or not the stress migration failure occurs. Therefore, by setting the recess d1 to 0.2 μm or less, that is, to about 1/3 or less of the diameter of the upper layer and lower layer plugs, it is possible to form a good multilayer wiring structure in which stress migration failure hardly occurs.

Although the case where the contact buried metal 3 and the through-hole buried metal 6 are formed using the etch-back method by dry etching has been described, when the etch-back method is used, residues tend to remain. Overetching tends to increase and the recess d1 tends to increase. In contrast, CMP (Chemical Mechanical
When the contact buried metal 3 and the through-hole buried metal 6 are formed by using the (Polishing) method, the dimensions of the recess d1 can be controlled with high precision. Therefore, the multilayer wiring structure of the semiconductor device according to the present embodiment can be reliably formed.

(Third Embodiment) FIG. 9 is a view showing a method for manufacturing a multilayer wiring structure of a semiconductor device according to a third embodiment of the present invention, and is a cross-sectional view of the structure in each step. As shown in FIG. 9A, a contact opening 2a as a first opening is formed in the first insulating film 2 on the semiconductor substrate 1, and as shown in FIG. , Ti and TiN
A W film 3b is formed on the two-layer film 3a. As shown in FIG. 9C, a two-layer film 3 of Ti and TiN on the first insulating film 2 is formed.
The a and W films 3b are etched to leave the two-layer film 3a of Ti and TiN and the W film 3b only in the contact opening 2a, thereby forming the contact buried metal 3. A two-layered film 4a of Ti and TiN is formed thereon, an Al alloy 4b containing Cu is formed on the two-layered film 4a, and a TiN film 4c is formed thereon. The wiring 4 is formed.

The Al alloy 4b is formed by sputtering, and the deposition temperature at this time is set to 200 ° C. or higher. 20
By depositing the Al alloy 4b at a temperature equal to or higher than 0 ° C., a crystal grain boundary hardly occurs on the contact opening 2a. The Al alloy 4b is formed so as to fill the depression on the contact opening 2a, and the thickness of the portion on the contact opening 2a is larger than that of the other portions.

As shown in FIG. 9D, a second insulating film 5 is formed on the first wiring 4, and a through-hole opening 5a as a second opening is formed in the second insulating film 5. The W film 6b is formed on the two-layer film 6a of Ti and TiN. At this time, the through-hole opening 5 a is formed to have a height equal to or larger than the height difference between the upper surface of the first insulating film 2 and the upper surface of the contact embedded metal 3.
Not deeply into the wiring 4. By forming the through-hole opening 5a in this manner, the thickness of the first wiring 4 on the contact embedding metal 3 is equal to or greater than the thickness of other portions.

Next, as shown in FIG. 9E, the two-layer film 6a of Ti and TiN and the W film 6b on the second insulating film 5 are etched, and Ti and Ti are formed only in the through-hole opening 5a. The two-layer film 6a and the W film 6b of TiN are left, and thereby the through-hole buried metal 6 is formed. On top of that, T
forming a two-layer film 7a of i and TiN, forming an Al alloy 7b containing Cu on the two-layer film 7a, further forming a TiN film 7c thereon, and forming a second wiring 7; I do.
As shown in FIG. 9F, a silicon nitride film 8 is formed as a protective film by plasma CVD.

In the multilayer wiring structure of the semiconductor device manufactured as described above, the thickness of the Al alloy 4b of the first wiring 4 on the contact embedding metal 3 is equal to or greater than the thickness of other portions. Then, as in the second embodiment, the region of the first wiring 4 on the contact buried metal 3, that is,
Al alloy 4b in the region between the upper and lower plugs opposed to each other had almost no crystal grain boundaries, and the size of the crystal grains in this region was almost the same as the other regions. . For this reason, in the structure according to the present embodiment, similarly to the second embodiment, no increase in wiring resistance due to stress migration failure after high-temperature storage was observed.

FIG. 10 shows the deposition temperature during sputtering and
FIG. 9 is a diagram showing a relationship between the thickness of a first wiring 4 in a region sandwiched between opposed upper and lower plugs. FIG. 10A is a diagram showing a cross-sectional structure of a sample used in an experiment for obtaining this relationship. 0.7μ on semiconductor substrate 1
A contact opening having a diameter of 0.6 μm is formed in the first insulating film 2 having a thickness of m, and Ti and TiN are formed in the contact opening.
Is formed on the two-layer film of FIG. The distance between the lower surface of the first wiring 4 and the upper surface of the contact burying metal 3 is 0.2 μm. Then, a 50 nm thick Ti film and a Cu-containing 600
An Al alloy having a thickness of 30 nm and a TiN film having a thickness of 30 nm are formed. In this experiment, a sample was manufactured by changing the deposition temperature of the Al alloy, and the cross section thereof was observed by SEM to measure the depth d2 of the depression 4I of the first wiring 4 on the contact embedded metal 3.

FIG. 10B is a graph showing the results of this experiment. In order for the Al alloy of the first wiring 4 to be formed as thick as or more than the other region in the region above the contact opening, the depth d2 needs to be 0.2 μm or less. In this way, by setting the depth d2 of the depression 4I to 0.2 μm or less, it is possible to reduce a large stress caused by the upper plug entering the wiring layer as shown in the stress simulation of FIG. Can be. Therefore, by setting the depth d2 to 0.2 μm or less, that is, to about 1/3 or less of the diameter of the upper and lower plugs, it is possible to form a favorable multilayer wiring structure in which stress migration failure hardly occurs. FIG.
As can be seen from (b), the depth d2 becomes 0.2 μm or less when the deposition temperature of the Al alloy is 200 ° C. or more. Therefore, it can be said that the deposition temperature of the Al alloy is preferably 200 ° C. or higher so that the wiring does not have a crystal grain boundary in a region sandwiched between the upper and lower plugs facing each other.

(Fourth Embodiment) FIG. 11 shows a fourth embodiment of the present invention.
FIG. 8 is a view illustrating the method for manufacturing the multilayer wiring structure of the semiconductor device according to the embodiment, and is a cross-sectional view of the structure in each step.
As shown in FIG. 11A, a contact opening 2a as a first opening is formed in a first insulating film 2 on a semiconductor substrate 1. Then, as shown in FIG. 11B, a Ti film 4d is formed, and an aluminum film is deposited thereon to a thickness of 100 nm by a CVD method at a deposition temperature of 260 ° C. using dimethylaluminum hydride as a source gas, followed by sputtering. An Al alloy containing Cu is deposited at a deposition temperature of 400 ° C. to a thickness of 500 nm to form a layer 4 e of CVD aluminum and an Al alloy. Furthermore, TiN
The film 4f is formed. The first wiring 4 is provided by processing the Ti film 4d, the CVD aluminum and Al alloy layer 4e, and the TiN film 4f into a wiring shape. Since the aluminum film is formed by the CVD method, aluminum is buried in the contact opening 2a, so that the first wiring 4 on the contact opening 2a is sufficiently thicker than other portions.

As shown in FIG. 11C, the first wiring 4
The second insulating film 5 is formed thereon, and the second insulating film 5 is provided with a through-hole opening 5a as a second opening. FIG.
As shown in FIG. 1D, a layer 7e of CVD aluminum and an Al alloy is formed on the Ti film 7d, and a TiN film 7 is formed thereon.
f is formed and processed into a wiring shape to form the second wiring 7. Next, as shown in FIG.
D forms a silicon nitride film 8 as a protective film.

In the multilayer wiring structure of the semiconductor device manufactured as described above, the first wiring 4, the contact burying metal 3 and the through-hole burying metal 6 are both formed of the same Al alloy. That is, the wiring and the upper and lower plugs opposed to each other with the wiring therebetween are formed of the same material. For this reason, the stress applied to the region sandwiched between the upper layer plug and the lower layer plug is much smaller than a structure in which the upper layer plug and the lower layer plug are formed of a metal (for example, W) different from the wiring. Therefore, in the structure according to the present embodiment, no increase in wiring resistance due to stress migration failure after high-temperature storage was observed.

In this embodiment, the Al alloy is buried in the contact opening 2a and the through-hole opening 5a by CVD and sputtering. However, the embedding may be performed only by CVD. After the Al alloy is formed by sputtering, the embedding may be performed by flowing the Al alloy by heating or pressing.

Even when the material of the upper plug and the lower plug is different from that of the wiring, if the difference in the coefficient of thermal expansion between the materials is small enough not to cause voids due to high-temperature storage, the stress is reduced. No migration failure occurs. For example, the thermal expansion coefficient of Al is 23.8 × 10
⁻⁶ / K, whereas the thermal expansion coefficient of W is 4.3 × 10
⁻⁶ / K, and the difference is large, so that stress migration failure occurs in the W plug. However, Ni (thermal expansion coefficient 13.1 × 10 ⁻⁶ / K) and Cu (thermal expansion coefficient 16.8 ×)
By using 10 ⁻⁶ / K) or the like as a plug material, stress migration failure does not occur.

Further, the difference between the thermal expansion coefficient of the material and the one of the upper layer side plug and the lower layer side plug may be so small that voids are not generated by high-temperature storage. For example, when forming a multilayer wiring structure in which the lower wiring is made of an Al alloy and the upper wiring is made of Cu, if a plug between wiring layers is formed of W, stress migration occurs due to a difference in thermal expansion coefficient in the Al wiring.
By replacing this plug material with Ni or Cu, A
Stress migration failure of the l wiring can be prevented.

(Fifth Embodiment) FIG. 12 shows a fifth embodiment of the present invention.
FIG. 11 is an enlarged view of a region of a first wiring 4 sandwiched between a contact burying metal 3 and a through-hole burying metal 6 in the multilayer wiring structure of the semiconductor device according to the third embodiment. In the multilayer wiring structure shown in FIG. 12, the first wiring 4 is formed by laminating a Ti film 4a, an Al alloy 4b to which Cu is added, and a TiN film 4c as a film of a high melting point metal or a high melting point metal alloy. It is in contact with a through-hole buried metal 6 as a side plug via a TiN film 4c.

The multilayer wiring structure shown in FIG. 12 is manufactured basically in the same manner as the method according to the third embodiment shown in FIG. However, when the through-hole opening 5a is formed in the second insulating film 5 by dry etching or the like,
The TiN film 4c of the first wiring 4 is left without being removed.

According to the multilayer wiring structure of the semiconductor device according to the present embodiment, the first wiring 4 and the through-hole buried metal 6
Are in contact with each other via the TiN film 4c.
The N film 4c alleviates the stress caused by the through-hole buried metal 6. Therefore, generation of voids can be suppressed, and an increase in resistance due to stress migration can be prevented.

(Sixth Embodiment) In the sample of FIG. 1A, a Ti film as a refractory metal film is formed below the first wiring 4 instead of a two-layer film of Ti and TiN. By changing the thickness of the Ti film in the range of 0 to 120 nm,
Each defective rate was measured. FIG. 13 is a graph showing the relationship between the thickness of the Ti film and the defect rate obtained by such measurement. Here, each sample was placed at 250 ° C. for 1 hour.
The sample was stored for 68 hours, and a sample whose resistance variation exceeded 20% was determined to be defective, and the defect rate was determined.

As can be seen from FIG. 13, when the thickness of the Ti film is 50 nm, the defect rate is maximized, and
And the defect rate becomes 0 at 100 nm or more. T
The reason why the relationship between the thickness of the i-film and the defect rate becomes as shown in FIG. 13 is considered as follows. The stress applied to the first wiring 4 is relieved by the Ti film, and the greater the film thickness, the greater the effect of the stress relieving. On the other hand, if there is a Ti film, Si in the aluminum alloy is sucked out by the Ti film 4a, so that vacancies are easily generated in the aluminum alloy. Therefore,
It is considered that the relationship between the thickness of the Ti film and the defect rate is as shown in FIG. 13 due to the balance between the effect of stress relaxation and the tendency to form voids in the aluminum alloy.

Therefore, the thickness of the Ti film is 10 nm.
By excluding the range of ８０80 nm, ie,
By setting the thickness of the Ti film to 10 nm or less or 80 nm or more, it is possible to form a good multilayer wiring structure in which stress migration failure does not easily occur.

In each of the embodiments, a description has been given of a two-layer wiring structure as an example. However, the present invention can be similarly realized in a multilayer wiring structure having three or more layers.

Further, each embodiment may be implemented by combining any of them. For example, by combining the first embodiment and the second embodiment, the distance between the center of the contact surface between the upper-layer plug and the wiring and the center of the contact surface between the lower-layer plug and the wiring is higher than the upper layer. The height of the protrusion formed on the lower surface of the wiring layer and in contact with the lower-layer plug is set to approximately 2/3 or more of the diameter of the lower-layer plug, and approximately 1/1 / the diameter of the upper-layer and lower-layer plugs. A multilayer wiring structure set to three or less may be configured. Similarly, the second embodiment and the third embodiment may be combined, or the first to third embodiments may be combined.

[0063]

As described above, according to the present invention, it is possible to suppress a decrease in wiring reliability due to a stress in a region sandwiched between an upper-layer plug and a lower-layer plug. The rise can be suppressed.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a structure of a sample for electrically detecting the influence of a stack structure in a multilayer wiring structure of a semiconductor device, wherein FIG. 1A is a cross-sectional view of the sample, and FIG. It is a perspective view of a part of sample.

FIG. 2 is a characteristic diagram showing a problem to be solved by the present invention;
3 is a graph showing the relationship between the high-temperature storage time of the sample shown in FIG. 1 and the defect rate, and FIG. 4B is a graph showing the relationship between the wiring width of the sample shown in FIG.

FIG. 3 is a characteristic diagram showing the problem to be solved by the present invention, and is a graph showing a relationship between the storage temperature of the sample shown in FIG. 1 and the cumulative failure arrival time.

FIG. 4 is a characteristic diagram illustrating a problem to be solved by the present invention, and is a diagram illustrating a relationship between a wiring structure and a non-defective rate.

FIG. 5 is a cross-sectional view showing the result of observing the wiring structure shown in FIG. 1 which became defective after storage at a high temperature using a transmission electron microscope.

6 (a) and 6 (b) are diagrams showing the results of simulating the internal stress generated when the temperature changes in the wiring structure of FIG. 5 by the finite element method.

FIG. 7 is a diagram for explaining the first embodiment of the present invention, and is a graph showing the relationship between the degree of overlap between the upper plug and the lower plug and the yield rate.

FIG. 8A is a cross-sectional view illustrating a multilayer wiring structure of a semiconductor device according to a second embodiment of the present invention, and FIG.
6 is a graph showing the relationship between the defect rate and the defect rate.

FIGS. 9A to 9F are process cross-sectional views illustrating a method for manufacturing a multilayer wiring structure of a semiconductor device according to a third embodiment of the present invention.

FIGS. 10A and 10B are diagrams for explaining an experiment according to a third embodiment of the present invention, wherein FIG. 10A is a diagram showing a cross-sectional structure of a sample used in the experiment, and FIG. 9 is a graph showing a relationship between a wiring recess on a lower plug and a depth d2.

FIGS. 11A to 11E are process cross-sectional views illustrating a method for manufacturing a multilayer wiring structure of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 12 is a sectional view showing a multilayer wiring structure of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 13 is a diagram for explaining the sixth embodiment of the present invention, and is a graph showing the relationship between the thickness of the wiring lower Ti film and the defect rate.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 first insulating film 2a contact opening (first opening) 3 contact buried metal (lower plug) 4 first wiring (wiring formed in one wiring layer) 4a Ti film (high 4c TiN film (high-melting-point metal or high-melting-point metal alloy film) 4H protrusion 4I depression 5 second insulating film 5a through-hole opening (second opening) 6 through-hole buried metal (upper layer) Side plug) 7 Second wiring (upper wiring) 40 Void 45 Crystal grain boundary

Continuation of the front page (72) Inventor Kosaku Yano 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation

Claims (12)

[Claims] An electrical connection between a substrate, two or more wiring layers formed on the substrate, a wiring formed on one of the two or more wiring layers, and an upper layer wiring. An upper-layer plug that is connected to the upper-layer plug and a lower-layer plug that is provided opposite to the upper-layer plug with the wiring interposed therebetween and electrically connects the wiring to the lower-layer wiring or the substrate; When viewed from the perpendicular direction, the distance between the center of the contact surface between the upper-layer plug and the wiring and the center of the contact surface between the lower-layer plug and the wiring is equal to the distance between the upper-layer plug and the lower-layer plug. A multilayer wiring structure of a semiconductor device in which the diameter is set to approximately 2/3 or more. 2. An electrical circuit comprising: a substrate; two or more wiring layers formed on the substrate; and a wiring formed on one of the two or more wiring layers and an upper wiring. An upper-layer plug connected to the lower-layer plug, the lower-layer plug being provided opposite to the upper-layer plug with the wiring interposed therebetween, and electrically connecting the wiring to a lower-layer wiring or the substrate; A lower part of the wiring layer is formed with a protruding portion protruding from the lower layer side and in contact with the lower layer side plug. The height of the protruding part protruding from the lower surface of the one wiring layer is set to the upper layer side and the lower layer. A multilayer wiring structure of a semiconductor device in which a diameter of a side plug is set to approximately 1/3 or less. 3. An electrical connection between a substrate, two or more wiring layers formed on the substrate, and a wiring formed on one of the two or more wiring layers and an upper wiring. An upper-layer plug connected to the upper-layer plug and a lower-layer plug provided opposite to the upper-layer plug with the wiring interposed therebetween and electrically connecting the wiring to the lower-layer wiring or the substrate; Is a multilayer wiring structure of a semiconductor device which is configured so as not to have a crystal grain boundary in a region sandwiched between the opposed upper and lower plugs. 4. A substrate, two or more wiring layers formed on the substrate, and a wiring formed on one of the two or more wiring layers and an upper layer wiring are electrically connected to each other. An upper-layer plug to be connected, and a lower-layer plug provided opposite to the upper-layer plug with the wiring interposed therebetween and electrically connecting the wiring to a lower-layer wiring or the substrate, wherein the one wiring A depression is formed on the upper surface of the layer, the depression being in contact with the upper-layer plug, and the depth of the depression from the upper surface of the one wiring layer is approximately 1 mm of the diameter of the upper-layer and lower-layer plugs. A multilayer wiring structure of a semiconductor device set to be equal to or less than / 3. 5. An electrical connection between a substrate, two or more wiring layers formed on the substrate, a wiring formed on one of the two or more wiring layers, and an upper layer wiring. An upper-layer plug connected to the upper-layer plug and a lower-layer plug provided opposite to the upper-layer plug with the wiring interposed therebetween and electrically connecting the wiring to the lower-layer wiring or the substrate; And the difference in thermal expansion coefficient of the material between at least one of the upper layer side plug and the lower layer side plug is reduced to such an extent that voids do not occur in a region between the upper layer side and the lower layer side plug of the wiring. A multilayer wiring structure for a semiconductor device, comprising: 6. The semiconductor device according to claim 5, wherein the wiring and at least one of the upper and lower plugs are formed of the same material. The multilayer wiring structure of the device. 7. The multilayer wiring structure of a semiconductor device according to claim 6, wherein said wiring and at least one of said upper and lower plugs are made of aluminum or an aluminum alloy, or aluminum. Alternatively, a multilayer wiring structure for a semiconductor device, comprising a laminated structure of an aluminum alloy and a high melting point metal, a high melting point metal alloy or a composite layer thereof. 8. A substrate, two or more wiring layers formed on the substrate, and a wiring formed on one of the two or more wiring layers and an upper wiring are electrically connected to each other. An upper-layer plug connected to the lower-layer plug, the lower-layer plug being provided opposite to the upper-layer plug with the wiring interposed therebetween, and electrically connecting the wiring to a lower-layer wiring or the substrate; In the wiring layer, a film of a high melting point metal or a high melting point metal alloy is formed on the upper surface side, and the wiring and the upper layer side plug are interposed through the film of the high melting point metal or the high melting point metal alloy. The multilayer wiring structure of the semiconductor device in contact. 9. An electrical connection between a substrate, two or more wiring layers formed on the substrate, and a wiring formed on one of the two or more wiring layers and an upper wiring. An upper-layer plug connected to the lower-layer plug, the lower-layer plug being provided opposite to the upper-layer plug with the wiring interposed therebetween, and electrically connecting the wiring to a lower-layer wiring or the substrate; A high melting point metal film is formed on the lower surface side of the wiring layer, and the thickness of the high melting point metal film is set to 10 nm or less or 80 nm or more. . 10. A step of forming a first opening in a first insulating film formed on a substrate, and forming a lower plug on the first opening; and forming the first insulating film and the lower layer. Forming a wiring on the side plug; forming a second insulating film on the wiring; forming a second opening in the second insulating film facing the first opening; Forming an upper-layer plug in the second opening; and forming the lower-layer plug in the upper-layer plug and the first insulating film using a CMP method or an etch-back method. A method of manufacturing a multilayer wiring structure of a semiconductor device, wherein a distance from an upper surface is set to be approximately 1/3 or less of diameters of the upper and lower plugs. 11. A step of forming a first opening in a first insulating film formed on a substrate, and forming a lower plug in the first opening; and forming the first insulating film and the lower layer. Forming a wiring having at least a layer made of aluminum or an aluminum alloy on the side plug; forming a second insulating film on the wiring; forming a second insulating film on the second insulating film in the first opening; Forming an opposing second opening, and forming an upper-layer plug in the second opening, wherein the wiring is formed between the upper-layer and lower-layer plugs facing each other. The aluminum or aluminum alloy layer of the wiring is formed by sputtering at about 200 ° C. so as not to have a crystal grain boundary in the sandwiched region.
A method for manufacturing a multilayer wiring structure of a semiconductor device formed at the above deposition temperature. 12. A step of forming a first opening in a first insulating film formed on a substrate; forming a lower-layer plug in the first opening;
Forming a wiring on the first insulating film; forming a second insulating film on the wiring; and forming a second opening in the second insulating film opposite the first opening. Forming an upper-layer plug in the second opening. The lower-layer plug and the wiring forming step are performed by CVD or sputtering and aluminum or aluminum alloy. The first
Forming a lower-layer plug and a wiring in the opening of the semiconductor device and on the first insulating film to form a multilayer wiring structure of the semiconductor device.