JPH11237433A - Apparatus and method for testing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a circuit from being complex in constitution, miniaturize the circuit and reduce costs. SOLUTION: When a test board to be used is designated from test boards TB1, TB2,..., TBn where devices DUT,... to be measured are mounted, a DUT switch circuit 43 switches to supply a power from a DUT power source circuit 41 to only the test board TB1, TB2,..., TBn to be used. A driver comparator switch circuit 44 switches thereby inputting a test pattern from a driver comparator control circuit 41 to only the test board TB1, TB2,..., TBn to be used. The test pattern is processed by the device DUT,... to be measured, and the result of the processing is judged, whereby a characteristic of the device to be measured is judged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a device test apparatus for testing a semiconductor device, and more particularly, to a method for supplying power to a device under test to be tested.

[0002]

2. Description of the Related Art In recent years, the use of ICs (Integrated Circuits) in circuits used in various electronic devices has been rapidly advanced. IC, LSI (Large Scale Integrated)
circuit) and the like tend to cause some variation in characteristics during mass production, so a semiconductor device test apparatus for testing these semiconductor devices has been used.

In such a semiconductor device test apparatus, it is required to perform a test more easily and in a shorter time. That is, if much time and effort are required to test the characteristics, the number of manufacturing steps of the semiconductor device increases, and the manufacturing cost increases. For this reason, a semiconductor device test apparatus capable of simultaneously testing a large number of semiconductor devices has been used.

FIG. 2 is a block diagram showing a configuration of a semiconductor device test apparatus 100 as an example of a conventional semiconductor device test apparatus. This semiconductor device test apparatus 10
Numeral 0 is constituted by the constant temperature bath 2 and the control unit 7.
, A control device 71, a pattern generator 72, and a plurality of board control units 131, 132,..., 13n. Furthermore, the board control unit 131
T power supply circuit 111, driver / comparator control circuit 121, driver / comparator circuit 31aa,.
1zz internally, and the board control units 132, 1
, 13n are DUT power supply circuits 112, 11
3,..., 11n, driver / comparator control circuit 12
, 12n and driver / comparator circuits 32aa, 32bb,..., 3naa,.

[0005] In the thermostat 2, a board control unit 131, 1 is provided.
32,..., 13n as many test boards TB1, TB
, TBn are provided, and board control units 131 and 13 are provided.
, 13n and test boards TB1, TB2,.
Bn are connected one-to-one. The test boards TB1, TB2,..., TBn can be mounted with a large number of devices under test DUT,.

According to the semiconductor device test apparatus 100, the device under test DU is controlled by the control device 71 in accordance with an instruction input by an input device (not shown).
When a program for testing T,... Is executed, first, a test pattern is generated by the pattern generator 72, and the test pattern is generated by the driver / comparator control circuits 121, 122,.
, 13n are output to the devices under test DUT,... Via the comparator circuits 131, 132,. On the other hand, the test boards TB1, TB2, connected to the DUT power supply circuits 111, 112,.
, ..., power is supplied to TBn.

Then, processing is executed by the devices under test DUT,... Based on the test pattern, and the processing results are sent from the test boards TB1, TB2,..., TBn to the driver / comparator control circuits 121,. Is entered. The driver / comparator control circuits 121,..., 12n determine these processing results to determine the characteristics of the device under test.

The constant temperature bath 2 is provided with a temperature control means such as a heater (not shown). By changing the temperature in the constant temperature bath 2 by the temperature control means, the device to be measured under various temperature conditions can be controlled. , Are tested.

[0009]

However, in the conventional semiconductor device test apparatus 100, the same number of DUs are provided corresponding to the test boards TB1, TB2,..., TBn.
, 11n and a driver
And a comparator control circuit.
However, there is a problem that the size and complexity of the device are increased and the cost is increased.

[0010] The present invention has been made in order to solve the above problems.
It is an object of the present invention to provide a semiconductor device test apparatus and a semiconductor device test method capable of reducing the cost by simplifying the circuit configuration and reducing the size.

[0011]

According to an aspect of the present invention, a test signal is generated, and a device under test is caused to execute processing based on the test signal. In a semiconductor device test apparatus for testing a device, a plurality of device mounting units for mounting the device under test, a power supply unit for supplying power to the plurality of device mounting units, and a plurality of device mounting units The unit includes a power supply switching unit for switching a connection state between each device mounting unit and the power supply unit.

According to the first aspect of the present invention, there is provided a semiconductor device test apparatus for generating a test signal, causing the device under test to execute processing based on the test signal, and testing the device under test. , To multiple device mounting parts,
The device under test is mounted, power is supplied to the plurality of device mounting units by the power supply unit, and the connection state between the device mounting unit and the power supply unit is switched for the plurality of device mounting units by the power switching unit. .

According to a third aspect of the present invention, there is provided a semiconductor device test apparatus for generating a test signal, causing the device under test to execute processing based on the test signal, and testing the device under test. The method is characterized in that the device under test is mounted on a plurality of device mounting sections, and it is possible to switch whether or not to supply power to each of the plurality of device mounting sections.

According to the third aspect of the present invention, there is provided a semiconductor device test apparatus which generates a test signal, causes the device under test to execute processing based on the test signal, and tests the device under test. A semiconductor device testing method, wherein a device under test is mounted on a plurality of device mounting portions, and for each of the plurality of device mounting portions,
Switches whether to supply power.

Therefore, whether or not to supply power to each device mounting portion can be switched by the power supply switching means. Therefore, it is not necessary to provide a power supply portion for each device mounting portion, and the power supply is not required. Since only one unit needs to be installed, it is possible to avoid complication of the circuit, to reduce the size of the device and to reduce the cost.

According to a second aspect of the present invention, in the semiconductor device test apparatus of the first aspect, a test signal switching means for switching whether or not a test signal is input to each of the plurality of device mounting sections is further provided. Preparing,
.

According to the second aspect of the present invention, the test signal switching means switches whether to input a test signal to each of the plurality of device mounting sections.

According to a fourth aspect of the present invention, in the semiconductor device testing method according to the third aspect, it is possible to switch whether or not to input the test signal for each of the plurality of device mounting sections. It is characterized.

According to the fourth aspect of the present invention, it is possible to switch whether or not to input a test signal for each of the plurality of device mounting sections.

Therefore, it is not necessary to provide a circuit for controlling the input of the test signal to the device mounting section for each device mounting section. As a result, the size and cost of the apparatus can be further reduced.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 1, a semiconductor device test apparatus 1 includes a constant temperature bath 2 and a control unit 3. The control unit 3 includes a control device 51, a pattern generator 52,
Power supply / control unit 4 and driver / comparator units 61 and 6
, 6n. Further, the control unit 3
It is connected to an input device (not shown).

In the thermostat 2, a plurality of test boards TB
, TBn,..., TBn and a heater (not shown), and a large number of devices under test DUT,... Can be mounted on the test boards TB1, TB2,.

The thermostat 2, test boards TB1, T
, TBn, the device under test DUT,..., And the driver comparators 31aa, 31bb,.
Since it is the same as (FIG. 2), the same reference numerals are given and the description is omitted.

The control device 51 executes various test programs stored therein in accordance with an instruction input from an input device (not shown), outputs a control signal to the pattern generator 52, and outputs a control signal to the device under test DUT, A test pattern for the test of... Is generated.

Then, all the test boards TB1, TB
Test boards TB1, T used from among 2, 3, TBn
, TBn, and the driver / comparator units 61, 62,..., 6n corresponding to the test boards TB1, TB2,. The circuit 42 outputs the test pattern generated by the pattern generator 52 to the driver / comparator units 61, 62,..., 6n to be used.

On the other hand, the test boards TB1, TB2,
, TBn are switched, and power is supplied from the DUT power supply circuit 41 only to the test board to be used.

The pattern generator 52 receives a test board TB based on an instruction input from the control device 51.
, TB2,..., TBn, test patterns for testing the devices under test DUT,.

The power supply / control section 4 includes a DUT power supply circuit 41, a driver / comparator control circuit 42, a DUT
Switching circuit 43 and driver / comparator switching circuit 4
4 is provided.

The DUT power supply circuit 41 includes test boards TB1 and TB connected via a DUT switching circuit 43.
2, a power supply unit for supplying power to TBn,
The DUT switching circuit 43 is connected to the connected test board TB.
, TB2,..., TBn, each test board TB
1, TB2,..., TBn are switched as to whether or not to supply power.

The driver / comparator control circuit 42
The test patterns generated by the pattern generator 52 are output to the test boards TB1, TB2,..., TBn via the driver / comparator switching circuit 44, and are installed on the test boards TB1, TB2,. The processing is performed by the measured devices DUT,..., And when the obtained processing results are input, the processing results are discriminated to determine the measured devices DUT,.
Is determined.

The driver / comparator switching circuit 44
The test pattern input via the driver / comparator control circuit 42 is stored in the driver / comparator units 61 and 6.
2, ..., 6n, and the test board TB
, TB2,..., TBn, the processing results input from the devices under test DUT,.

The driver / comparator unit 61 includes driver / comparator units 31aa, 31bb,.
Similarly, the driver / comparator units 62,..., 6n internally include the driver / comparator 32
aa,..., 3nzz. , 6n are connected to the test boards TB1, TB2,..., TBn in a one-to-one correspondence, and test the test pattern input from the driver / comparator switching circuit 44. Board TB1, TB
, TBn, and test board TB1,
, TBn, the processing results obtained by the processing by the devices under test DUT,.
Output to

When the test boards TB1, TB2,..., TBn and the devices under test DUT,..., And various settings are set by an input device (not shown), and an instruction to start the test is input, the control device 51 is started. , A program for executing a test of the devices under test DUT,... Is generated by the pattern generator 52, and the designated test boards TB1, TB2,. The power is selected by the circuit 43 and supplied.

On the other hand, the test pattern generated by the pattern generator 52 is transmitted through the driver / comparator control circuit 42, and the driver / comparator switching circuit 44 and the driver / comparator units 61, 62,.
6n, test boards TB1, TB2,
.., TBn.

Thereafter, based on the test pattern generated by the pattern generator 52, the test board TB
, TB2,..., TBn, the processing is executed, and the processing results are output to the driver / comparator units 61, 62,. Driver / comparator units 61, 62, ..., 6
n extracts the processing results input from the test boards TB1, TB2,..., TBn for each device under test DUT,... and outputs the extracted processing results to the driver / comparator switching circuit 44. The characteristics of the devices under test DUT,... Are determined based on the processing results.

As described above, according to the semiconductor device test apparatus 1 as an embodiment of the present invention, the test boards TB1, TB2, on which the devices under test DUT,.
.., TBn are supplied by the DUT power supply circuit 41 and the DUT switching circuit 43, so that it is not necessary to provide a large number of circuits for supplying power, thereby preventing the entire semiconductor device test apparatus 1 from being enlarged. At the same time, cost can be reduced. Further, by providing the driver / comparator switching circuit 44, the test board TB
, TBn,..., And TBn, and the processing results of the devices under test DUT,..., Can be discriminated, and further downsizing and cost reduction can be realized. .

In the above embodiment, a plurality of test boards TB1, TB2,.
The test is performed by mounting the devices under test DUT on TBn. However, the present invention is not limited to this. For example, the devices under test DUT,
.. May be mounted, the board may be divided into a plurality of blocks, and power may be supplied to each block, or power may be independently supplied to a plurality of devices under test DUT,. It is good also as a structure which performs. Others
The configuration of the details can be appropriately changed without departing from the gist of the present invention.

[0039]

According to the first and third aspects of the present invention, whether or not to supply power to each device mounting portion can be switched by the power supply switching means. On the other hand, it is not necessary to provide a power supply unit, and only one power supply unit needs to be provided. Therefore, it is possible to avoid a complicated circuit, to reduce the size of the device and to reduce the cost.

According to the second and fourth aspects of the present invention, the circuit for controlling the input of the test signal to the device mounting section is
It is not necessary to provide each device mounting section.
As a result, the size and cost of the apparatus can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor device test apparatus as an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a conventional semiconductor device test apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor device test apparatus 2 Temperature chamber 3 Control part 4 Power supply / control part 41 DUT power supply circuit 42 Driver / comparator control circuit 43 DUT switching circuit 44 Driver / comparator switching circuit 51 Control device 52 Pattern generator 61, 62, ... , 6n driver / comparator unit 31aa, 31bb,..., 3nzz driver / comparator TB1, TB2,..., TBn test board DUT,.

Claims (4)

[Claims] 1. A semiconductor device test apparatus for generating a test signal, causing a device under test to execute processing based on the test signal, and testing the device under test, for mounting the device under test. A plurality of device mounting units; a power supply unit for supplying power to the plurality of device mounting units; and a connection state between each device mounting unit and the power supply unit for the plurality of device mounting units. And a power supply switching unit. 2. The semiconductor device test apparatus according to claim 1, further comprising a test signal switching unit for switching whether or not to input the test signal for each of the plurality of device mounting units. . 3. A semiconductor device test method in a semiconductor device test apparatus for generating a test signal, causing a device under test to execute processing based on the test signal, and testing the device under test. A semiconductor device test method, wherein the device under test is mounted on the device mounting portion, and it is possible to switch whether to supply power to each of the plurality of device mounting portions. 4. The semiconductor device test method according to claim 3, wherein it is possible to switch whether or not to input said test signal for each of said plurality of device mounting sections.