JPH11232316A - Pseudo-line fault generating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to easily have a line fault generated, to say nothing of enabling operation of an evaluation test that assumes a timing equal to that of a real machine. SOLUTION: A mechanism control device 21, a temperature control device 22, a pressure control device 23, a gas flow rate control device 24 and an operation part 25 are connected to a main control part 26 by way of SECS lines 27(1) to 27(5) respectively. The SECS lines 27(1) to 27(5) have line fault simulators 28(1) to 28(5) inserted respectively. The line fault simulators 28(1) to 28(5) have a function to hold line fault generation data in order to have a line fault specified by an operator generated, a function to simulatedly have the line fault generated in the SECS lines 27(1) to 27(5) on the basis of the held line fault generation data, and a function to record every time it has the line fault generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo line fault generating apparatus (hereinafter referred to as a pseudo line fault generating apparatus) for generating a line fault in a communication line connecting a plurality of modules in a solid state manufacturing system constituted by combining a plurality of modules. "Line failure simulator").

[0002]

2. Description of the Related Art In general, a solid-state manufacturing system such as a solid-state manufacturing line or a solid-state manufacturing apparatus for manufacturing a solid-state device such as a semiconductor device or a liquid crystal display device is configured by combining a plurality of modules.

For example, solid-state production lines such as a semiconductor production line for producing a semiconductor device and a liquid crystal production line for producing a liquid crystal display device are intended for solid-state production such as an oxidation device, a film formation device, and an ion implantation device. It is configured by combining various solid-state manufacturing devices. Also,
A solid-state manufacturing device such as a semiconductor manufacturing device for manufacturing a semiconductor device and a liquid crystal manufacturing device for manufacturing a liquid crystal display device is obtained by combining various control devices such as a mechanism control device (mechanical control device) and a temperature control device. It is configured.

In the solid-state manufacturing system as described above, a plurality of modules are usually connected via a communication line. In this case, the communication line is usually SEM
A communication line conforming to the SECS protocol defined in I (hereinafter referred to as “SECS line”) is used.

FIG. 16 is a block diagram showing an example of the configuration of a solid-state manufacturing apparatus in which a plurality of modules are connected by an SECS line.

The illustrated solid manufacturing apparatus includes a mechanical control device 11.
, A temperature control device 12, a pressure control device 13, a gas flow control device 14, an operation unit 15, and a main control unit 16. The mechanical control device 11, the temperature control device 12, the pressure control device 13, the gas flow control device 14, and the operation unit 15 are connected to the main control unit 16 via SECS lines 17 (1) to 17 (5), respectively.

In such a solid-state manufacturing system in which a plurality of modules are connected by an SECS line, the SECS is affected by a shift in the mutual communication timing between the transmitting side and the receiving side and external factors such as electromagnetic noise. A line failure may occur on the line. When this line failure occurs, the communication program may malfunction, which may lead to malfunction in solid-state manufacturing. Therefore, in this solid-state manufacturing system, during the manufacturing process, the operation of the communication program for the line failure is evaluated, and based on the evaluation result,
It is necessary to take measures to prevent malfunction.

As a method of evaluating the operation of a communication program for a line failure, there is a method of confirming the operation of the communication program after an actual line failure has occurred. However, in a normal operation, the probability that a line failure will occur is extremely low. Therefore, this method is not suitable in terms of efficiency and labor.

For this reason, conventionally, the operation of a communication program for a line fault has been positively evaluated by performing an operation evaluation test. In this case, the following three methods have conventionally been used as methods for performing the operation evaluation test.

(1) A method for testing by confirming the validity of a program logic in a module unit test. (2) A method for conducting a test by confirming the validity of an interface between modules in a module connection test. (3) A system. Testing method by checking the validity of system operation using a circuit simulator

[0011]

However, in the test methods (1) and (2) described above, since the operation is confirmed at the simulation level, it is possible to perform a test assuming the same timing as that of the actual device. There was a problem that it was difficult. Thus, this test method has a problem that it is difficult to evaluate the actual operation of the communication program when a line failure occurs.

On the other hand, in the test method (3) described above, since the validity of the system operation is confirmed in the system test, it is possible to perform the operation evaluation test assuming the same timing as the actual machine. It is. However, in this test method, since a line failure such as data abnormality, message collision, message delay, and the like must be generated in the line simulator, the existing line simulator must be significantly changed (for example, for a line simulator). You have to make major changes to the program). Thus, this test method has a problem that it is difficult to artificially cause a line failure.

The present invention has been made in order to cope with the above situation, and it is possible to perform an operation evaluation test assuming the same timing as that of an actual device, and also to easily generate a line failure. It is an object of the present invention to provide a line fault simulator capable of performing the above.

[0014]

According to a first aspect of the present invention, there is provided a line fault simulator, which is inserted into a communication line connecting a plurality of modules constituting a solid-state manufacturing system. In this case, a line failure is generated.

In such a configuration, when an operation evaluation test of a communication program for a line fault is performed, the solid state manufacturing system can be assembled and a line fault simulator can be inserted into the communication line. Thereby, an operation evaluation test assuming the same timing as that of the actual device can be performed.

Further, in such a configuration, a line fault can be generated only by creating a new simulator dedicated to line fault generation without changing the line simulator. As a result, a line failure can be easily generated as compared with a case where the line simulator is changed. As a result, an operation evaluation test of a communication program when a line failure occurs can be easily performed. As a result, it is possible to easily investigate and analyze a program failure when a line failure occurs, and to cope with the occurrence of the line failure immediately.

A line fault simulator according to claim 2 is
2. The simulator according to claim 1, wherein the line fault occurrence data holding means for holding the line fault occurrence data for causing the line fault specified by the line fault designation operation, and the line fault occurrence data holding means. Line failure generating means for generating a line failure in a communication line in a pseudo manner based on the line failure occurrence data.

In such a configuration, line fault occurrence data for causing a line fault specified by an operator's line fault designation operation is held by the line fault occurrence data holding means. Then, based on the line fault occurrence data held by the line fault occurrence data holding unit, the line fault occurrence unit simulates a line fault. As a result, the content of the line fault can be freely changed according to the operator's request.

Further, according to such a configuration, it is possible to designate that a line failure is not to be caused by a line failure designation operation. Therefore, it is possible to commercialize a solid-state manufacturing system including a line failure simulator. it can. This makes it possible to easily cope with a case where an operation evaluation test of a communication program for a line failure is desired to be performed after the operation of the solid-state manufacturing system.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[Embodiment] (1) Configuration (1-1) Arrangement Configuration of Circuit Fault Simulator First, an arrangement configuration of a circuit fault simulator according to an embodiment of the present invention will be described. That is, an arrangement configuration of the line fault simulator in the solid-state manufacturing system will be described. FIG.
Is a block diagram showing this arrangement. In the drawing, a solid-state manufacturing apparatus is shown as a representative of the solid-state manufacturing system.

The illustrated solid manufacturing apparatus includes a mechanism control device 21 for controlling the mechanism system, a temperature control device 22 for controlling the temperature of the reaction system, and a pressure control device 23 for controlling the pressure of the reaction system.
And a gas flow controller 24 for controlling the gas flow of the reaction system.
And an operation unit 25 that serves as an input / output interface between an operator and the solid manufacturing apparatus, and a main control unit 26 that controls the entire solid manufacturing apparatus.

A mechanism control device 21 and a temperature control device 22
, The pressure control device 23, the gas flow control device 24, and the operation unit 25 are SECS lines 27 (1) to 27, respectively.
It is connected to the main controller 26 via (5). Therefore, the mechanism control device 21, the temperature control device 22, the pressure control device 23, the gas flow control device 24, and the operation unit 25
And the main control unit 26 has an SECS line 27
A communication program for performing communication with a partner connected via (1) to (5) is installed.

In such a configuration, 28 (1) to 28 (2)
8 (5) shows the line fault simulator of the present embodiment. This line failure simulator 28 (1) to 28 (5)
Are inserted into the SESC lines 27 (1) to 27 (5), respectively. The arrangement configuration of the line fault simulators 28 (1) to 28 (5) of the present embodiment in the solid-state manufacturing apparatus has been described above.

(1-2) Function of Line Fault Simulator Next, the line fault simulator 28 (1) of the present embodiment.
The function of (28) to (28) will be described. The line fault simulators 28 (1) to 28 (5) of the present embodiment have the following three functions.

(1-2-1) Function for holding line fault occurrence data Line fault simulators 28 (1) to 28 of this embodiment
(5) can hold line fault occurrence data for causing a line fault specified by the operator. Here, the operation of designating the line fault is performed using the operation unit 27.

(1-2-2) Line Fault Occurrence Function Line fault simulator 28 (1) to 28 of the present embodiment
(5) has a function of causing a line failure in the SECS lines 27 (1) to 27 (5) in a pseudo manner based on the line occurrence data held by the line failure occurrence data holding function.

(1-2-3) Function for Recording Line Fault Occurrence History Line fault simulators 28 (1) to 28 (28) of this embodiment
(5) has a function of recording a line failure every time it occurs. That is, it has a function of recording the occurrence history of the line failure. The above is the function of the line fault simulators 28 (1) to 28 (5) of the present embodiment.

(1-3) Type of Line Fault Next, the line fault simulator 28 (1) of the present embodiment.
A description will now be given of a line fault that can be caused by .about.28 (5).
Line fault simulator 28 (1) -28 of the present embodiment
In (5), the following four line faults can be selectively generated.

(1-3-1) Transmission delay failure for delaying transmission of ENQ, EOT, length, text, and ACK (1-3-2) Changing the value of the length from the original value to another value Length abnormal failure to be transmitted (1-3-3) Text abnormal failure to change the content of text from original content to another content and transmit (garbled data failure) (1-3-4) Change BCC value to original BCC abnormal failure that changes from one value to another and sends

Here, ENQ, EOT, and ACK are data indicating transmission control characters used in data communication. Specifically, ENQ is data indicating an inquiry character for requesting a response from the other party. E
OT is data indicating one or more transmission end characters indicating the end of transmission. ACK is data indicating an acknowledgment character that informs the transmitting side that the operation has been completed from the receiving side.

The length is data indicating the length of the text. BCC is data indicating a block check character for performing error control. The above is the description of the line fault simulators 28 (1) to 28 (28) according to the present embodiment.
This is a line fault that can be caused by (5).

(1-4) Specific Configuration of Line Fault Simulator Next, the line fault simulator 28 will be described with reference to FIG.
An example of a specific configuration of (1) to (5) will be described. Here, FIG. 2 is a circuit failure simulator 28 (1) -28.
It is a block diagram which shows an example of a specific structure of (5). Note that the line failure simulators 28 (1) to 28 (5) have the same configuration. Therefore, the figure shows the configuration of one line fault simulator 28 (n) (n = 1, 2,..., 5) as a representative.

The illustrated circuit failure simulator 28 (n)
Is configured using a computer system. That is, the illustrated line fault simulator 28 (n) is a central processing unit (hereinafter referred to as “CPU”) that executes a line fault occurrence process and the like.
281 (n), a storage unit 282 (n) used for storing various information, a delay timer 283 (n) used for transmission delay, and a random number generation unit 284 ( n), a communication control unit 285 (n) for controlling communication with the outside, and a bus 286 connecting them.
(N).

The storage unit 282 (n) includes a CPU 281
Program storage unit A for holding the processing program of (n)
And a work storage unit B used for storing the processing results of the CPU 281, a line fault occurrence data storage unit C used for storing line fault occurrence data, and used for recording a line fault occurrence history. And a line failure occurrence history storage unit D.

FIG. 3 is a diagram conceptually showing a storage configuration of line fault occurrence data in the line fault occurrence data storage unit C.

As shown, the line failure occurrence data storage unit C includes a line failure flag storage unit C1 for storing a flag indicating whether or not a line failure is to be generated, and a delayed data storage unit for storing data to be delayed. C2, and a delay time storage unit C3 that stores data indicating the delay time.

The line failure flag storage unit C1 stores a transmission delay flag storage unit C11 that stores a transmission delay failure flag f1 that indicates whether a transmission delay failure occurs, and a length that indicates whether a length abnormal failure occurs. Length abnormal failure flag storage unit C12 that stores the abnormal failure flag f2
And a text abnormality failure flag storage unit C13 storing a text abnormality failure flag f3 indicating whether or not a text abnormality failure occurs, and a BCC storing a BCC abnormality failure flag f4 indicating whether a BCC abnormality failure occurs. An abnormal failure flag storage unit C14.

The delayed data storage section C2 has five storage sections C11 to C15, and can store up to five delayed data. This is because the maximum number of data that can be delayed due to a transmission delay fault is ENQ, EOT, length, text, and ACK. Similarly, the delay time storage unit C3 also has five storage units C31 to C35, and can store data indicating a maximum of five delay times.
The above is the description of the line fault simulator 28 according to the present embodiment.
It is an example of the specific structure of (1) -28 (5).

(2) Operation The operation of the above configuration will be described.

(2-1) Holding Operation of Line Fault Data First, the holding operation of line fault data will be described with reference to FIG. FIG. 4 shows the CPU 281 in this case.
It is a flowchart which shows the process of (n).

This processing is performed in accordance with the line fault designation operation of the operator. In this designation operation, a line failure simulator 28 (n) to be activated,
The type of line fault to be generated (transmission delay fault, length fault, text fault, BCC fault) is specified. If a transmission delay fault is specified as a line fault to be generated, the type of data to be delayed (EN
Q, EOT, text, ACK, length) and the time to be delayed are specified.

The data indicating the line fault, the data to be delayed, and the data indicating the delay time specified by this operation are transmitted to the line fault simulator 28 (n ).
Therefore, these data are transmitted to the operation unit 26 by the SECS.
Not only the line fault simulator 28 (5) directly connected via the line 27 (5) but also the line fault simulator 28 indirectly connected via the main control unit 26
(1) to 28 (4) can also be supplied.

When the CPU 281 (n) receives data from the main control unit 26 by the above-described line fault designation operation, it first identifies the type of the specified line fault (step S).
11). If the designated line fault is a transmission delay fault, 1 is set to the transmission delay fault flag f1 stored in the transmission delay fault flag storage unit C11 of the line fault flag storage unit C1 shown in FIG. S12). At this time, the designated delayed data is stored in the data storage section C2. Further, data indicating the designated delay time is stored in the delay time storage unit C3. Thus, the operation of holding the line failure occurrence data in the case where a transmission delay failure has occurred as the line failure is completed.

Now, as data to be delayed, ENQ and E
If OT is specified, the CPU 281 (n)
The ENQ is stored in, for example, the storage unit C21 of the data storage unit C2, and the EOT is stored in the storage unit C22. The storage unit C31 of the delay time storage unit C3 stores data indicating the delay time of ENQ, and the storage unit C31 stores data indicating the delay time of EOT.

If the designated line fault is a length fault fault, the CPU 281 (n) sets 1 to the length fault fault flag f2 stored in the length fault fault flag storage unit C12 shown in FIG. S1
3). As a result, the operation of holding the line failure occurrence data when the length abnormality failure occurs as the line failure is completed.

If the specified line fault is a text fault fault, the CPU 281 (n) sets 1 to the text fault flag f3 stored in the text fault flag storage unit C13 shown in FIG. S1
4). As a result, the operation of holding the line failure occurrence data when the length abnormality failure occurs as the line failure is completed.

If the designated line fault is a BCC fault, the CPU 281 (n) sets 1 to the BCC fault flag f4 stored in the BCC fault flag storage unit C14 shown in FIG. 3 (step S15). ). As a result, the operation of holding the line failure occurrence data when the BCC abnormal failure is desired to occur as the line failure is completed.

(2-2) Line Failure Occurrence Operation Next, based on the line failure occurrence data held by the holding operation of the line failure occurrence data, the SECS line 28
A line failure generating operation for causing a line failure in a pseudo manner will be described in (n).

(2-2-1) Overall Operation First, the overall operation for causing a line fault will be described with reference to FIG. Here, FIG. 5 is a flowchart showing the operation of the CPU 281 (n) in this case.

In this case, the CPU 281 (n) first
The data (reception data) transmitted from the transmission side is identified (step S21).

If the received data is ENQ, the CPU 2
81 (n) determines whether a transmission delay fault is specified for this ENQ (step S22). This determination is made based on the transmission delay failure flag f1 stored in the transmission delay failure flag storage unit C11 shown in FIG. 3 and the delayed data stored in the data storage unit C2. In this case, if 1 is set in the transmission delay failure flag f1 and ENQ is stored in the data storage unit C2, it is determined that a transmission delay failure has been specified for ENQ.

If a transmission delay fault is specified, C
The PU 281 (n) first executes an ENQ transmission delay process (Step S23). Thereby, the ENQ is delayed. Next, the CPU 281 (n) executes a process of recording a line failure occurrence history (step S24). As a result, the contents of the transmission delay failure executed in step S23 are stored in the line failure occurrence history storage unit D shown in FIG.
On the other hand, if no transmission delay failure is specified,
The CPU 281 (n) does nothing. As described above, the line failure occurrence operation when the received data is ENQ is completed.

If the received data is of length, the CP
U281 (n) first identifies a line fault specified for this length (step S25). This identification is performed by the transmission delay failure flag f1 stored in the transmission delay failure flag storage unit C11 shown in FIG. 3, the length abnormality failure flag f2 stored in the length abnormality failure flag storage unit C12, and the delayed data storage This is performed based on the delayed data stored in the unit C2.

In this case, if the transmission delay fault flag f1 is set to 1 and the length is stored as the delayed data, it is determined that the transmission delay fault is designated as the line fault. Further, the length abnormality failure flag f2
Is set to 1, it is determined that an abnormal length failure is designated as a line failure. These may be specified at the same time, or only one of them may be specified.

If the designated line fault is a transmission delay fault, the CPU 281 (n) executes a length transmission delay process (step S26), and then executes a process of recording a line fault occurrence history (step S26). S27). As a result, the length is delayed, and the content of the transmission delay fault is stored in the line fault occurrence history storage unit D shown in FIG.

On the other hand, if the specified line fault is a length error fault, the CPU 281 (n) first executes a length error value transmission process (step S).
28). As a result, a length having a value different from the received length value is transmitted. Next, the CPU 281 (n)
Executes a process of recording a line failure occurrence history (step S29). As a result, the contents of the length abnormality failure are stored in the line failure occurrence history storage unit D shown in FIG.

If neither the transmission delay failure nor the length abnormality failure is specified, the CPU 281 (n)
Does nothing. As described above, the line failure occurrence operation in the case where the received data is the length is completed.

If the received data is text, the CP
U281 (n) first identifies a line fault specified for this text (step S30). This identification is performed by the transmission delay failure flag f1 stored in the transmission delay failure flag storage unit C11 shown in FIG. 3, the text abnormality failure flag f3 stored in the text abnormality failure flag storage unit C13, and the delayed data storage. This is performed based on the delayed data stored in the unit C2.

If the designated line fault is a transmission delay fault, the CPU 281 (n) executes a text transmission delay process (step S31), and then executes a process of recording a line fault occurrence history (step S31). S32). As a result, the text is delayed, and the content of the transmission delay fault is stored in the line fault occurrence history storage unit D shown in FIG.

On the other hand, if the specified line fault is a text error fault, the CPU 281 (n) first executes a process of transmitting a text error value (step S33), and then displays the line fault occurrence history. The recording process is performed (Step S34). As a result, a text having a value different from the value of the received text is transmitted, and the contents of the text abnormality failure are stored in the line failure occurrence history storage unit D shown in FIG.

If neither the transmission delay failure nor the text abnormality failure is specified, the CPU 281 (n)
Does nothing. As described above, the line failure occurrence operation when the received data is text is completed.

If the received data is BCC, the CPU
281 (n) first identifies a line fault specified for this BCC (step S35). This identification is performed by the transmission delay failure flag f1 stored in the transmission delay failure flag storage unit C11 shown in FIG. 3, the BCC abnormal failure flag f4 stored in the BCC abnormal failure flag storage unit C14, and the delayed data storage. This is performed based on the delayed data stored in the unit C2.

If the designated line fault is a transmission delay fault, the CPU 281 (n) executes a BCC transmission delay process (step S36), and then executes a process of recording a line fault occurrence history (step S36). S37). Thus, the BCC is delayed, and the content of the transmission delay fault is stored in the line fault occurrence history storage unit D shown in FIG.

On the other hand, if the designated line fault is BCC
In the case of an abnormal failure, the CPU 281 (n)
After executing the transmission process of the BCC abnormal value (step S3
8) A line failure occurrence history recording process is executed (step S39). As a result, a BCC having a value different from the received BCC value is transmitted, and the contents of the BCC abnormality failure are stored in the line failure history storage unit D shown in FIG.

When neither the transmission delay failure nor the BCC abnormality failure is specified, the CPU 281 (n) does nothing. As described above, the line failure occurrence operation in the case where the received data is the BCC is completed.

If the received data is ACK, the CPU 2
81 (n) first determines whether or not a transmission delay fault has been designated for this ACK (step S4).
0). This determination is based on the transmission delay failure flag f1 stored in the transmission delay failure flag storage unit C11 shown in FIG.
This is performed based on the delayed data stored in the data storage unit C2.

If a transmission delay fault is specified, C
After executing the ACK transmission delay process (step S41), the PU 281 (n) executes a process of recording a line failure occurrence history (step S24). As a result, the ACK is delayed, and the contents of the transmission delay fault are stored in the line fault occurrence history storage unit D shown in FIG. On the other hand, if the transmission delay fault is not specified, the CPU 2
81 (n) does nothing. As described above, the received data is A
The line fault occurrence operation in the case of CK ends.

(2-2-2) ENQ Transmission Delay Processing Next, the ENQ transmission delay processing (step S23 in FIG. 5) will be described with reference to FIG. FIG. 6 is a flowchart showing the processing of the CPU 281 (n) in this case.

In this case, the CPU 281 (n) first
A delay time reading process is executed (step S51).
Thereby, the data indicating the delay time of ENQ stored in the delay time storage unit C3 shown in FIG. 3 is read.
Next, the CPU 281 (n) sets the delay timer 283 (n)
Is set to the ON state (step S52). Next, CP
U281 (n) monitors whether the delay timer 283 (n) has overflowed (step S53). That is, it monitors whether or not the measurement time of the delay timer 283 (n) has reached the delay time of ENQ. When the delay timer overflows, the CPU 281 (n) transmits ENQ (step S54). Thereby, the ENQ is transmitted after being delayed by the designated time.

(2-2-3) Length Transmission Delay Processing Next, the length transmission delay processing (step S26 in FIG. 5) will be described with reference to FIG. FIG. 7 is a flowchart showing the processing of the CPU 281 (n) in this case. Also in this case, the CPU 281 (n) reads the delay time (step S61),
(N) ON processing (step S62), delay timer 28
3 (n) overflow monitoring processing (step S63);
The length transmission process (step S64) is sequentially performed. As a result, the length is transmitted after being delayed by the designated time.

(2-2-4) Length Abnormal Value Transmission Process Next, the length abnormal value transmission process (step S28 in FIG. 5) will be described with reference to FIG. FIG. 8 is a flowchart showing the processing of the CPU 281 (n) in this case.

In this case, the CPU 281 (n) sets the random number generator 284 (n) to the ON state, and generates a random number in the range of 0 to 255 (step S71). Next, C
The PU 281 (n) starts the random number generation unit 2 at a predetermined timing.
84 (n) is transmitted (step S
72). As a result, a length having a value different from the received length value is transmitted.

(2-2-5) Text Transmission Delay Processing Next, text transmission delay processing (step S31 in FIG. 5) will be described in detail with reference to FIG. FIG.
It is a flowchart which shows the process of CPU281 (n) in this case.

In this case, the CPU 281 (n) first
It is determined whether the count value of the delay timing counter is 0 (step S81). Here, the delay timing counter is a counter for setting a timing at which part in the text to start the delay. This counter is configured using the internal memory of the CPU 281 (n).

When the count value of the delay timing counter is 0
In the case of, the CPU 281 (n)
(N) is turned on to generate a random number, and the random number output at a predetermined timing is set in this counter (step S82). In this case, random numbers are generated in the range of 1 to 253. Next, the CPU 281 (n) sets 1 to a data reception counter (Step S83). Here, the data reception counter is a counter indicating how many characters of the received text data are present. The count value of this counter is incremented each time data of one character is received. This counter is stored in the CPU 281
It is configured using the internal memory of (n). When this process ends, the CPU 281 (n) executes a process of step S85.

The CPU 281 (n) increments the count value of the reception counter each time data of one character is received (step S84). In step S85, the count value of the delay timing counter and the count value of the reception counter are incremented. Determine if they are equal. If they are equal, a text transmission delay process is executed (step S
86, S87, S88, S89). That is, CPU2
81 (n) is a delay time reading process (step S8)
6), ON processing of the delay timer 283 (n) (step S
87), an overflow monitoring process of the delay timer 283 (n) (step S88), and a text transmission process (step S89) are sequentially executed. When the transmission delay processing ends, the CPU 281 (n) sets the count value of the delay timing counter and the count value of the reception counter to 0.

On the other hand, when the count value of the delay timing counter is not equal to the count value of the reception counter, the CPU 281 (n) repeats the processing of step S84 and the processing of step S85. Thus, the text transmission delay processing ends.

(2-2-6) Text Abnormal Value Transmission Processing Next, the text abnormal value transmission processing (step S33 in FIG. 5) will be described in detail with reference to FIG. FIG.
Is a flowchart showing the processing of the CPU 281 (n) in this case.

In this case, the CPU 281 (n) first
It is determined whether the count value of the text abnormality timing counter is 0 (step S91). Here, the text abnormality timing counter is a counter that indicates the number of characters of the abnormal data from the beginning of the text in the text data. This counter is configured using the internal memory of the CPU 281 (n).

When the count value of the text abnormality timing counter is 0, the CPU 281 (n) sets the random number generator 284 (n) to the ON state to generate a random number, and outputs the random number output at a predetermined timing. This counter is set (step S92). In this case, the random number is 1 to 25
3 are generated. Next, the CPU 281 (n)
Set 1 to the data reception counter (step S9)
3). When this process ends, the CPU 281 (n)
The processing of step S95 is performed.

On the other hand, if the count value of the text abnormality timing counter is not 0, the CPU 281 (n)
Executes the processing of step S95 after incrementing the count value of the reception counter (step S94).

At step S95, CPU 281 (n)
Determines whether the count value of the text abnormality timing counter is equal to the count value of the reception counter, and if they are equal, sets the random number generator 284 (n) to the ON state (step S96). Thereby, a random number is generated. In this case, the range of the generated random numbers is set in the range of 0 to 255. Next, the CPU 281 (1)
The random number output from the random number generator 284 (n) is transmitted as data at a predetermined timing (step S97).
As a result, a text having a content different from the content of the received text is transmitted. When this transmission processing ends, C
The PU 281 (n) sets the count value of the text abnormality timing counter and the count value of the reception counter to 0.

On the other hand, when the count value of the text abnormality timing counter is not equal to the count value of the reception counter, the CPU 281 (n) repeats the processing of step S94 and the processing of step S95. Thus, the text abnormal value transmission process ends.

(2-2-7) Transmission Delay Processing of BCC Next, the transmission delay processing of BCC (step S36 in FIG. 5) will be described with reference to FIG. FIG. 11 is a flowchart showing the processing of the CPU 281 (n) in this case. Also in this case, the CPU 281 (n) reads the delay time (step S101),
(N) ON processing (step S102), delay timer 2
83 (n) overflow monitoring process (step S10)
3) The BCC transmission process (step S104) is sequentially performed. This causes the BCC to be delayed by the specified time.

(2-2-8) BCC Abnormal Value Transmission Process Next, the BCC abnormal value transmission process (step S38 in FIG. 5) will be described with reference to FIG. FIG. 12 is a flowchart showing the processing of the CPU 281 (n) in this case. In this case, the CPU 281 (n) first sets the random number generation unit 284 (n) to the ON state,
A random number is generated within the range of 5 (step S111).
Next, the CPU 281 (n) transmits a random number output at a predetermined timing as a 2-byte BCC (step S112). As a result, a BCC having a value different from the received BCC value is transmitted.

(2-2-9) ACK Transmission Delay Processing Next, the ACK transmission delay processing (step S41 in FIG. 5) will be described with reference to FIG. FIG. 13 is a flowchart showing the processing of the CPU 281 (n) in this case. Also in this case, the CPU 281 (n) reads the delay time (step S121),
(N) ON processing (step S122), delay timer 2
83 (n) overflow monitoring process (step S12)
3), ACK transmission processing (step S124) is sequentially performed. This delays the ACK by the specified time.

(2-2-10) SE by Transmission Delay Processing
CS Sequence Next, a change in the SECS sequence due to the above-described transmission delay processing will be described with reference to FIGS.
Here, FIG. 14 shows a normal SECS sequence. FIG. 15 shows an example of the SECS sequence when the above-described transmission delay processing is performed. FIG. 15 shows ENQ, EOT, length, TEXT, BCC, A
The case where all the CKs are delayed by the same time is shown.

As shown in FIG. 14, in the SECS sequence, ENQ, EOT, length, TEXT, BCC,
ACKs are transmitted sequentially in this order. Here, when these are delayed by the line failure simulator 28 (n),
The SECS sequence changes as shown in FIG. As shown, ENQ, EOT, length, TEXT, BC
C and ACK are delayed by a designated time from the original transmission timing indicated by the broken line. As a result, these transmission timings are as shown by the solid lines.

(3) Effects According to the present embodiment described in detail above, the following effects can be obtained.

(3-1) First, according to the line fault simulator 28 (n) according to the present embodiment, the SECS line 2
7 (n), it is possible to artificially cause a line fault in the SECS line 27 (n). Therefore, when an operation evaluation test of a communication program is performed, it is performed in a state where the solid-state manufacturing apparatus is assembled. it can. Thereby, an operation evaluation test assuming the same timing as that of the actual device can be performed.

(3-2) According to such a configuration, a line fault can be generated only by creating a new simulator dedicated to line fault occurrence without changing the line simulator. As a result, a line failure can be easily generated as compared with a case where the line simulator is changed. As a result, an operation evaluation test of a communication program when a line failure occurs can be easily performed. As a result, it is possible to easily investigate and analyze a program failure when a line failure occurs, and to cope with the occurrence of the line failure immediately.

(3-3) According to the present embodiment,
A function for holding line failure occurrence data for causing a line failure specified by an operator's line failure designation operation, and S based on the held line failure occurrence data
Since the ECS line 27 (n) is provided with a function of causing a pseudo line fault, the contents of the line fault can be freely changed according to the operator's request.

(3-4) Further, according to such a configuration, it is possible to specify that a line fault is not to be generated by a line fault specifying operation, so that the solid-state manufacturing apparatus can be connected to the line fault simulator 28 (n). It can be commercialized in a form that includes it. This makes it possible to easily cope with a case where an operation evaluation test of a communication program for a line failure is desired to be performed after the operation of the solid-state manufacturing apparatus.

(3-5) According to the present embodiment,
Since the recording function of the history of occurrence of the line failure is provided, the operation of evaluating the operation of the communication program based on the test result of the operation evaluation test of the communication program can be facilitated.

[Other Embodiments] One embodiment of the present invention has been described in detail above, but the present invention is not limited to the above embodiment.

(1) For example, in the above-described embodiment, a case has been described in which the operator can freely specify the content of the line fault. However, according to the present invention, the content of the line fault to be generated may be fixed to a predetermined content.

(2) In the above embodiment, the case where the present invention is applied to a solid manufacturing apparatus has been described. However, the invention can also be applied to solid production lines.

(3) In addition, it goes without saying that the present invention can be variously modified and implemented without departing from the scope of the invention.

[0100]

As described in detail above, according to the line fault simulator of the first aspect, since the line fault can be inserted into the communication line and a pseudo line fault can be generated in the communication line, the operation of the communication program can be performed. When the evaluation test is performed, it can be performed in a state where the solid manufacturing system is assembled. Thereby, an operation evaluation test assuming the same timing as that of the actual device can be performed.

Further, according to such a configuration, a line fault can be generated only by newly creating a dedicated simulator for generating a line fault without changing the line simulator. As a result, a line failure can be easily generated as compared with a case where the line simulator is changed. As a result, an operation evaluation test of a communication program when a line failure occurs can be easily performed. As a result, it is possible to easily investigate and analyze a program failure when a line failure occurs, and to cope with the occurrence of the line failure immediately.

According to the second aspect of the present invention, a function for holding line fault occurrence data for generating a line fault specified by a line fault designation operation by an operator, and a function for holding the held line fault occurrence data. Since the communication line is provided with a function of causing a pseudo line failure on the basis of the data, the content of the line failure can be freely changed according to the operator's request.

Further, according to such a configuration, it is possible to specify that a line fault is not to be generated by a line fault designating operation. Therefore, it is possible to commercialize a solid-state manufacturing system including a line fault simulator. it can. This makes it possible to easily cope with a case where an operation evaluation test of a communication program for a line failure is desired to be performed after the operation of the solid-state manufacturing system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an arrangement configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a specific configuration according to an embodiment of the present invention.

FIG. 3 is a diagram showing a storage configuration of line fault display data in a specific configuration of one embodiment of the present invention.

FIG. 4 is a flowchart illustrating an operation of holding line fault occurrence data according to an embodiment of the present invention.

FIG. 5 is a flowchart for explaining an overall image of a line fault occurrence operation according to the embodiment of the present invention;

FIG. 6 is a flowchart illustrating an ENQ transmission delay process according to an embodiment of the present invention.

FIG. 7 is a flowchart illustrating a length transmission delay process according to an embodiment of the present invention.

FIG. 8 is a flowchart illustrating a length abnormal value transmission process according to an embodiment of the present invention.

FIG. 9 is a flowchart illustrating a text transmission delay process according to an embodiment of the present invention.

FIG. 10 is a flowchart illustrating a text abnormal value transmission process according to an embodiment of the present invention.

FIG. 11 is a flowchart illustrating a BCC transmission delay process according to an embodiment of the present invention.

FIG. 12 is a flowchart illustrating a BCC abnormal value transmission process according to an embodiment of the present invention.

FIG. 13 is a flowchart illustrating ACK transmission delay processing according to an embodiment of the present invention.

FIG. 14 is a diagram showing an SECS sequence in a normal state.

FIG. 15 is a diagram illustrating an example of the SECS sequence when the transmission is delayed by the transmission delay processing according to the embodiment of the present invention.

FIG. 16 is a block diagram illustrating a configuration of an example of a solid-state manufacturing apparatus.

[Explanation of symbols]

Reference numeral 21: mechanism control device, 22: temperature control device, 23: pressure control device, 24: gas flow control device, 25: operation unit, 2
6 main control unit, 27 (1) to 27 (5) ... SECS line, 28 (1) to 28 (5) ... line failure simulator,
281 (n) CPU, 282 (n) storage unit, 283
(N) delay timer, 284 (n) random number generator, 28
5 (n): communication control unit, 286 (n): bus, A: program storage unit, B: working storage unit, C: line failure occurrence data storage unit, D: line failure occurrence history storage unit, C1 ... line Failure flag storage unit, C11: Transmission delay failure flag storage unit, C12: Length abnormal failure flag storage unit, C13 ...
Text abnormality failure flag storage unit, C14: BCC abnormality failure flag storage unit, C2: delayed data storage unit, C3: delay time storage unit.

Claims (2)

[Claims] 1. A pseudo line fault generating apparatus which is inserted into a communication line connecting a plurality of modules constituting a solid-state manufacturing system and causes a pseudo line fault in the communication line. 2. A line fault occurrence data holding means for holding line fault occurrence data for generating a line fault designated by a line fault designation operation, and said line fault held by said line fault occurrence data holding means. 2. A pseudo line fault generating apparatus according to claim 1, further comprising: line fault generating means for generating a line fault in the communication line based on the generated data.