CN118051369A

CN118051369A - Error detection method, device, equipment and storage medium for algorithm operation errors

Info

Publication number: CN118051369A
Application number: CN202410164141.0A
Authority: CN
Inventors: 包朝伟; 王斌; 张旭华
Original assignee: Shenzhen Pango Microsystems Co Ltd
Current assignee: Shenzhen Pango Microsystems Co Ltd
Priority date: 2024-02-02
Filing date: 2024-02-02
Publication date: 2024-05-17

Abstract

The invention discloses an error detection method, a device, equipment and a storage medium for algorithm operation errors, wherein the error detection method comprises the following steps: respectively inputting preset data streams into at least two operation modules which are connected in sequence; performing cyclic redundancy check calculation on the output result of each operation module to obtain and store the cyclic redundancy check actual value corresponding to each operation module; judging the correctness of the target result value output by the last operation module through the upper computer; when the target result value is correct, judging that the cyclic redundancy check actual value corresponding to each operation module is normal data; repeatedly executing the steps for a plurality of times, and storing the normal data or the abnormal data corresponding to each operation module obtained by each execution. The method disclosed by the invention can solve the problems that in the prior art, the scene items of algorithm multi-layer calling, longer data link, complex data flow and algorithm statement need to be copied in a large quantity can not be accurately judged in the error occurrence position.

Description

Error detection method, device, equipment and storage medium for algorithm operation errors

Technical Field

The invention belongs to the technical field of chips, and particularly relates to an error detection method, device, equipment and storage medium for algorithm operation errors.

Background

When the calculation is performed through the calculation module of the programmable device, the algorithm error in the calculation module is fed back to the test platform (such as a host computer) to be a final result error, and particularly, where the error of the calculation module occurs cannot be resolved, so that corresponding correction cannot be performed on the error.

In this regard, in the prior art, a debug tool is generally used to grab out the data inside the programmable device to determine the data error. However, for the scene items of multi-layer algorithm call, longer data link and complex data flow, especially for the scene items of algorithm statement which need to be copied in a large amount, the internal data of the programmable device is very difficult to grasp by using a debugging tool, and the grasped data cannot judge the error.

In view of the foregoing, there is a need in the art for a method that can accurately determine the error occurrence position for a scenario item that requires a large number of copies for algorithm multi-layer calls, relatively long data links, complex data flow, and algorithm statements.

Disclosure of Invention

The invention provides an error detection method, device, equipment and storage medium for algorithm operation errors, which are used for solving the problems that in the prior art, scene items which are used for algorithm multi-layer calling, relatively long in data link, complex in data flow and large in number of copies of algorithm sentences are required, and the occurrence positions of errors cannot be accurately judged.

In order to solve the above technical problem, in a first aspect, the present invention provides an error detection method for algorithm operation errors, which is applied to a programmable device, and the method includes:

Respectively inputting preset data streams into at least two operation modules which are connected in sequence;

performing cyclic redundancy check calculation on the output result of each operation module to obtain and store a cyclic redundancy check actual value corresponding to each operation module;

judging the correctness of the target result value output by the last operation module through an upper computer;

When the target result value is correct, judging that the cyclic redundancy check actual value corresponding to each operation module is normal data;

Repeatedly executing the steps of inputting preset data streams into at least two sequentially connected operation modules respectively until the step, judging that the actual cyclic redundancy check value corresponding to each operation module is normal data when the target result value is correct, and storing the normal data or the abnormal data corresponding to each operation module obtained by each execution, wherein the abnormal data is different from the normal data;

And judging the operation module corresponding to the abnormal data as a problem operation module.

Optionally, when a preset data stream is input into a target operation module each time, monitoring whether the preset data stream input into the target operation module by a previous operation module of the target operation module is the same each time;

and when the data input to the target operation module by the last operation module is different, inputting pseudo-random binary sequence data to the target operation module each time.

Optionally, the performing cyclic redundancy check calculation on the output result of each operation module to obtain and store a cyclic redundancy check actual value corresponding to each operation module includes:

counting the number of output results of each operation module;

And performing cyclic redundancy check calculation on the output result of each operation module until the number of the output results reaches a preset threshold value, stopping cyclic redundancy check calculation on the output result, outputting the cyclic redundancy check actual value corresponding to each operation module obtained through final calculation, and storing the cyclic redundancy check actual value.

Optionally, the preset mode of the preset threshold value is:

counting to obtain the number increment of the output results of each operation module in a preset time period;

calculating a first ratio of a number increment of an output result of each operation module;

Setting a preset threshold value of each operation module, and enabling a second ratio of the preset threshold value of each operation module to be the first ratio.

In a second aspect, the present invention provides an error detection apparatus for detecting arithmetic operation errors, applied to a programmable device, the apparatus comprising: the first input module is used for respectively inputting preset data streams into at least two operation modules which are connected in sequence;

The computing module is used for carrying out cyclic redundancy check computation on the output result of each computing module to obtain and store the cyclic redundancy check actual value corresponding to each computing module;

the first judging module is also used for judging the correctness of the target result value output by the last operation module through the upper computer;

The second judging module is used for judging that the cyclic redundancy check actual value corresponding to each operation module is normal data when the target result value is correct;

the third judging module is used for repeatedly executing the operations executed by the first input module, the calculating module, the first judging module and the second judging module for a plurality of times and storing the normal data or the abnormal data corresponding to each operation module obtained by each execution, wherein the abnormal data is different from the normal data;

And the fourth judging module is used for judging the operation module corresponding to the abnormal data as a problem operation module.

In a third aspect, the present invention provides an error detection apparatus for arithmetic operation errors, comprising a memory and a processor, wherein:

The memory is used for storing a computer program;

The processor is configured to read the program in the memory and execute the steps of the method for detecting errors in arithmetic operations provided in the first aspect.

In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon a readable computer program which when executed by a processor performs the steps of the method for error detection of arithmetic operation errors as provided in the first aspect above.

Compared with the prior art, the error detection method for algorithm operation errors has the following beneficial effects:

According to the invention, the data are calculated through a plurality of sequentially connected operation modules (corresponding to complex scene items such as algorithm multi-layer call, longer data link, complex data flow direction, large quantity of copying of algorithm sentences and the like in the prior art), and the result errors fed back to the upper computer through the plurality of operation modules are finally used for judging whether the operation modules work normally (namely, the operation modules work normally when the result fed back to the upper computer is not wrong), and the operation result values output by the operation modules are subjected to cyclic redundancy check calculation when the operation modules work normally so as to obtain the cyclic redundancy check normal data corresponding to the operation modules, so that when the operation modules work abnormally, the obtained actual values are inconsistent with the cyclic redundancy check normal data corresponding to the operation modules, and the abnormal operation of the operation modules can be judged. In summary, the invention can directly locate the operation module with problems in the data operation process, thereby locating the specific occurrence position of the error, and thus solving the problems that the prior art needs a large number of copied scene items for algorithm multi-layer call, longer data link, complex data flow and algorithm statement, and the error occurrence position cannot be accurately judged.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present application, but not all embodiments, and other drawings obtained according to these drawings without inventive effort are all within the scope of the present application.

FIG. 1 is a flow chart of an error detection method for arithmetic operation errors provided by an embodiment of the invention;

FIG. 2 is a flowchart of an error detection apparatus for detecting arithmetic operation errors according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of an error detection device for algorithm operation errors according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of an error detection device for algorithm operation errors according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

In order that the present disclosure may be more fully described and fully understood, the following description is provided by way of illustration of embodiments and specific examples of the present application; this is not the only form of practicing or implementing the application as embodied. The description covers the features of the embodiments and the method steps and sequences for constructing and operating the embodiments. However, other embodiments may be utilized to achieve the same or equivalent functions and sequences of steps. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.

In the description of the embodiments of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; the text "and/or" is merely an association relation describing the associated object, and indicates that three relations may exist, for example, a and/or B may indicate: in addition, in the description of the embodiments of the present application, "plural" means two or more, and other words and the like, it is to be understood that the preferred embodiments described herein are for illustration and explanation of the present application only, and are not intended to limit the present application, and embodiments of the present application and features in the embodiments may be combined with each other without conflict.

As shown in fig. 1, a flowchart of an error detection method for algorithm operation errors provided in an embodiment of the present invention includes the following steps.

Step S101, respectively inputting preset data streams into at least two operation modules which are connected in sequence.

It should be noted that, since the computing module in the prior art is usually a complete computing module, the multiple computing modules in this step are split from one complete computing module, and the specific number of computing modules can be set according to the specific needs in application, it can be understood that the higher the error detection precision of the required algorithm computing error is, the more the specific number of computing modules is split;

It should be further noted that, the splitting rule of splitting a complete computing module into a plurality of computing modules may be determined according to specific requirements during application, and as a specific example, when computing data through a complete computing module, there may be a plurality of computing steps, and each computing step may be split into one computing module, so that each computing module may correspondingly implement a computing function corresponding to one computing step.

It should be noted that the preset data streams input into the plurality of operation modules may be the same or different, and may be specifically determined according to specific requirements during application.

It is to be understood that, in this step, the connection order of the plurality of operation modules is determined based on the complete operation functions executed by the plurality of operation modules (i.e., the operation functions of the complete operation modules of the plurality of operation modules are obtained by splitting), and as a specific example, assuming that the operation functions of the complete operation modules are that the area of the equilateral triangle is calculated by the side length of the equilateral triangle, the plurality of operation modules obtained by splitting the complete operation module may be set to be the first operation module for obtaining the square value of the side length, the second operation module for obtaining the square value of the side length and the first product value of the root number 3, and the third operation module for obtaining the division value of the first product value and the division value of the 4, and it is to be understood that the connection order of the operation modules is that the first operation module to the third operation module are sequentially connected under this setting.

Step S102, performing cyclic redundancy check calculation on the output result of each operation module to obtain and store the cyclic redundancy check actual value corresponding to each operation module.

It should be noted that the cyclic redundancy check (Cyclic redundancy check, CRC) is a hash function that generates a short fixed bit check code according to data such as a network packet or a computer file, and is mainly used to detect or check errors that may occur after data transmission or storage, the generated number is calculated before transmission or storage and appended to the data, and then the receiving party performs a check to determine whether the data has changed.

It should be further noted that, as the common criteria for CRC, there are CRC-4, CRC-5, CRC-6, CRC-7, CRC-8, CRC-16, and CRC-32, etc., and the number of bits of the transmitted data that can be checked by different CRC criteria may be different, so that the CRC criteria may be selected according to the number of bits of the transmitted data and the checking requirement in specific applications.

For example, CRC-16 works on the principle: the CRC-16 code is composed of two bytes, each bit of a CRC register (used for registering each calculated value in the CRC calculation process) is preset to be 1 at the beginning, then the CRC register is exclusive-ored with 8 bits of data (namely transmission data), then the CRC register is shifted from high to low, 0 is complemented at the position of the highest bit, the lowest bit (shifted out of the CRC register after shifting) is 1, the register is exclusive-ored with a predefined polynomial code, otherwise, if the lowest bit is 0, the exclusive-ored is not needed, the shifting from high to low is repeated 8 times, the first 8 bits of data are processed, the value of the CRC register is exclusive-ored with the next 8 bits of data at the moment, and 8 times of shifting similar to the former data are carried out, and the value in the CRC register is the final CRC calculated value after all character processing is completed.

And step S103, judging the correctness of the target result value output by the last operation module through the upper computer.

Because the upper computer is a computer capable of sending out a control command, the screen of the upper computer can display the received data, so that a relevant technician can determine whether the data is an expected result or not through the data displayed by the upper computer, when the data is not the expected result, the operation modules with a certain number of abnormal operations can be determined, and if the data is the expected result, the operation modules can be determined to work normally.

Step S104, when the target result value is correct, determining that the cyclic redundancy check actual value corresponding to each operation module is normal data.

It can be understood that when the upper computer judges that the target result value output by the last operation module is correct, each operation module can be determined to work normally, and the actual CRC value obtained by performing CRC operation on the output result of each operation module is natural data.

Step S105, repeatedly executing steps S101 to S104 a plurality of times, and storing the normal data or the abnormal data corresponding to each operation module obtained by each execution.

Wherein the abnormal data is data different from the normal data.

It should be noted that, when each execution of steps S101 to S104 is performed, the preset data stream input by each operation module is the same preset data stream, so that when each execution is performed, it is determined that the actual CRC value corresponding to each operation module is normal data or abnormal data, the actual CRC value may be obtained by comparing the actual CRC value obtained in steps S101 to S104 with the normal data obtained in steps S101 to S104, that is, when the actual CRC value obtained in each execution is the same as the normal data obtained in steps S101 to S104, the actual CRC value is normal data, and when the actual CRC value obtained is different from the normal data, the actual CRC value is abnormal data.

And step S106, judging the operation module corresponding to the abnormal data as a problem operation module.

It can be understood that in the embodiment of the invention, the data is calculated by a plurality of sequentially connected operation modules (corresponding to complex scene items such as multi-layer algorithm call, relatively long data link, complex data flow, and large quantity of replication needed by algorithm sentences in the prior art), and whether each operation module works normally or not is judged by the result errors finally fed back to the upper computer by the plurality of operation modules (namely, each operation module works normally when the result fed back to the upper computer is not wrong), and the operation result value output by each operation module is calculated by cyclic redundancy check when each operation module works normally, so as to obtain the cyclic redundancy check normal data corresponding to each operation module. In summary, the invention can directly locate the operation module with problems in the data operation process, thereby locating the specific occurrence position of the error, and thus solving the problems that the prior art needs a large number of copied scene items for algorithm multi-layer call, longer data link, complex data flow and algorithm statement, and the error occurrence position cannot be accurately judged.

In an alternative implementation manner, when a preset data stream is input into a target operation module each time, monitoring whether the preset data stream input into the target operation module by a last operation module of the target operation module is the same or not;

It can be understood that, when the data input to each operation module is the same, the CRC calculation value of the output result of each operation module obtained each time can be compared, so as to determine the normal data and the abnormal data corresponding to the CRC calculation value.

It should be noted that, when the upper computer determines the correctness of the target result value output by the last operation module, and further determines that each operation module works normally when the target result value is correct, the output result of the last operation module needs to be input as the input result of the next operation module.

Therefore, in this implementation, when the data input to the target operation module by the previous operation module is different, a pseudo-random binary sequence (PRBS) needs to be input to the target operation module each time, in which case it is determined whether the CRC calculated by the CRC of the output result of the target operation module is normal data, and it is not possible to refer to the normal data determined according to the upper computer. In this embodiment, the CRC actual values of the output results obtained by the target operation module operating a plurality of times may be stored and compared, and if a plurality of CRC actual values are the same, the CRC actual values may be determined as normal data, and if the CRC actual values are the same, the CRC actual values that are inconsistent with the same CRC actual values may be abnormal data.

It is further understood that when the preset data stream input to the target operation module by the previous operation module is the same, the PRBS data need not be input to the target operation module, which can effectively save resources compared with the case where the PRBS data generating module needs to be specifically set to the target operation module to input the PRBS data to the target operation module.

As a specific example, fig. 2 shows a workflow diagram of an error detection device for arithmetic operation errors according to an embodiment of the present invention, where the error detection device includes two operation modules, namely, a module a and a module B, and a selector is disposed before the module a, where the selector may select whether PRBS data is input to the module a or original data (i.e., a preset data stream) through a sel signal before the module a, and may select whether PRBS data is input to the module B or an output result of the module B through the sel signal before the module B, and may control data transmission through a clock signal (Clk) and a signal (Vld) indicating that the data is valid during data (i.e., date in the drawing) transmission.

In an alternative implementation, the step S102 includes:

counting the number of output results of each operation module;

Specifically, the number of output results of each operation module in this implementation may be counted by a counter.

It should be noted that, the preset threshold in this implementation manner may be set according to specific requirements during application, for example, if the computing resources for performing CRC computation on the output result of each operation module are limited, the preset threshold may be set to a smaller value, for example, 500 or 1000, etc., and if the computing resources for performing CRC computation on the output result of each operation module are abundant, and the reliability of the value obtained by the CRC computation needs to be made higher, the preset threshold may be set to a larger value, for example, 5000 or 10000, etc.

It can be understood that, when performing CRC calculation on data, since the operation result value of CRC depends on the number of operation data, in order to make the result value of CRC operation on the output result of the same operation module relatively comparable to determine whether the result value is normal data or abnormal data, the number of output data of CRC calculation on the same operation module needs to be the same, and by making the number of output results participating in CRC operation be a preset threshold in this implementation, the number of output results participating in CRC operation each time can be controlled to be the same.

As a specific example, as shown in fig. 2, the output result of the module a may be counted by a counter (i.e., CNT in the figure), and the counted result may be transmitted to a virtual input output (virtual input output, VIO) for presentation, and when the counted result reaches a preset threshold, the VIO sends a Stop calculation signal (i.e., stop in the figure) to the CRC module (i.e., CRC in the figure) performing CRC calculation on the output result, so that the CRC module stops CRC calculation.

In an alternative implementation, the preset manner of the preset threshold is:

The preset time period may be set according to specific requirements in application, for example, may be 5 minutes, may be 10 minutes, may be 30 minutes, and the like.

It should be understood that the preset threshold value of each operation module may be any specifically set value, so long as the ratio of the preset threshold value of each operation module is ensured to be the same as the first ratio.

It can be understood that, because the operation rates of the operation modules may be different, the number of output results of the operation modules in the same time period may be increased differently, so that the preset threshold of each operation module is set according to the ratio of the number of output results of the operation modules in the same time period, and the preset threshold can be sufficiently large on the basis of fully utilizing the operation resources of each operation module, so that the reliability of the value obtained by CRC calculation can be increased.

Based on the above error detection method of algorithm operation errors, an embodiment of the present invention provides an error detection device of algorithm operation errors, as shown in fig. 3, the error detection device includes:

A first input module 310, configured to input preset data streams into at least two sequentially connected operation modules respectively;

the computing module 320 is configured to perform cyclic redundancy check computation on an output result of each computing module, obtain a cyclic redundancy check actual value corresponding to each computing module, and store the cyclic redundancy check actual value;

The first judging module 330 is further configured to judge, by using an upper computer, correctness of the target result value output by the last computing module;

A second judging module 340, configured to judge that the cyclic redundancy check actual value corresponding to each of the operation modules is normal data when the target result value is correct;

A third determining module 350, configured to repeatedly execute the operations executed by the first input module, the computing module, the first determining module, and the second determining module for multiple times, and store the normal data or the abnormal data corresponding to each computing module obtained by each execution, where the abnormal data is different from the normal data;

a fourth judging module 360, configured to judge the operation module corresponding to the abnormal data as a problem operation module.

For other details of implementing the above technical solution by each module in the error detection device for algorithm operation errors, reference may be made to the description in the error detection method for algorithm operation errors provided in the above embodiment of the present invention, which is not repeated here.

The embodiment of the invention also provides a schematic structural diagram of an error detection device for arithmetic operation errors based on the above error detection method, as shown in fig. 4, where the identification device includes a processor 41 and a memory 42 coupled to the processor 41. The memory 42 stores a computer program which, when executed by the processor 41, causes the processor 41 to execute the steps of the algorithm operation error detection method in the above-described embodiment.

For further details of the implementation of the above technical solution by the processor 41 in the error detection device with the algorithm operation error, reference may be made to the description of the error detection method with the algorithm operation error provided in the above embodiment of the present invention, which is not repeated here.

Wherein the processor 41 may also be referred to as a central processing unit (Central Processing Unit, CPU), the processor 41 may be an integrated circuit chip with signal processing capability; the processor 41 may also be a general purpose processor, such as a microprocessor or the processor 41 may also be any conventional processor, digital Signal Processor (DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field programmable gate array (Field Programmable GATE ARRAY, FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like.

As shown in fig. 5, an embodiment of the present invention further provides a schematic structural diagram of a computer-readable storage medium, on which a readable computer program 51 is stored; the computer program 51 may be stored in the storage medium in the form of a software product, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a mobile hard disk, a magnetic disk or a compact disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), or a terminal device such as a computer, a server, a mobile phone, a tablet, etc.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.

The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, tape), optical medium, or semiconductor medium (e.g., solid State Drive (SSD)), etc.

The above description has been made in detail for the technical solutions provided by the present application, and specific examples are applied in the present application to illustrate the principles and embodiments of the present application, and the above examples are only used to help understand the method and core ideas of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the one or more processes and-

Or a block diagram of one or more of the functions specified in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. An error detection method for algorithm operation errors, which is applied to a programmable device, is characterized by comprising the following steps:

2. The method for detecting an arithmetic operation error according to claim 1, wherein:

When a preset data stream is input into a target operation module each time, monitoring whether the preset data stream input into the target operation module by a last operation module of the target operation module is the same or not;

3. The method for detecting an arithmetic operation error according to claim 1, wherein the performing a cyclic redundancy check calculation on the output result of each operation module to obtain and store a cyclic redundancy check actual value corresponding to each operation module includes:

counting the number of output results of each operation module;

4. The method for detecting an arithmetic operation error according to claim 3, wherein the preset threshold is preset in the following manner:

setting the preset threshold value of each operation module, so that the second ratio of the preset threshold value of each operation module is the first ratio.

5. An error detection device for algorithm operation errors, which is applied to a programmable device, and is characterized by comprising:

the first input module is used for respectively inputting preset data streams into at least two operation modules which are connected in sequence;

6. The arithmetic operation error detection apparatus according to claim 5, further comprising:

The monitoring module is used for monitoring whether the preset data stream input to the target operation module by the last operation module of the target operation module is the same or not when the preset data stream is input to the target operation module each time;

And the second input module is used for inputting pseudo-random binary sequence data to the target operation module each time when the data input to the target operation module by the last operation module are different.

7. The algorithmic operation error detection device of claim 5, wherein the computation module is further configured to:

counting the number of output results of each operation module;

8. The apparatus for detecting an arithmetic operation error according to claim 7, wherein the preset threshold is preset in the following manner:

9. An error detection apparatus for arithmetic operation errors, comprising a memory and a processor, wherein:

The memory is used for storing a computer program;

The processor is configured to read the computer program in the memory and execute the steps of the error detection method for arithmetic errors according to any one of claims 1-4.

10. A computer readable storage medium, having stored thereon a readable computer program which when executed by a processor implements the steps of the method for error detection of arithmetic operations according to any of claims 1-4.