CN111625492A - Multi-chip unaddressed communication method, electronic device, and medium - Google Patents
Multi-chip unaddressed communication method, electronic device, and medium Download PDFInfo
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Abstract
The invention discloses a multi-chip non-addressing communication method, an electronic device and a medium, belonging to the technical field of communication, wherein the method comprises the steps of firstly connecting a master chip and m slave chips in series through signal beams to generate m slave chip numbers corresponding to the m slave chips which are arranged in sequence; distributing data to m corresponding slave chips by the master chip in each period of the clock signal line based on the serial connection to obtain n data packets corresponding to the m slave chips arranged in sequence; when a certain slave chip receives a data packet sent by the master chip, verifying whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located; and if so, determining the serial number of the slave chip corresponding to the slave chip where the data packet is received. The serial connection method has the advantages that the serial connection of the master chip and the slave chip automatically generates the serial number of the slave chip, the serial number position corresponding to the slave chip is quickly positioned through data transmission, the operation is simple, and the efficiency is high.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a multi-chip non-addressing communication method, an electronic device and a medium.
Background
With the advancement of science and technology, the arrangement of AI-capable, computationally intensive and dense chips is meeting ever-increasing market demands and applications.
However, conventional communication has also been deficient. For example, the devices perform communication transmission in a parallel manner, the IP addresses of the devices need to be set first, and the devices corresponding to the IP addresses are selected to transmit data correspondingly, so that the encoding of the IP addresses for communication transmission is troublesome, and the communication is single-wire transmission, which is inefficient.
Disclosure of Invention
The invention provides a multi-chip addressing-free communication method, an electronic device and a medium, which solve the problems of troublesome IP address coding, single-wire communication transmission and low communication efficiency of the traditional communication transmission.
In order to achieve the above object, the present invention provides a multi-chip unaddressed communication method, which comprises:
connecting a master chip and m slave chips in series through a signal beam to generate m slave chip numbers corresponding to the m slave chips arranged in sequence, wherein the signal beam comprises a flow control signal line, a clock signal line, a forward transmission signal line and a backward transmission signal line;
distributing data to m corresponding slave chips by the master chip in each period of a clock signal line based on serial connection to obtain n data packets corresponding to the m slave chips arranged in sequence, wherein the data contained in each data packet is the same;
when a certain slave chip receives a data packet sent by the master chip, verifying whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located;
if the cycle number of the data packet transmitted to a certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located; determining the slave chip number corresponding to the slave chip where the data packet is received.
Preferably, the master chip distributes the data to the m corresponding slave chips in each cycle of the clock signal line, the data obtained from each slave chip is packaged into a corresponding data packet, and the data packet includes the data distributed from the slave chip and the corresponding slave chip numbers.
Preferably, the flow control signal line comprises a high level flow control and a low level flow control, and when the flow control signal line is in the high level flow control, the flow control signal line controls data transmission between the master chip and the slave chip; and
when the flow control signal line is in low-level flow control, data transmission between the master chip and the slave chip is invalid.
Preferably, the control of data transmission between the master chip and the slave chip by the flow control signal line comprises at least 1 clock cycle formed by the clock signal line on a rising edge and a falling edge;
when the clock signal line is at a rising edge, triggering the master chip to send data to the slave chip on a forward signal line, or triggering the slave chip to send data to the master chip on a backward signal line; and
when the clock signal line is at a falling edge, the slave chip receives corresponding data, or the master chip receives corresponding data.
Preferably, the period calculation formula of the clock signal line is: T1/F
T is the clock period and F is the clock frequency.
Preferably, the method further comprises:
when the master chip receives a data packet sent by a certain slave chip, whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located is verified.
In addition, to achieve the above object, the present invention further provides an electronic device, which includes a memory and a processor, wherein the memory stores therein a non-addressed communication program operable on the processor, and the non-addressed communication program, when executed by the processor, implements the following steps:
a series connection step: connecting a master chip and m slave chips in series through a signal beam to generate m slave chip numbers corresponding to the m slave chips arranged in sequence, wherein the signal beam comprises a flow control signal line, a clock signal line, a forward transmission signal line and a backward transmission signal line;
an acquisition step: distributing data to m corresponding slave chips by the master chip in each period of a clock signal line based on serial connection to obtain n data packets corresponding to the m slave chips arranged in sequence, wherein the data contained in each data packet is the same;
a verification step: when a certain slave chip receives a data packet sent by the master chip, verifying whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located;
a determination step: if the cycle number of the data packet transmitted to a certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located; determining the slave chip number corresponding to the slave chip where the data packet is received.
In addition, to achieve the above object, the present invention further provides a computer-readable storage medium, which includes a non-addressed communication program, and when the non-addressed communication program is executed by a processor, the steps of the multi-chip non-addressed communication method as described in any one of the above items can be implemented.
The invention provides a multi-chip non-addressing communication method, an electronic device and a medium.A main chip and m slave chips are connected in series through a signal beam to generate m slave chip numbers corresponding to the m slave chips which are arranged in sequence; distributing data to m corresponding slave chips by the master chip in each period of the clock signal line based on serial connection to obtain n data packets corresponding to the m slave chips arranged in sequence, wherein the data contained in each data packet is the same; when a certain slave chip receives a data packet sent by the master chip, verifying whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located; and if so, determining the serial number of the slave chip corresponding to the slave chip where the data packet is received. The serial number generating method automatically generates serial numbers of the slave chips when the master chip and the slave chip are connected in series, quickly positions the serial number positions corresponding to the slave chips through data transmission, and has the advantages of simple operation and high efficiency.
To more clearly illustrate the structural features and effects of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Drawings
FIG. 1 is a flow chart of a multi-chip unaddressed communication method of the present invention;
FIG. 2 is a schematic diagram of a multi-chip series connection of FIG. 1;
FIG. 3 is a schematic diagram of the phase relationship of the signal beams of FIG. 1;
FIG. 4 is a schematic diagram of transmission phases of a clock signal line and a forward signal line;
FIG. 5 is a schematic diagram of transmission phases of a clock signal line and a counter signal line;
FIG. 6 is another flow chart of the multi-chip unaddressed communication method of the present invention;
FIG. 7 is a diagram of an electronic device according to a preferred embodiment of the present invention;
FIG. 8 is a block diagram of a preferred embodiment of the unaddressed communication routine of FIG. 7;
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "including" and "having," and any variations thereof, in the description and claims of this application and the description of the above figures are intended to cover non-exclusive inclusions. The terms "first," "second," and the like in the description and claims of this application or in the above-described drawings are used for distinguishing between different objects and not for describing a particular order.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
An embodiment of the present invention provides a multi-chip unaddressed communication method, and referring to fig. 1, a flow chart of the multi-chip unaddressed communication method of the present invention is shown, where the method includes:
and S1, serially connecting the master chip and the m slave chips through a signal beam to generate m slave chip numbers corresponding to the m slave chips arranged in sequence, wherein the signal beam comprises a flow control signal line, a clock signal line, a forward transmission signal line and a backward transmission signal line.
In the embodiment, the master chip and m slave chips arranged in sequence are arranged on the PCB, connecting a master chip with a slave chip and connecting two adjacent slave chips through a signal beam to form a communication link connected in series, automatically generating m corresponding slave chip numbers (for example, 1, 2, 3, 4.. m, m represents a positive integer) by m sequentially arranged slave chips, wherein the slave chip numbers are used for confirming the data position of communication transmission, namely, the specific position of the slave chip for receiving or sending data is determined, compared with the traditional chip which needs to compile the IP address of the chip to be transmitted before data transmission and then carry out data transmission, the method is time-consuming and troublesome, the invention automatically generates the serial number of the slave chip when the master chip and the slave chip are arranged in series, avoids coding the IP address of each slave chip, and has simple operation and high data transmission efficiency.
Specifically, referring to fig. 2 and fig. 3, a schematic diagram of a structure of a multi-chip series connection and a schematic diagram of a phase relationship of a signal beam in fig. 1 are shown, where the signal beam includes a flow control signal line, a clock signal line, a forward transmission signal line and a backward transmission signal line, and the flow control signal line is denoted by TEN and is used to control the start and end of transmission of a frame of data on the forward transmission signal line or the backward transmission signal line; the clock signal line is represented by TCLK, and generates a pulse signal with periodicity; the forward signal line is represented by TXDA and is used for transmitting communication data from the master chip to the slave chip; the reverse signal line is denoted by RXDA and is used for transmitting communication data from the slave chip to the master chip.
It should be noted that the serial master-slave chips can complete bidirectional data transmission on the forward transmission signal line or the backward transmission signal line simultaneously, and in the data transmission process, the chips are connected in series to automatically generate slave chip numbers corresponding to m slave chips, so that the slave chips can be positioned to the slave chip positions where the data transmission is received or sent.
Further, the flow control signal line comprises a high-level flow control line and a low-level flow control line, and when the flow control signal line is in the high-level flow control state, the flow control signal line controls data transmission between the master chip and the slave chip; and
when the flow control signal line is in low-level flow control, data transmission between the master chip and the slave chip is invalid.
In this embodiment, when the current control signal line is in high-level current control, the current control signal line is triggered to control data transmission between the master chip and the slave chip, including receiving or sending data between the master chip and the slave chip; when the flow control signal line is in low-level flow control, the enabling transmission of the flow control signal line is limited, the communication operation between the master chip and the slave chip on the forward transmission signal line and the backward transmission signal line is not reacted, and the operation is invalid.
Further, referring to fig. 4 and fig. 5, a transmission phase diagram of a clock signal line corresponding to a forward transmission signal line and a transmission phase diagram of a clock signal line corresponding to a backward transmission signal line are respectively shown, where the flow control signal line controls data transmission between the master chip and the slave chip to include at least 1 clock cycle formed by the clock signal line on a rising edge and a falling edge;
when the clock signal line is at a rising edge, triggering the master chip to send data to the slave chip on a forward signal line, or triggering the slave chip to send data to the master chip on a backward signal line; and
when the clock signal line is at a falling edge, the slave chip receives corresponding data, or the master chip receives corresponding data.
For example, in one embodiment, it takes a plurality of clock cycles for the master chip to send data to a certain slave chip before the data transmission is completed, and the clock cycles formed by the rising edge and the falling edge of the clock signal line are iterated until the data transmission is completed, at which time, the flow control signal line is changed from high-level flow control to low-level flow control.
Further, the period calculation formula of the clock signal line is as follows: T1/F
T is the clock period and F is the clock frequency.
For example, in one embodiment, if a clock frequency is 10MHz, 10000000 clock cycles can be generated in 1s, that is, 10000000 bits of data can be transmitted in 1 s; then, a clock frequency of 10MHz corresponds to one period:
T＝1/F＝1/10000000＝0.0000001S＝100ns。
and S2, distributing data to the corresponding m slave chips by the master chip in each period of the clock signal line based on the serial connection to obtain n data packets corresponding to the m slave chips arranged in sequence, wherein the data contained in each data packet is the same.
In this embodiment, the master chip distributes data to m corresponding slave chips in each cycle of the clock signal line, and data obtained by each slave chip is encapsulated into a corresponding data packet, where the data packet includes data distributed by the slave chip and a corresponding slave chip number. It should be noted that the data distributed to each slave chip by the master chip connected in series is the same, and the data obtained by the even distribution is packaged into a data packet with the corresponding slave chip number.
S3, when a certain slave chip receives the data packet sent by the master chip, verifying whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located.
For example, in an alternative embodiment, the main chip and the operation chip 1, the operation chip 2, and the operation chip 3 are included, the transmission of the periodic data packet is 4 bits, and the total data is 12 bits, then the mode of the forward transmission signal line (TXDA) that the main chip transmits data toward the operation chip is as follows:
a1, when the high level flow control is carried out, the main chip sends a 4-bit data packet of a period to the operation chip 1, and at the moment, the operation chip 1 has the 4-bit data packet;
a2, when the next period is in high level flow control, the main chip continuously sends a 4-bit data packet of one period to the operation chip 1, at the moment, the operation chip 1 has an 8-bit data packet, meanwhile, the operation chip 1 connected in series transmits a 4-bit data packet of one period to the operation chip 2, and the operation chip 2 has a 4-bit data packet;
a3, when the current control is in a high level flow control in another period, the main chip continuously sends a 4-bit data packet of one period to the operation chip 1, at this time, the operation chip 1 has a 12-bit data packet, meanwhile, the operation chip 1 connected in series transmits a 4-bit data packet of one period to the operation chip 2, the operation chip 2 has an 8-bit data packet, the operation chip 2 transmits a 4-bit data packet of one period to the operation chip 3, and the operation chip 3 has a 4-bit data packet, so that the data transmission of one total data of 12 bits is finished. Therefore, after the data transmission cycle is 3 times, the certain slave chip receives the data packet transmitted by the master chip, and therefore, the certain slave chip is determined to be the slave chip 3 by the data transmission.
S4, if the cycle number of the data packet transmitted to a certain slave chip is equal to the slave chip number of the certain slave chip; determining the slave chip number corresponding to the slave chip where the data packet is received.
In an embodiment, when a master chip sends a data packet (e.g., data enclosure 4M) to a certain slave chip (e.g., slave chip 3), if the number of cycles for transmitting the data packet to the certain slave chip is equal to the slave chip number where the certain slave chip is located, that is, the master chip transmits the data packet 4M to the slave chip 3 after 3 cycles, it may be determined that the certain slave chip that finally receives the data packet is the slave chip 3 according to the serial communication link, so as to determine the specific position of the slave chip for this communication transmission, thereby implementing non-addressing communication.
Further, referring to fig. 6, it is another flowchart of the multi-chip unaddressed communication method of the present invention, and the step S3 in the method may further be:
when the master chip receives a data packet sent by a certain slave chip, whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located is verified.
For example, in an alternative embodiment, the back propagation signal line (TXDR) transmits data toward the main chip by the operation chip:
b1, when the high level flow control is performed, the operation chip 3 sends a 4-bit data packet of a period to the operation chip 2, and at the moment, the operation chip 2 has the 4-bit data packet;
b2, when the next period is in high level flow control, the operation chip 3 continuously sends a 4-bit data packet of one period to the operation chip 2, at this time, the operation chip 2 has an 8-bit data packet, meanwhile, the operation chip 2 connected in series transmits a 4-bit data packet of one period to the operation chip 1, and the operation chip 1 has a 4-bit data packet;
b3, when the current control is at the high level in the second period, the operation chip 3 continues to send a 4-bit data packet of the second period to the operation chip 2, at this time, the operation chip 2 has a 12-bit data packet, at the same time, the operation chip 2 connected in series transmits a 4-bit data packet of the second period to the operation chip 1, the operation chip 1 has an 8-bit data packet, the operation chip 1 transmits a 4-bit data packet of the second period to the main chip connected in series, the main chip has a 4-bit data packet, and thus, a total data of 12 bits is completed by the data transmitted from the operation chip 3 to the main chip.
Therefore, no matter the main chip transmits data towards the operation chip or the operation chip transmits data towards the main chip, which operation chip (for example, the operation chip 3) the data transmission comes from can be determined, the IP address of the operation chip does not need to be written, and therefore bidirectional unaddressed data transmission is achieved.
Fig. 7 is a schematic view of an electronic device according to a preferred embodiment of the invention. The electronic apparatus 1 is a device capable of automatically performing numerical calculation and/or information processing in accordance with a command set or stored in advance. The electronic device 1 may be a computer, or may be a single network server, a server group composed of a plurality of network servers, or a cloud composed of a large number of hosts or network servers based on cloud computing, where cloud computing is one of distributed computing and is a super virtual computer composed of a group of loosely coupled computers.
In the present embodiment, the electronic device 1 may include, but is not limited to, a memory 11, a processor 12, and a network interface 13, which are communicatively connected to each other through a system bus, and the memory 11 stores an unaddressed communication program 10 that can be executed on the processor 12. It is noted that fig. 7 only shows the electronic device 1 with components 11-13, but it is to be understood that not all shown components are required to be implemented, and that more or less components may be implemented instead.
The storage 11 includes a memory and at least one type of readable storage medium. The memory provides cache for the operation of the electronic device 1; the readable storage medium may be a non-volatile storage medium such as flash memory, a hard disk, a multimedia card, a card type memory (e.g., SD or DX memory, etc.), a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a Programmable Read Only Memory (PROM), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the readable storage medium may be an internal storage unit of the electronic apparatus 1, such as a hard disk of the electronic apparatus 1; in other embodiments, the non-volatile storage medium may also be an external storage device of the electronic apparatus 1, such as a plug-in hard disk provided on the electronic apparatus 1, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. In this embodiment, the readable storage medium of the memory 11 is generally used for storing an operating system and various application software installed in the electronic device 1, for example, the unaddressed communication program 10 in an embodiment of the present invention is stored. Further, the memory 11 may also be used to temporarily store various types of data that have been output or are to be output.
The processor 12 may be a Central Processing Unit (CPU), controller, microcontroller, microprocessor, or other data Processing chip in some embodiments. The processor 12 is generally used for controlling the overall operation of the electronic apparatus 1, such as performing control and processing related to data interaction or communication with the other devices. In this embodiment, the processor 12 is configured to execute the program code stored in the memory 11 or process data, for example, execute the unaddressed communication program 10.
The unaddressed communication program 10 is stored in memory 11 and includes computer readable instructions stored in memory 11 that are executable by processor 12 to implement the methods of the embodiments of the present application.
In one embodiment, the unaddressed communication program 10 when executed by the processor 12 implements the following steps:
a series connection step: the master chip and the m slave chips are connected in series through a signal beam to generate m slave chip numbers corresponding to the m slave chips arranged in sequence, wherein the signal beam comprises a flow control signal line, a clock signal line, a forward transmission signal line and a backward transmission signal line.
In the embodiment, the master chip and m slave chips arranged in sequence are arranged on the PCB, connecting a master chip with a slave chip and connecting two adjacent slave chips through a signal beam to form a communication link connected in series, automatically generating m corresponding slave chip numbers (for example, 1, 2, 3, 4.. m, m represents a positive integer) by m sequentially arranged slave chips, wherein the slave chip numbers are used for confirming the data position of communication transmission, namely, the specific position of the slave chip for receiving or sending data is determined, compared with the traditional chip which needs to compile the IP address of the chip to be transmitted before data transmission and then carry out data transmission, the method is time-consuming and troublesome, the invention automatically generates the serial number of the slave chip when the master chip and the slave chip are arranged in series, avoids coding the IP address of each slave chip, and has simple operation and high data transmission efficiency.
Specifically, the signal beam comprises a flow control signal line, a clock signal line, a forward transmission signal line and a backward transmission signal line, wherein the flow control signal line is represented by TEN and is used for controlling the transmission start and end of a frame of data on the forward transmission signal line or the backward transmission signal line; the clock signal line is represented by TCLK, and generates a pulse signal with periodicity; the forward signal line is represented by TXDA and is used for transmitting communication data from the master chip to the slave chip; the reverse signal line is denoted by RXDA and is used for transmitting communication data from the slave chip to the master chip.
It should be noted that the serial master-slave chips can complete bidirectional data transmission on the forward transmission signal line or the backward transmission signal line simultaneously, and in the data transmission process, the chips are connected in series to automatically generate slave chip numbers corresponding to m slave chips, so that the slave chips can be positioned to the slave chip positions where the data transmission is received or sent.
An acquisition step: and distributing data to m corresponding slave chips by the master chip in each period of the clock signal line based on the serial connection to obtain n data packets corresponding to the m slave chips arranged in sequence, wherein the data contained in each data packet is the same.
In this embodiment, the master chip distributes data to m corresponding slave chips in each cycle of the clock signal line, and data obtained by each slave chip is encapsulated into a corresponding data packet, where the data packet includes data distributed by the slave chip and a corresponding slave chip number. It should be noted that the data distributed to each slave chip by the master chip connected in series is the same, and the data obtained by the even distribution is packaged into a data packet with the corresponding slave chip number.
A verification step: when a certain slave chip receives a data packet sent by the master chip, whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located is verified.
For example, in an alternative embodiment, the main chip and the operation chip 1, the operation chip 2, and the operation chip 3 are included, the transmission of the periodic data packet is 4 bits, and the total data is 12 bits, then the mode of the forward transmission signal line (TXDA) that the main chip transmits data toward the operation chip is as follows:
a1, when the high level flow control is carried out, the main chip sends a 4-bit data packet of a period to the operation chip 1, and at the moment, the operation chip 1 has the 4-bit data packet;
a2, when the next period is in high level flow control, the main chip continuously sends a 4-bit data packet of one period to the operation chip 1, at the moment, the operation chip 1 has an 8-bit data packet, meanwhile, the operation chip 1 connected in series transmits a 4-bit data packet of one period to the operation chip 2, and the operation chip 2 has a 4-bit data packet;
a3, when the current control is in a high level flow control in another period, the main chip continuously sends a 4-bit data packet of one period to the operation chip 1, at this time, the operation chip 1 has a 12-bit data packet, meanwhile, the operation chip 1 connected in series transmits a 4-bit data packet of one period to the operation chip 2, the operation chip 2 has an 8-bit data packet, the operation chip 2 transmits a 4-bit data packet of one period to the operation chip 3, and the operation chip 3 has a 4-bit data packet, so that the data transmission of one total data of 12 bits is finished. Therefore, after the data transmission cycle is 3 times, the certain slave chip receives the data packet transmitted by the master chip, and therefore, the certain slave chip is determined to be the slave chip 3 by the data transmission.
A determination step: if the cycle number of the data packet transmitted to a certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located; determining the slave chip number corresponding to the slave chip where the data packet is received.
In an embodiment, when a master chip sends a data packet (e.g., data enclosure 4M) to a certain slave chip (e.g., slave chip 3), if the number of cycles for transmitting the data packet to the certain slave chip is equal to the slave chip number where the certain slave chip is located, that is, the master chip transmits the data packet 4M to the slave chip 3 after 3 cycles, it may be determined that the certain slave chip that finally receives the data packet is the slave chip 3 according to the serial communication link, so as to determine the specific position of the slave chip for this communication transmission, thereby implementing non-addressing communication.
Referring to FIG. 8, a block diagram of a preferred embodiment of the unaddressed communication process of FIG. 7 is shown.
In one embodiment, the unaddressed communication program 10 comprises: a concatenation module 101, an acquisition module 102, a verification module 103, and a validation module 104. The functions or operation steps implemented by the modules 101-104 are similar to those of the above-mentioned multi-chip unaddressed communication method, and are not described in detail here, for example, where:
the serial module 101 is configured to connect a master chip and m slave chips in series through a signal bundle to generate m slave chip numbers corresponding to the m slave chips arranged in sequence, where the signal bundle includes a flow control signal line, a clock signal line, a forward transmission signal line, and a backward transmission signal line;
the obtaining module 102 is configured to distribute, by the master chip, data to the m corresponding slave chips in each cycle of the clock signal line based on the serial connection, so as to obtain n data packets corresponding to the m slave chips arranged in sequence, where data included in each data packet is the same;
the verification module 103 is configured to verify whether the cycle number of the data packet transmitted to a certain slave chip is equal to a slave chip number of the certain slave chip when the certain slave chip receives the data packet sent by the master chip; and
a determining module 104, configured to determine that the number of cycles for transmitting the data packet to a certain slave chip is equal to a slave chip number of the certain slave chip; determining the slave chip number corresponding to the slave chip where the data packet is received.
Furthermore, the present invention also provides a computer-readable storage medium, which includes a non-addressed communication program, and when the non-addressed communication program is executed by a processor, the non-addressed communication program can implement the following operations:
a series connection step: connecting a master chip and m slave chips in series through a signal beam to generate m slave chip numbers corresponding to the m slave chips arranged in sequence, wherein the signal beam comprises a flow control signal line, a clock signal line, a forward transmission signal line and a backward transmission signal line;
an acquisition step: distributing data to m corresponding slave chips by the master chip in each period of a clock signal line based on serial connection to obtain n data packets corresponding to the m slave chips arranged in sequence, wherein the data contained in each data packet is the same;
a verification step: when a certain slave chip receives a data packet sent by the master chip, verifying whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located; and
a determination step: if the cycle number of the data packet transmitted to a certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located; determining the slave chip number corresponding to the slave chip where the data packet is received.
The specific implementation of the computer-readable storage medium of the present invention is substantially the same as the embodiments of the above-mentioned method and electronic device for quickly locating a bug, and will not be described herein again.
The technical principle of the present invention has been described above with reference to specific embodiments, which are merely preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. Other embodiments of the invention will occur to those skilled in the art without the exercise of inventive faculty, and such will fall within the scope of the invention.
Claims (10)
1. A multi-chip unaddressed communication method, comprising:
connecting a master chip and m slave chips in series through a signal beam to generate m slave chip numbers corresponding to the m slave chips arranged in sequence, wherein the signal beam comprises a flow control signal line, a clock signal line, a forward transmission signal line and a backward transmission signal line;
distributing data to m corresponding slave chips by the master chip in each period of a clock signal line based on serial connection to obtain n data packets corresponding to the m slave chips arranged in sequence, wherein the data contained in each data packet is the same;
when a certain slave chip receives a data packet sent by the master chip, verifying whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located;
if the cycle number of the data packet transmitted to a certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located; determining the slave chip number corresponding to the slave chip where the data packet is received.
2. The multi-chip unaddressed communication method according to claim 1, wherein the master chip distributes data to m corresponding slave chips in each cycle of the clock signal line, and data obtained from each slave chip is packaged into a corresponding data packet, where the data packet includes data distributed from a slave chip and a corresponding slave chip number.
3. The multi-chip unaddressed communication method according to claim 1, wherein the flow control signal line comprises a high level flow control and a low level flow control, and when the flow control signal line is in the high level flow control, the flow control signal line controls data transmission between the master chip and the slave chip; and
when the flow control signal line is in low-level flow control, data transmission between the master chip and the slave chip is invalid.
4. The multi-chip unaddressed communication method according to claim 3, wherein the flow control signal line controls the data transmission between the master chip and the slave chip comprises at least 1 clock cycle of the clock signal line formed at the rising edge and the falling edge;
when the clock signal line is at a rising edge, triggering the master chip to send data to the slave chip on a forward signal line, or triggering the slave chip to send data to the master chip on a backward signal line; and
when the clock signal line is at a falling edge, the slave chip receives corresponding data, or the master chip receives corresponding data.
5. The multi-chip unaddressed communication method according to claim 4, wherein the period of the clock signal line is calculated by the formula: T1/F
T is the clock period and F is the clock frequency.
6. The multi-chip unaddressed communication method of claim 1, further comprising:
when the master chip receives a data packet sent by a certain slave chip, whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located is verified.
7. An electronic device comprising a memory and a processor, the memory having stored therein a non-addressed communication program operable on the processor, the non-addressed communication program when executed by the processor implementing the steps of:
a series connection step: connecting a master chip and m slave chips in series through a signal beam to generate m slave chip numbers corresponding to the m slave chips arranged in sequence, wherein the signal beam comprises a flow control signal line, a clock signal line, a forward transmission signal line and a backward transmission signal line;
an acquisition step: distributing data to m corresponding slave chips by the master chip in each period of a clock signal line based on serial connection to obtain n data packets corresponding to the m slave chips arranged in sequence, wherein the data contained in each data packet is the same;
a verification step: when a certain slave chip receives a data packet sent by the master chip, verifying whether the cycle number of the data packet transmitted to the certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located;
a determination step: if the cycle number of the data packet transmitted to a certain slave chip is equal to the serial number of the slave chip where the certain slave chip is located; determining the slave chip number corresponding to the slave chip where the data packet is received.
8. The electronic device according to claim 1, wherein the master chip distributes data to the m corresponding slave chips in each cycle of the clock signal line, and data obtained from each slave chip is packaged into a corresponding data packet, and the data packet includes data distributed from the slave chips and corresponding slave chip numbers.
9. The electronic device of claim 1, wherein the current control signal line comprises a high level current control and a low level current control, and when the current control signal line is in the high level current control, the current control signal line controls data transmission between the master chip and the slave chip; and
when the flow control signal line is in low-level flow control, data transmission between the master chip and the slave chip is invalid.
10. A computer-readable storage medium, comprising an unaddressed communication program that, when executed by a processor, performs the steps of the multi-chip unaddressed communication method of any of claims 1-6.
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| CN202010474223.7A CN111625492A (en) | 2020-05-29 | 2020-05-29 | Multi-chip unaddressed communication method, electronic device, and medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112557882A (en) * | 2021-02-19 | 2021-03-26 | 深圳市明微电子股份有限公司 | Chip initial address self-adaptive detection method, device, equipment and storage medium |
| CN113594077A (en) * | 2021-07-22 | 2021-11-02 | 重庆双芯科技有限公司 | Chip positioning method of multistage chip series system and multistage chip series system |
-
2020
- 2020-05-29 CN CN202010474223.7A patent/CN111625492A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112557882A (en) * | 2021-02-19 | 2021-03-26 | 深圳市明微电子股份有限公司 | Chip initial address self-adaptive detection method, device, equipment and storage medium |
| CN112557882B (en) * | 2021-02-19 | 2021-05-28 | 深圳市明微电子股份有限公司 | Chip initial address self-adaptive detection method, device, equipment and storage medium |
| CN113594077A (en) * | 2021-07-22 | 2021-11-02 | 重庆双芯科技有限公司 | Chip positioning method of multistage chip series system and multistage chip series system |
| CN113594077B (en) * | 2021-07-22 | 2024-03-08 | 重庆双芯科技有限公司 | Multistage chip serial system chip positioning method and multistage chip serial system |
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