JPH11218787A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a drift in level in one frame by constituting TFTs constituting a peripheral circuit so that hole mobility or electron mobility has values in specific ranges. SOLUTION: Photoresist is formed by using a photomask to form a mask in an N channel type thin-film transistor(NTFT) area, thereby forming a P channel type thin-film transistor(PTFT). For the PTFT, a source and a drain are formed by self-alignment by the ion injection of boron into source and drain areas 410, 412, and 415 by a dosage of 1×10<15> cm<-3> . To manufacture the NTFT, a source and a drain for the NTFT are formed by adding phosphorus as impurities by ion injection by 1×10<15> cm<-3> . Thus, the TFT has 10 to 200 cm<2> /Vsec hole mobility (μh) and 15 to 300 cm<2> /Vsec electron mobility (μe).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal electro-optical device using thin film transistors (hereinafter referred to as TFTs) as driving switching elements.

[0002]

2. Description of the Related Art Conventionally, an active matrix type liquid crystal electro-optical device using a TFT has been known. in this case,
An amorphous or polycrystalline semiconductor is used for the TFT, and only one of P-type and N-type TFTs is used for one pixel. That is, generally, N
A channel type TFT (referred to as NTFT) is connected to the pixel in series. FIG. 2 shows a typical example.

FIG. 2 schematically shows an equivalent circuit of a liquid crystal electro-optical device. Reference numeral 22 denotes a liquid crystal portion of one pixel. An NTFT 21 is provided in series with it. Such pixels are arranged in a matrix. Generally, it has a very large number of pixels of 640 × 480 or 1260 × 960, but in this drawing, a 2 × 2 matrix arrangement is simply drawn in the same meaning. A signal is applied to each pixel from the peripheral circuits 26 and 27, a predetermined pixel is selectively turned on, and the other pixels are turned off. Accordingly, it is possible to realize a liquid crystal electro-optical device having a large contrast even in the case of a high duty.

[0004]

However, when actually manufacturing such a liquid crystal electro-optical device, a TFT
, The input voltage V _LC 20 for the liquid crystal
(Liquid crystal potential) often does not become "1" (High) when it should be "1" (High), and sometimes does not become "0" (Low) when it should be "0" (Low). . This is because the TFT, which is a switching element for applying a signal to a pixel, is in an asymmetric state when the TFT is in an ON / OFF state.

The liquid crystal 22 is inherently insulating in its operating condition, and has a liquid crystal potential (V _LC ) when the TFT is off.
Is in a floating state. Since the liquid crystal 22 is a capacitor in an equivalent circuit, _VLC is determined by the electric charge stored therein. This charge leaks because the resistance R _LC 24 of the liquid crystal is relatively small, or dust or ionic impurities exist in the liquid crystal.

Further, R _GS 25 is applied between the gate electrode and the input / output terminal of the TFT due to the pinhole of the gate insulating film of the TFT 21.
Occurs, the charge leaks therefrom, and the V _LC 20 is in an incomplete state.

For this reason, 200,000 to 500 in one panel
In a liquid crystal display device having ten thousand pixels, TFTs also exist, so that the above-described problem occurs and a high yield cannot be achieved. In particular, as the liquid crystal 22, a TN (twisted nematic) liquid crystal is generally used. For the alignment of the liquid crystal, a rubbed alignment film is provided on each electrode. A weak dielectric breakdown occurs in the TFT due to static electricity generated by the rubbing process, causing leakage between adjacent pixels or adjacent conductors, and weak leakage due to weak gate insulating film. Resulting in. In an active matrix type liquid crystal electro-optical device,
It is extremely important to keep the liquid crystal potential at the same level as the initial value during one frame to maintain a predetermined level. However, in reality, there are many defects and it is not always the case.

If the liquid crystal material is a ferroelectric liquid crystal, it is necessary to increase the injection current. For this purpose, there is a drawback that the current margin must be increased by increasing the element size of the TFT.

According to the present invention, there is a problem caused by the asymmetry of the state when the driving element for driving each pixel of the display device is turned on and off, that is, the potential of the display portion is fixed stably to "1" and "0". However, it is an object of the invention to solve the problem that the level drifts during one frame.

In addition, the present invention proposes a liquid crystal electro-optical device having a function of compensating for the occurrence of a malfunction of a large number of TFTs in one liquid crystal electro-optical device (mainly, a defect due to short-circuit or leak between the source and drain). Things.

[0011]

The present invention relates to a liquid crystal electro-optical device in which a plurality of pixels having a matrix configuration are provided on a substrate, wherein each pixel electrode has a P-channel thin film transistor and an N-channel thin film transistor. A plurality of sets of complementary thin-film transistors are provided in a complementary manner, input / output terminals of the plurality of complementary thin-film transistors are connected in series, one of the input / output terminals is connected to the pixel electrode, and the other is connected to the first signal. A liquid crystal electro-optical device, wherein all the gate electrodes of the plurality of complementary thin film transistors are connected to a second signal line.

Here, the complementary type thin film transistor is N
One of the input / output portions of the channel type thin film transistor (hereinafter referred to as NTFT) is connected to one of the input / output portions of the P channel type thin film transistor (hereinafter referred to as PTFT), and the gate electrodes of the P and N channel type thin film transistors are Complementary thin film transistors (hereinafter referred to as C / TF) which are connected to each other, and these connected portions serve as source, drain and gate electrodes which are input / output.
T).

A liquid crystal electro-optical device provided with a plurality of pixels having a matrix configuration on a substrate, wherein each pixel electrode has a plurality of P-channel thin film transistors and a plurality of N-channel thin film transistors, The input / output terminals of the source and drain regions of the plurality of P-channel thin film transistors are connected in series, one of the input / output terminals is connected to the pixel electrode, and the other is connected to a first signal line, The input and output terminals of the source and drain regions of the N-channel type thin film transistor are connected in series, one of the input and output terminals is connected to the pixel electrode, the other is connected to the same first signal line, and all of the thin film transistors are connected. Wherein the gate electrode is connected to the same second signal line.

FIG. 1 shows a typical example of the present invention as a circuit.
2 × driven by the peripheral circuits 1 and 2 shown in FIG.
2 shows an example of an active matrix type liquid crystal electro-optical device. In the figure, two PTFTs and two NTFTs are connected in a complementary configuration corresponding to one pixel portion 3. PTFT out of 4 TFTs
The source and the drain region are electrically connected to the NTFT and constitute a set of C / TFTs. The two C / TFTs have an input / output unit electrically connected in series to the pixel electrode, and one input / output unit 4 is connected to a matrix-arranged signal line V _DD1 and the other input / output unit 5 Is connected to the pixel electrode 6 of the liquid crystal.

The gate electrodes of these four TFTs are connected to the same signal line _{VGG1 so} that one pixel portion is provided with two sets of C / TFTs.

An active matrix type liquid crystal electro-optical device is constituted by arranging pixel portions having TFTs having such a configuration in a matrix.

With such a configuration, the PT
The potential of the pixel portion 3 when the C / TFT including the FT and NTFT is turned on and off is fixed to “1” and “0” sufficiently and stably, so that the level does not drift during one frame. A display device can be obtained.

In the present invention, such a C / TFT
Are provided in series, so that even if some of the four TFTs malfunction (specifically, short-circuit or leak between the source and drain), the other TFTs can compensate for the operation. It is. That is, since the C / TFT is provided in series with the pixel, even if a part of the C / TFT is always in a conductive state, the remaining TFT turns on and off the pixel.
This is because FF can be controlled.

Also, since they are arranged in series, OFF
A small amount of leakage of a small current in the state occurs due to twice the resistance of a normal TFT, and the potential of the pixel portion 3 can be fixed to “1” and “0” more stably. It became.

FIG. 3 shows another example of the present invention.
FIG. 3 also shows an example in which a 2.times.2 matrix is arranged for description, similarly to FIG.

In FIG. 1, two PTFTs and two NTFTs are connected in a complementary configuration corresponding to one pixel portion 3. That is, the source and drain regions of two PTFTs of the four TFTs are connected in series, and the source and drain regions of two NTFTs are also connected in series. Such PTFT group and NTFT
The source and drain regions of the group are electrically connected,
A set of C / TFTs is configured. The C / TFT has an input / output section electrically connected to the pixel electrode in series. One input / output section 30 is connected to a matrix-arranged signal line V _DD1 and the other input / output section 31 is a liquid crystal display. Are connected to the pixel electrodes 6.

The gate electrodes of the four TFTs are connected to the same signal line _{VGG1 so} that one pixel portion is provided with a set of C / TFTs composed of four TFTs.

As described above, in the present invention, a plurality of TFTs are provided in series with respect to the pixel electrode, and individually or as a whole functions as a C / TFT.
This is characterized in that the function of compensating for the operation failure is realized, and the present invention is not limited to only the above example, but can be realized even if a plurality of TFTs are provided.

In the example of FIG. 1, PTFT and N
Even if the relative positional relationship with the TFT is changed, exactly the same function can be realized, and the layout of the liquid crystal electro-optical device can be given a degree of freedom.

[0025]

Embodiment 1 This embodiment is a liquid crystal electro-optical device corresponding to the equivalent circuit shown in FIG. 3, in which two PTFTs and two NTFTs are provided for one pixel.

FIG. 4 shows a top view and a cross-sectional view of the TFT, and FIG. 5 shows a manufacturing process of the TFT used in this embodiment.
These drawings are drawn for explanation, are different from actual dimensions of the apparatus, and details are omitted for explanation.

First, the steps of manufacturing the PTFT 41 and the NTFT 40 will be described with reference to FIG. Since the basic manufacturing method of the PTFT and the NTFT is the same except for the type of impurities to be introduced, the description will be made with reference to FIG.

First, a silicon oxide film 51 as a blocking layer having a thickness of 1000 to 3000 mm is formed on a glass substrate 50 such as AN glass or Pyrex glass which can withstand a heat treatment at about 600 ° C. by using a magnetron RF (high frequency) sputtering method. Prepared. The process conditions are 100% oxygen atmosphere, deposition temperature 150 ℃,
The output was 400 to 800 W and the pressure was 0.5 Pa. Quartz or single crystal silicon is used for the target, and the film formation speed is 30 to 1000.
/ Min. Further, a silicon film 52 is further formed on the
VD (decompressed gas phase) method, sputtering method or plasma CVD
It was formed by a known method, and the pattern of (A) was obtained through a known patterning step such as photolithography.

When this silicon film is formed by a reduced pressure gas phase method, 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature,
For example, disilane (Si ₂ H ₆ ) or trisilane (Si ₃
H ₈ ) was supplied to a CVD apparatus to form a film. The reactor pressure is 3
0 to 300 Pa. The deposition rate was 50 to 250 ° / min. The threshold voltage of the NTFT and PTFT (V
In order to control (th) substantially the same, boron may be added during film formation at a concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ using diborane.

When this silicon film is obtained by sputtering, the back pressure before sputtering is set to 1 × 10 ⁻⁵ Pa or less,
Using single crystal silicon as the target, hydrogen
Performed in an atmosphere mixed with ~ 80%. For example, argon 20
% And hydrogen 80%. Deposition temperature is 150 ° C, frequency is 13.5
The power was set to 6 MHz and the sputter output was set to 400 to 800 W. Pressure is 0.5 Pa
Met.

When the silicon film is obtained by the plasma CVD method, the film forming temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) can be used as a reactive gas. Such a reactive gas was introduced into a PCVD apparatus, and a high-frequency power of 13.56 MHz was applied to form a film.

The coatings formed by these methods are:
It is preferable that oxygen is not more than 7 × 10 ²⁰ cm ⁻³ . If the oxygen concentration is high, it is difficult to crystallize the semiconductor layer, so that the temperature of the thermal annealing must be increased or the thermal annealing time must be increased. If the amount is too small, the leakage current in the off state increases when the semiconductor layer is irradiated with light by the backlight used in the liquid crystal electro-optical device.
Therefore, in the range of 4 × 10 ¹⁹ to 4 × 10 ²¹ cm ⁻³ , crystallization can be easily performed by thermal annealing at a medium temperature (600 ° C. or lower). For example, impurities in the coating used in this example were measured by SIMS (secondary ion mass spectrometry). As a result, an oxygen amount of 8 × 10 ¹⁸ cm ⁻³ and a carbon of 3 × 10 ¹⁶ cm ⁻³ were obtained. Hydrogen was 4 × 10 ²⁰ cm ⁻³ , which was 1 atomic% as compared with silicon 4 × 10 ²² cm ⁻³ .

In order to further promote crystallization of the source and drain regions, the oxygen concentration is set to 7 × 10 ²⁰ cm ⁻³ or less, preferably 7 × 10 ¹⁹ cm ⁻³ or less, and the TFT constituting the pixel is formed. It is also effective to weaken the sensitivity to light by adding oxygen, carbon or nitrogen to only a part of the channel forming region by ion implantation so as to have a concentration of 5 × 10 ^{19 to} 5 × 10 ²¹ cm ^−3. . In this case, especially in the TFT constituting the peripheral circuit, the mixing of oxygen can be reduced, the carrier mobility can be increased, the high-frequency operation can be easily performed, and the TFT around the pixel can be easily operated. The switching TFT can reduce the leak current in the off state.

The film formed by these methods contains oxygen of 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ^−3.
It is preferable to have the following concentration. This is because, when crystallization is performed under typical crystallization conditions, the degree of crystallization can be promoted.

Thus, the amorphous silicon film is
After manufacturing to a thickness of 0-3000Å, for example 1500Å, 450-70Å
Heat treatment was performed at a medium temperature in a non-oxide atmosphere at a temperature of 0 ° C. for 12 to 70 hours. For example, it was kept at a temperature of 600 ° C. in a nitrogen or hydrogen atmosphere. Since an amorphous silicon oxide film is formed on the surface of the substrate below the silicon film, no specific nucleus is present in this heat treatment, and the whole is annealed uniformly. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein. By this annealing,
The silicon film shifts from an amorphous structure to a highly ordered state, and a part of the silicon film exhibits a crystalline state. In particular, a region having a relatively high order at the time of forming a silicon film is particularly likely to be crystallized to be in a crystalline state. However, since the silicon existing between these regions is bonded to each other, silicon mutually pulls each other. When the crystal is measured by laser Raman spectroscopy, a peak shifted to a lower frequency side than a single crystal silicon peak of 522 cm ^-1 is observed. Calculated from its half-width, the apparent particle size is 50 to 500 mm, which is like a microcrystal.In fact, there are many regions with high crystallinity and a cluster structure. Was able to form a film having a semi-amorphous structure in which silicon mutually bonded (anchored).
As a result, this coating is substantially grain boundary (G
B). Carriers can easily move from one cluster to another through anchored locations, resulting in higher carrier mobility than so-called GB polycrystalline silicon. That is,
Mobility (μh) = 10-200 cm ² / Vsec, electron mobility (μ
e) = 15-300 cm ² / Vsec is obtained.

On the other hand, when the coating is polycrystallized by high-temperature annealing at a temperature of 900 to 1200 ° C. instead of annealing at medium temperature as described above, segregation of impurities in the coating by solid phase growth from nuclei. In GB, impurities such as oxygen, carbon, and nitrogen are increased in GB, and the mobility in the crystal is large. However, a barrier is formed in GB to hinder the movement of carriers there. As a result, it is difficult to obtain a mobility of 10 cm ² / Vsec or more.

That is, in the embodiment of the present invention, as described above, a silicon semiconductor having a semi-amorphous or semi-crystalline structure is used. Further, a silicon oxide film is formed thereon as a gate insulating film 420 to have a thickness of 500 to 2,000 (for example, 1000).
Å formed. This was performed under the same conditions as those for forming the silicon oxide film 51 as the blocking layer. A small amount of fluorine may be added during this film formation. Thereafter, a metal film made of aluminum was formed on the upper side. This was patterned using a photomask to form gate electrodes 413 and 416. For example, a channel length of 10 μm and a thickness of 0.3 μm were formed to obtain the shape shown in FIG. The extended portion of the gate electrode simultaneously forms the electrode wirings 43 and 44 in the Y direction in the top view of FIG.

Although aluminum was used as the gate electrode, other metal materials, such as molybdenum, chromium, and doped silicon film, can be used. When aluminum is used as the gate electrode as in this embodiment, the periphery of the gate electrode can be anodized, and the oxide film can be used to form contact holes for the source and drain region electrodes in a self-aligned manner. In addition, a power supply point can be provided near the channel region, and the influence of the resistance component in the source and drain regions can be reduced.

Next, referring to FIG. 5C, a photoresist is formed using a photomask, a mask is formed on the NTFT region, and a PTFT is first manufactured.

In the case of PTFT, boron is added to the source and drain regions 410, 412, and 415 at 1 × 10 ¹⁵ cm ^-3.
Was formed in a self-aligned manner by ion implantation using the gate electrode as a mask.

When an NTFT is manufactured, a source and a drain for the NTFT can be formed by adding phosphorus as an impurity in an amount of 1 × 10 ¹⁵ cm ⁻³ by ion implantation. In this embodiment, since the PTFT 41 and the NTFT 40 are arranged in parallel as shown in FIG.
The FT region may be masked with a photoresist or the like.

This ion implantation is performed by the gate insulating film 42.
0. However, in FIG. 5B, the silicon oxide on the silicon film may be removed using the gate electrodes 413 and 416 as a mask, and then boron and phosphorus may be directly ion-implanted into the silicon film.

Next, annealing was performed again at 600 ° C. for 10 to 50 hours. Then, the impurity region drains 400, 402, and 405 of the NTFT of FIG.
10, 412 and 415 impurities are activated to make N ⁺ , P ⁺
It was produced as. Channel formation regions 411 and 401 are formed below the gate electrode 413, and channel formation regions 414 and 404 are formed below the gate electrode 416 as semi-amorphous semiconductors.

In this way, the C / TFT shown in FIG. 4 can be manufactured without applying any temperature to 700 ° C. or more, even though it is a self-aligned system. for that reason,
It is not necessary to use an expensive substrate such as quartz as a substrate material, and this is a process that is extremely suitable for the large-pixel liquid crystal electro-optical device of the present invention.

Thermal annealing was performed twice in FIGS. 5A and 5C.
However, the annealing in FIG. 5 (A) is omitted due to the required characteristics.
Both may be combined by the annealing of FIG. 5 (C) to shorten the manufacturing time.

Before or after the annealing step of FIG. 5C, the surfaces of gate electrodes 413 and 416 are anodized to form aluminum oxide insulating film 53. Next, in FIG. 5D, an interlayer insulator 418 was formed as a silicon oxide film on the upper surface by the above-described sputtering method. This silicon oxide film may be formed by an LPCVD method or an optical CVD method. For example, it was formed to a thickness of 0.2 to 0.4 μm. Thereafter, a window 54 for an electrode was formed using a photomask. The window is formed using a photomask. At this time, a contact hole is formed by aligning the end of the window with the aluminum oxide film 53, and the distance between the power supply point to the impurity region and the channel formation region is formed. Can be shortened.

Further, the whole was formed by sputtering aluminum, and a lead 45 was formed using a photomask. Further, as shown in FIG. 4A, the four TFTs are of a complementary type, and their output terminals 405 and 415 are connected to the transparent electrode 6 which is one pixel electrode of the liquid crystal device by a contact 31.
In order to connect to ITO (indium
(A tin oxide film). It was etched using a photomask to form the pixel electrode 6. The ITO was deposited at room temperature to 150 DEG C. and was achieved with oxygen at 200 DEG to 400 DEG C. or with air annealing.

As described above, the two PTFTs 41 and 2
One NTFT 40 and the electrode 6 of the transparent conductive film were formed on the same glass substrate 50. The characteristics of such TFTs are abbreviated in Table 1 below.

[0049]

[Table 1]

By using such a semiconductor, it was possible to produce a large mobility in a TFT which was generally considered impossible. Therefore, for the first time, a complementary TFT could be configured as an active element of the liquid crystal electro-optical device shown in FIG.

In this embodiment, the structure of the TFT is as follows:
Although the description has been given using the planar type TFT, the present invention is not particularly limited to this structure, and the effects of the present invention can be realized with a TFT having another structure.

In FIG. 4, V _DD1 and V _DD2 are _arranged in the Y-axis direction.
(Hereinafter also referred to as Y line) 43, 4
4 was formed. In the X-axis direction, V _GG1 and V _GG2 and wirings (hereinafter also referred to as X-rays) 45 and 46 in the X-axis direction were formed.
FIG. 4A is a plan view, and FIG.
See (B). FIG. 4C shows a vertical cross-sectional view taken along line BB ′. 2
The two NTFTs 40 and the two PTFTs 41 are provided at the intersection of the Y line V _DD1 and the X line V _GG1 to form a C / TFT. The other pixels also have a matrix configuration using C / TFTs having the same configuration as shown in FIG. NTFT40, PTFT4 constituting C / TFT
Reference numeral 1 denotes a source and a drain 405 and 415 connected to a transparent conductive film 6 as a pixel electrode via a contact 31, and the other source and drain regions 400 and 410 are one signal line having a matrix configuration by the contact 30. It is connected to a certain X-ray 45. NTFT,
All the gate electrodes of the PTFT are connected to one of the signal lines, ie, the Y line 43 aluminum wiring. That is, two PTFTs are connected in series between the pixel electrode and the Y-line signal line 43, and similarly, two NTFTs are connected in series between the pixel electrode and the Y-line signal line 43, and these four TFTs are connected.
The C / TFT could be constituted by FT.

Thus, one pixel was constituted by the transparent conductive film 6 and the C / TFT composed of four TFTs between (inside) the two X-rays and the Y-rays. By repeating such a structure left, right, up and down, 2
One example of a × 2 matrix or an expanded version of 64
It has become possible to produce a liquid crystal electro-optical device with a large pixel size of 0 × 480 or 1280 × 960.

FIG. 4 shows the structure of one substrate for holding liquid crystal in a liquid crystal electro-optical device. An alignment film and an alignment process are performed on a transparent conductive film of a liquid crystal driving element provided on a substrate whose configuration is shown in FIG. 4, and furthermore, a fixed distance is provided between this substrate and a substrate having another pixel electrode. , And arranged in a known manner. During this time, a liquid crystal material was injected to complete the liquid crystal electro-optical device according to the present embodiment. If TN liquid crystal is used as the liquid crystal material, it is necessary to set the distance between the substrates to about 10 μm and to form an alignment film on both transparent conductive films by rubbing.

When a ferroelectric liquid crystal is used as the liquid crystal material, the operating voltage is set to ± 20 V, and the cell interval is set to 1.5 to
The thickness may be 3.5 μm, for example, 2.3 μm, and an rubbing treatment may be performed by providing an alignment film only on the counter electrode.

In the case of using a dispersion type liquid crystal or a polymer type liquid crystal, an alignment film is not required, and in order to increase the switching speed, the operating voltage is set to ± 10 to ± 15 V, and the cell interval (a pair of the liquid crystal sandwiching pair). The distance between the substrates was reduced to 1 to 10 μm. In particular, when a dispersion type liquid crystal is used, since a polarizing plate is not required, the amount of light can be increased both in a reflection type and in a transmission type. Since the liquid crystal has no threshold, a large contrast can be obtained by using a driving element (C / TFT) in which a clear threshold voltage is defined, which is a feature of the C / TFT of the present invention. Bad interference with the neighboring pixels) could be eliminated.

In the present embodiment, semi-amorphous or semi-crystal was used as the semiconductor of the device. However, it goes without saying that a semiconductor having another crystal structure may be used for the same purpose.

In this embodiment, a liquid crystal display device is used as an example of a liquid crystal electro-optical device. However, a voltage is applied to a pixel electrode to drive a pixel in the display device to perform some display operation. Needless to say, the C / TFT of the present invention can be used for the element that performs the above.

An advantage of the present invention is that a plurality of TFs are provided in one pixel.
T is provided in a complementary configuration, and the electrode 6 constitutes a liquid crystal potential V _LC , which means that PTFT is on and NTFT is off, or PTFT is off and N
That is, the level of the TFT is fixed to either ON or ON.

Hereinafter, the C / TFT of this embodiment will be described with reference to FIG.
The operation principle of will be described. By applying a signal voltage to the pair of signal lines V _DD1 , V _DD2 , V _GG1 , and V _GG2 shown in FIG. 3, a voltage is applied to the pixel portion, and the liquid crystal electro-optic effect is developed. FIG. 6 shows drive waveforms of signal voltages applied to these four signal lines and the counter electrode on the other substrate in order to apply a voltage to the liquid crystal present at point A (the pixel located at the intersection of V _DD1 and V _GG1 ). The chart is shown. As can be seen from FIG. 6, what is shown in FIG. 3 is a 2 × 2 matrix, so that one frame is divided into two. Further, the voltage actually applied to the liquid crystal 3 in this case is shown as a block A voltage. FIG. 6 shows only the ON and OFF states, but in order to perform a gradation display, the signal voltage applied to V _DD1 or V _DD2 should be changed to a signal voltage waveform corresponding to the strength. Good. For example, in the case of FIG. 3, if it is desired to increase the transmittance of the liquid crystal at point A, it is _sufficient to apply a high signal voltage in accordance with the transmittance of the liquid crystal of V _DD1 in FIG. If it is desired to reduce the rate, a low signal voltage may be applied. (That is, gradation display can be performed by applying voltages of V _DD1 and V _DD2 .)

[0061] On the other hand, the signal voltage applied to the V _GG1, V _GG2 must be greater than the threshold voltage V _th of the _{C / TFT (V GG »V th} ). Further, as shown in FIG. 6, applying a V _OFFSET voltage, which can be said to be a threshold voltage at which the liquid crystal reacts to the applied voltage, at a negative potential to the counter electrode at a negative potential, requires the transmittance of the liquid crystal and the applied voltage to the liquid crystal. This is useful when gradation display is performed by utilizing the relationship.

In such driving, when one of the two TFTs constituting the PTFT 41 or the NTFT 40 malfunctions due to a short circuit or a leak, the applied voltage of V _DD1 or V _DD2 is usually V _GG1 or V _GG1.
Irrespective of the selection signal of _GG2 , it is applied to the liquid crystal pixel portion as it is, and it is always in the ON state (or the OFF state). V _DD1 or V _DD
By providing two PTFTs and NTFTs in series between _DD2 and the pixel electrode, even if the source and drain of one TFT are short-circuited, selection and non-selection can be controlled by the other TFT. And helped to improve the yield of the liquid crystal electro-optical device.

At the same time, these four TFTs are C / T
The FT configuration is employed, which eliminates the conventional problem of instability of the liquid crystal potential, can fix the liquid crystal potential, and can exhibit a stable liquid crystal electro-optic effect.

[0064] Example 2 This example, the plan view in FIG. 7 (A), the A-A FIG. 7 ^(B), the cross-sectional view of FIG. 7 (C) ^B-B, of 1 is a liquid crystal electro-optical device having a configuration shown in a cross-sectional view.

The equivalent circuit of the present embodiment is as shown in FIG. 1. A switching element portion is constituted by four TFTs, and one PTFT and NTFT are formed as a C / TFT.
The C / TFT is provided in series between two sets of V _DD1 and V _DD2 and the pixel electrode 6.

In the present embodiment, the transparent conductive film 6 which is the pixel electrode in the first embodiment is manufactured, and then the transparent conductive film 6 is formed first and then patterned to form the pixel electrode 6. What you get. At this time, an electrode portion 703 for connecting one set of C / TFT and the other C / TFT was also provided.

In this manner, when the transparent conductive film, for example, ITO is patterned, the lower element may be destroyed.
The structure of the present invention can be obtained in a process that does not break the wiring.

In this embodiment, two PTFTs 7
The positions of the NTFTs 1 and 72 and the two NTFTs 73 and 74 are electrically equivalent at any position, exhibiting the same effect as that of the first embodiment, and at the same time, are arranged at arbitrary positions according to the necessity in the TFT manufacturing process. be able to.

Further, the structure of the element is an inverted stagger type TF.
As T, in the PTFTs 71 and 72, the gate electrodes 75 and 76 and the source and drain regions 700, 702 and 7
04 and 706 are provided on the gate insulating films 708 and 709.

In this embodiment, as these semiconductor layers, P
A semiconductor layer produced by subjecting a silicon semiconductor layer produced by a CVD method to thermal annealing to promote crystallization was used.

Although the NTFT is not shown, the PTFT
Although it has the same structure as the FT and is provided beside the PTFT, the PTFT and the NTFT can be arranged in an arbitrary positional relationship without particular limitation.

The other manufacturing steps and the like are the same as those in the first embodiment, and a description thereof will be omitted.

In the present invention, the TFTs are arranged in series because a failure mode of the TFT is assumed to be a short circuit between the source and the drain or a leak. In order to guarantee the operation, it is necessary to electrically disconnect the gate electrode of the defective TFT from the signal line. Therefore, if the gate electrode is disconnected in series, all the TFTs that operate with the gate electrode cannot operate. Cannot handle, in this case multiple C /
By providing the TFTs in parallel, when a malfunctioning TFT occurs, the gate electrode of the malfunctioning TFT can be easily electrically disconnected from the signal line.

However, in this case, it is necessary to supply a power supply line independently to the source and drain regions, and it is necessary to devise a layout pattern.

[0075]

By adopting such a configuration, P
ON / OFF of C / TFT consisting of TFT and NTFT
It is possible to obtain a display device in which the potential of the pixel portion 3 at the time is fixed to “1” and “0” sufficiently and stably, and the level does not drift during one frame.

In the present invention, such a C / TFT
Are provided in series, so that even if some of the four TFTs malfunction (specifically, short-circuit or leak between the source and drain), the other TFTs can compensate for the operation. It is. That is, since the C / TFT is provided in series with the pixel, even if a part of the C / TFT is always in a conductive state, the remaining TFT turns on and off the pixel.
This is because FF can be controlled.

Also, since they are arranged in series,
A small amount of leakage of a small current in the state occurs due to twice the resistance of a normal TFT, and the potential of the pixel portion 3 can be fixed to “1” and “0” more stably. It became.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram when the configuration of the present invention is assembled in a 2 × 2 matrix.

FIG. 2 shows a conventional example not using the present invention.

FIG. 3 shows an example of an embodiment of the present invention.

FIG. 4 shows a top view and a cross-sectional view of the first embodiment.

FIG. 5 illustrates an example of a manufacturing process diagram of a TFT.

FIG. 6 shows an example of a signal for driving a C / TFT.

FIG. 7 shows a top view and a cross-sectional view of the second embodiment.

[Explanation of symbols]

 6 Pixel electrode part 40 P-channel thin film transistor (PTFT) 41 N-channel thin film transistor (NTFT) 400, 402, 405 Source / drain electrode 410, 412, 415 Source / drain electrode 413, 416 Gate electrode

Claims (3)

[Claims] 1. A pixel having a pixel electrode, a switching element connected to the pixel electrode, and a peripheral circuit for driving the pixel electrode on a substrate, wherein a TFT constituting the peripheral circuit has a hole mobility. (Μ
h) is 10 to 200 cm ² / Vsec or electron mobility (μe) is 15
A display device characterized by being at most 300 cm ² / Vsec. 2. A semiconductor device comprising: a pixel electrode on a substrate; a switching element connected to the pixel electrode; and a peripheral circuit for driving the pixel electrode, wherein the switching element includes a plurality of TFTs connected in series.
A display device, comprising: a carrier mobility of a TFT of the switching element is smaller than a carrier mobility of a TFT constituting the peripheral circuit. 3. The display device according to claim 2, wherein the plurality of TFTs use only one of P-type and N-type TFTs.