JPH11214850A - Printed wiring board and production thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a production method for printed wiring board in which fine patterning is effected while decreasing the number of steps by employing dry etching or sputtering. SOLUTION: The production method for printed wiring board comprises a step for forming a wiring pattern 2 on the surface of a core material 1, a step, for forming an insulation layer 3 of organic resin mixed with an inorganic filler 5 on the surface of the core material 1 including the wiring pattern 2, a step for making a contact hole 8 reaching the wiring pattern 2 in the insulation layer 3, a step for roughening the surface of the insulation layer 3 by dry etching, a step for forming a conductive film 13 for electroplating on the surface of the insulation layer 3 containing the inorganic filler by vacuum deposition, and a step for forming a conductor film 14 on the conductive film 13 by electroplating. In other words, a fine patterned printed board is produced while decreasing the number of steps by employing dry etching or sputtering.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a printed circuit board such as a so-called multilayer printed circuit board (built-up board) on which electronic components such as bare chips are mounted, and a printed circuit board.

[0002]

2. Description of the Related Art In general, in electronic equipment, a printed circuit board for mounting circuit elements such as various electronic parts is used. However, in recent years, devices and circuit elements have become smaller and more highly integrated. Due to the demand, miniaturization of the printed circuit board itself and miniaturization of the wiring pattern are required. At present, the line width and the line-to-line width of the wiring pattern of the printed circuit board are each on the order of about 100 μm. Something of the order is required. Here, a conventional method of manufacturing a printed circuit board will be described with reference to FIGS.

First, as shown in FIG. 8A, a predetermined wiring pattern 2 is formed by forming a copper foil or the like on the surface of an insulating core material 1 made of, for example, a glass epoxy resin and patterning the same. Form. At present, the line width L1 and the line width L2 of the wiring pattern 2 are at least 1 respectively.
The thickness W1 is about 20 μm. The surface of the wiring pattern 2 is oxidized and blackened to increase the degree of adhesion to the epoxy resin layer in a later step.

Next, as shown in FIG. 8B, a first insulating layer 3 is screen-printed on the entire surface of the core material 1 and a second insulating layer 4 is printed as shown in FIG. Etc. are sequentially applied and formed. FIG. 9 is FIG.
FIG. 3D is an enlarged view of a portion A in FIG.
The main material of this material is, for example, an epoxy resin. As shown in FIG. 9, the first insulating layer 3 has a particle diameter L3 of about 1 μm as an inorganic filler in order to improve insulation properties.
The SiO ₂ filler 5 is mixed in an appropriate amount, and its thickness T1 is set to about 50 μm (see FIG. 8C). The second insulating layer 4 has a particle diameter L4 of about 10 as an inorganic filler to be dissolved in a roughening step described later.
An appropriate amount of the CaCO ₃ filler 6 of μm is mixed in, and its thickness T2 is set to about 20 μm.

[0005] Next, as shown in FIG. 8 (D), a connection hole 8 is penetrated through the first and second insulating layers 3 and 4 by using, for example, a carbon dioxide laser beam 7 in an electric connection portion. It is selectively formed and the internal wiring pattern 2 is exposed. The diameter D1 of the hole 8 is about 100 μm. next,
As shown in FIG. 8E, an alkaline roughening solution, for example, a potassium permanganate solution is applied to the surface of the second insulating layer 4 so that the CaCO ₃ inorganic filler exposed on this surface is exposed. 6 is melted to form many uneven portions 9
Is formed to roughen the surface of the insulating layer 4. FIG. 10 shows FIG.
It is an enlarged view which shows the B section in (E). Further, in the connection hole 8, debris generated when the laser beam 7 is used to form a hole remains as a residue 10 (see FIG. 8D).
The residue 10 is cleaned and removed by the action of the potassium permanganate solution.

[0008] Next, as shown in FIG. 8 (F), in order to form a base for electroless plating in the next step, for example, a solution formed by dissolving tin and palladium is applied to the surface of the insulating layer 4 to form a catalyst 12. To make the entire surface of the insulating layer conductive. Next, as shown in FIG. 8G, for example, a thickness of 0.3 μm is applied over the entire surface of the insulating layer 4 by electroless plating.
m for electroplating conductive film 13 of copper or the like
To form Further, as shown in FIG. 8H, a conductive film 14 made of, for example, copper is formed on the conductive film 13 for electroplating with a thickness of about 20 μm by electroplating. Thereby, the conductive film 14 and the lower wiring pattern 2
Can be conducted. In a normal process, after that, after forming an insulating layer, wiring patterning is performed again, and a printed circuit board of each layer is manufactured by repeating the above-described process.

[0007]

By the way, in the above-mentioned manufacturing method, the line width or the line width of the wiring pattern 2 is set to 5 or less.
In order to reduce the size to 0 μm or less, it is necessary to reduce the thickness of the insulating layers 3 and 4 and the diameter of the connection holes 8 accordingly. However, it was very difficult to form a good printed circuit board with this. . The reason is that the diameter L4 of the inorganic filler 6 contained in the second insulating layer 4 is about 10 μm, so that this dimension is too large compared to the line width or the like, so that it is very difficult to form a pattern with high accuracy in a straight line. Becomes difficult. On the other hand, it is conceivable to reduce the diameter of the inorganic filler 6. In this case, however, the catalysis solution is sufficiently filled with the uneven portions 9.
It cannot be adopted because it will not penetrate inside.

In addition, as described above, it is desired that the diameter of the connection hole 8 be set to 50 μm or less in accordance with the miniaturization. In some cases, it becomes difficult for the catalysis solution to enter, so that not only the residue 10 cannot be sufficiently removed, but also the conduction between the conductive film 14 formed by plating and the underlying pattern 2 cannot be sufficiently obtained. Further, in the above-described manufacturing method, not only the two insulating layers 3 and 4 are required, but also a chemical method is used in which a chemical solution is washed away each time since a wet method using an alkaline potassium permanganate solution or a catalysis solution is used. Since a cleaning process is required, the number of steps is increased as a whole, resulting in an increase in cost. In addition, since the inorganic filler 6 made of CaCO ₃ has a high hygroscopicity, it may absorb moisture every time the wet treatment is performed, thereby deteriorating the insulation performance.

The present invention focuses on the above problems,
The purpose of the present invention is to provide a method of manufacturing a fine-patterned printed circuit board and a printed circuit board with a small number of processes by using dry etching or sputter film formation. is there.

[0010]

In order to solve the above-mentioned problems, the present invention comprises a step of forming a wiring pattern on a surface of a core material, and a step of forming an inorganic filler on the surface of the core material including the wiring pattern. A step of forming an insulating layer made of a mixed organic resin, a step of selectively forming a connection hole reaching the wiring pattern in the insulating layer, and removing the surface of the insulating layer by dry etching to obtain a rough surface. Forming a conductive film for electroplating on the surface of the insulating layer containing the inorganic filler by vacuum film formation; and forming a conductive film on the conductive film for electroplating by electroplating. Is included.

As a result, it is possible to form a printed circuit board having a reduced line width and line width with a smaller number of steps than in the conventional method without increasing the number of steps. In this case, between the surface roughening step and the step of forming the electroplating conductive film, a filler removing step of removing the inorganic filler exposed on the surface of the insulating layer may be included. The free filler that is falling off from the surface of the insulating layer can be removed, and the adhesion between the electroplating conductive film and the surface of the insulating layer can be improved accordingly.

Further, after the surface roughening step, a fine surface roughening step of further finely roughening the surface of the insulating layer by dry etching is performed, whereby the surface of the insulating layer is further finely roughened. Therefore, it is possible to further improve the adhesion between this and the electroplating conductive film.

For the dry etching, for example, reactive ion etching under a high oxygen partial pressure can be used, and the fine graining step can be performed by a reactive ion etching under a low oxygen partial pressure.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a printed circuit board manufacturing method and a printed circuit board according to an embodiment of the present invention; The same components as those of the conventional printed circuit board described with reference to FIGS. 1 is a process diagram showing a method of manufacturing a printed circuit board according to the present invention, FIG. 2 is an enlarged view showing a portion C in FIG. 1, and FIG. 3 is an enlarged view showing a portion D in FIG. A feature of the method of the present invention is that the wet processing is only an electroplating processing and a free filler removing processing, and the other steps are performed by dry etching or sputtering.

First, as shown in FIG. 1A, a predetermined wiring pattern 2 is formed by forming a copper foil or the like on the surface of an insulating core material 1 made of, for example, a glass epoxy resin and patterning the same. Form. The line width L5 and the line width L6 of the wiring pattern 2 are each about 25 to 50 μm, which is smaller than a conventional printed circuit board.
The thickness W2 of the pattern 2 is about 20 μm. The surface of the wiring pattern 2 is oxidized and blackened to increase the degree of adhesion to the epoxy resin layer in a later step. Note that the line width L5 and the line width L6 of the wiring pattern 2 may be set to the line width L1 and the line width L2 shown in the related art without being set to the above-mentioned widths, and the dimensions are not limited. .

Next, as shown in FIG. 1B, an insulating layer 3 is formed on the entire surface of the core material 1 by a method such as screen printing. As the insulating layer 3, the same material as that of the first insulating layer 3 described above is used.
That is, as shown in FIG. 2, the main material of the insulating layer 3 is, for example, an epoxy resin. The insulating layer 3 contains an appropriate amount of an SiO ₂ filler 5 having a particle size L3 of about 1 μm as an inorganic filler to improve the insulating properties, and the thickness T3 is set to about 20 to 30 μm. It is formed much thinner than the conventional printed circuit board of about 50 μm.

Next, as shown in FIG. 1C, a connection hole 8 is selectively formed in the electrical connection portion by using, for example, a laser beam 7 so as to penetrate the insulating layer 3, thereby forming an internal wiring. The pattern 2 is exposed. The diameter D2 of this hole 8 is 20
５０50 μm, which is considerably smaller than that of a conventional printed circuit board.

Next, the entire core material is introduced into a dry etching apparatus and subjected to a dry etching treatment as shown in FIG. 1 (D), so that the surface of only the insulating layer 3 which is an organic substance is reduced by a slight thickness. Remove by shaving. In this case, as shown in FIG.
Is not removed by dry etching but remains partially exposed, and consequently unevenness appears on the entire surface and the surface is roughened. In order to perform the etching process at this time, a normal RIE (reactive ion etching) device using a high-frequency power supply for plasma formation may be used, and an O ₂ gas is used as an etching gas for dry-etching organic substances. In order to increase the etching rate, the etching is performed under a high oxygen partial pressure. Although this oxygen partial pressure depends on a target etching rate, for example, 0.05 to 0.1 T
It may be set to about orr.

In the connection hole 8, debris generated when drilling by the laser beam 7 is left as a residue 10 (FIG. 1).
(See (C)), but is decomposed into H ₂ O and CO ₂ by the above dry etching treatment.
0 is removed.

Next, the entire core material is introduced into a sputter film forming apparatus using a vacuum film forming method to perform sputter film formation, and as shown in FIG.
An electroplating conductive film 13 made of copper or the like is formed over the entire inner wall surface until the thickness becomes, for example, about 0.3 μm. As the sputtering device, for example, a DC magnetron sputtering film forming device can be used, and as the plasma gas, Ar gas can be used. The film formation of the electroplating conductive film 13 is not limited to the case where the film is formed using a sputtering film forming apparatus, but may be formed by any method as long as it is a vacuum film forming method. Next, FIG.
As shown in (F), on the electroplating conductive film 13,
The conductive film 14 made of, for example, copper is
It is formed with a thickness of about m. Thereby, conduction between the conductor film 14 and the lower wiring pattern 2 can be achieved. In a normal process, after that, after forming an insulating layer, wiring patterning is performed again, and the above-described process is repeated to form a multilayer printed board (built-up board).
To manufacture.

As described above, according to the method of the present invention, the steps for performing the wet processing are only the electroplating step shown in FIG. 1 (F) and the free filler removing step (FIG. 4) described later.
Since the other processes are dry processes that do not use a liquid, a number of washing processes and neutralization processes required by the conventional method can be eliminated. Further, in the conventional method, one or more insulating layers are used, but only one insulating layer can be used in the method of the present invention. Accordingly, it is possible to manufacture a printed circuit board having a miniaturized wiring pattern without increasing the number of processing steps as compared with the case of the conventional method.

Further, the water-absorbing Ca used in the conventional method is used.
Since it is not necessary to use a Co ₃ filler, the insulating property can be improved accordingly. In the above embodiment, the electroplating conductive film 13 was formed as shown in FIG. 1E in a state where the inorganic filler 5 partially exposed on the surface of the insulating layer 3 as shown in FIG. In this case, it is conceivable that the inorganic filler 5 partially exposed is dropped from the surface of the insulating layer 3 and separated in a later step or the like, and when the separated free filler is generated, the insulating layer 3 and the upper layer are removed. , The adhesion of the electroplating conductive film 13 may be deteriorated. Therefore, before forming the electroplating conductive film 13, it is preferable to incorporate a free filler removing step of removing the inorganic filler 5 having a part thereof exposed. In this free filler removing step, as shown in FIG. 4, the entire core material after the dry etching step is immersed in pure water, and ultrasonic cleaning is performed by applying ultrasonic waves to the core material. FIG. 5 is an enlarged view showing a portion E in FIG. As a result, the inorganic filler 5 partially exposed on the surface of the insulating layer 3 falls off and becomes a free filler 5A and is removed. In addition, a concave portion 15 is formed in a portion where the inorganic filler 5 has dropped off, whereby the entire surface of the insulating layer 3 becomes uneven and is maintained in a roughened state.

In this state, if the electroconductive film 13 for electroplating as shown in FIG. 1E is formed on the surface of the insulating layer 3 by a sputtering film forming apparatus, the above-mentioned deterioration of adhesion due to the free filler 5A is prevented. And higher adhesion can be obtained. Further, the insulating layer 5 shown in FIG.
Instead of the above-described process of forming the electroplating conductive film 13 directly on the insulating layer 3, as shown in FIG.
A fine surface roughening step of further finely roughening the surface may be performed. FIG. 7 is an enlarged view showing a portion F in FIG. This fine roughening step may be performed after the step shown in FIG.

In this fine-roughening step, the surface of the insulating layer 3 made of an organic material is subjected to a dry etching treatment at a smaller etching rate than the case of the dry etching shown in FIG. The same reactive ion etching as described above is performed. At the time of this dry etching, the process is performed under a low oxygen partial pressure by lowering the partial pressure of the O ₂ gas in order to reduce the etching rate. At this time, the oxygen partial pressure is set to a pressure of 0.05 Torr or less, and the lower limit is a limit value at which the plasma starts, for example, 0.003T.
orr. By performing the reactive ion etching under the low oxygen partial pressure in this manner, very fine irregularities, that is, minute irregularities 16 are formed on the surface of the insulating layer 3. Therefore, when the electroplating conductive film 13 is directly formed on the fine irregularities 16 by a sputtering film forming apparatus, the adhesion between the two can be further improved.

In the above embodiment, the case where SiO ₂ particles are used as the inorganic filler 5 has been described as an example. However, the material is not limited to this as long as it is not removed by dry etching. Of course, it is good. In addition, the dimensions of each of the above members are merely examples, and are not limited thereto.

[0026]

As described above, according to the method of manufacturing a printed circuit board and the printed circuit board of the present invention, the following excellent operational effects can be obtained. By using dry etching or vacuum film formation (sputtering), a printed circuit board having a miniaturized wiring pattern can be manufactured without increasing the number of steps or reducing the number of steps. Therefore, it is possible to provide an inexpensive fine-pattern printed circuit board that does not cause an increase in cost. In addition, by removing the inorganic filler exposed on the surface of the insulating layer to remove the free filler, the adhesion between the insulating layer and the upper conductive film can be improved. Further, by performing a fine roughening step of finely roughening the surface of the insulating layer, the adhesion between the insulating layer and the upper conductive film can be further improved.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing a printed circuit board according to the present invention.

FIG. 2 is an enlarged view showing a portion C in FIG.

FIG. 3 is an enlarged view showing a D part in FIG. 1;

FIG. 4 is a diagram for explaining a modification of the method of the present invention.

FIG. 5 is an enlarged view showing a portion E in FIG. 4;

FIG. 6 is a diagram for explaining another modification of the method of the present invention.

FIG. 7 is an enlarged view showing a portion F in FIG. 6;

FIG. 8 is a view for explaining a conventional method of manufacturing a printed circuit board.

FIG. 9 is an enlarged view showing a portion A in FIGS. 8 (C) and 8 (D).

FIG. 10 is an enlarged view showing a portion B in FIG. 8 (E).

[Explanation of symbols]

1 ... core material, 2 ... wiring pattern, 3: insulating layer (first insulating layer), 5 ... SiO ₂ filler (inorganic filler), 7
... Laser light, 8 ... Connection hole, 13 ... Electroplating conductive film, 14 ... Conductor film.

Claims (6)

[Claims] A step of forming a wiring pattern on a surface of a core material; a step of forming an insulating layer made of an organic resin mixed with an inorganic filler on a surface of the core material including the wiring pattern; A step of selectively forming a connection hole reaching the wiring pattern in a layer; a step of removing the surface of the insulating layer by dry etching to roughen the layer; and forming the insulating layer containing the inorganic filler by vacuum film formation. A method for manufacturing a printed board, comprising: forming a conductive film for electroplating on the surface of a layer; and forming a conductive film on the conductive film for electroplating by electroplating. 2. A filler removing step of removing the inorganic filler exposed on the surface of the insulating layer is performed between the surface roughening step and the electroplating conductive film forming step. The method for manufacturing a printed circuit board according to claim 1. 3. The method according to claim 1, further comprising, after the surface roughening step, performing a fine surface roughening step of further finely roughening the surface of the insulating layer by dry etching.
The method for manufacturing a printed circuit board according to the above. 4. The method according to claim 1, wherein said dry etching is reactive ion etching under a high oxygen partial pressure. 5. The method for manufacturing a printed circuit board according to claim 3, wherein the fine surface roughening step is performed by reactive ion etching under a low oxygen partial pressure. 6. A wiring pattern is formed on a surface of a core material,
Forming an insulating layer made of an organic resin mixed with an inorganic filler on the surface of the core material including the wiring pattern, selectively forming a connection hole reaching the wiring pattern in the insulating layer, and performing dry etching. The surface of the insulating layer is removed to roughen the surface, a conductive film for electroplating is formed on the surface of the insulating layer containing the inorganic filler by vacuum film formation, and a conductor is formed on the conductive film for electroplating by electroplating. A printed circuit board formed by forming a film.