JPH11213863A - Field emission type cold cathode and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain delay of signal by lowering the wiring resistance of a gate electrode of a field emission type cold cathode. SOLUTION: An emitter electrode layer 13 is formed on a quartz glass substrate 11 via an ITO electrode layer 12 which serves as a cathode electrode. The emitter electrode layer 13 has a projecting part 20 which projects like a pyramid to the surface of the emitter electrode layer 13. A thin silicon oxide film 14 is formed on the emitter electrode layer 13. The silicon oxide layer 14 is formed except at a tip of the projection part 20 of the emitter electrode layer 13, and the emitter electrode layer 13 is exposed at the projecting part 20. A gate electrode 16 formed of a tungsten film having flat surface is formed on the silicon oxide film 14. The gate electrode 16 is formed with an opening part at a position over the tip of the projecting part 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field emission cold cathode and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, field emission type cold cathodes utilizing advanced Si semiconductor processing technology have been actively developed.

[0003] A field emission cold cathode is formed of a conical or pyramid-shaped emitter electrode layer formed on a cathode electrode, and a gate electrode for extracting electrons from the tip of the emitter electrode layer.

[0004] The method of forming the field emission type cold cathode is roughly classified into two methods, a Spindt method and a transfer molding method. When formed by the Spindt method, a gate electrode is formed on an insulating layer formed so as to surround a conical emitter. Further, when formed by the transfer molding method, a gate electrode is formed via an insulating film formed on a side surface of the emitter. In any of the configurations, the gate electrode is a thin film. Therefore, there is a problem that the resistance of the gate electrode is high, and when the size is increased, a signal delay occurs.

After tiling a small panel on a substrate, adjacent gate electrodes are electrically connected by wire bonding to form a large-area field emission cold cathode. Technology has been reported. However, the use of wire bonding has a problem that the manufacturing cost is high.

[0006]

As described above, the conventional field emission type cold cathode has a problem that the gate electrode is thin and its wiring resistance is high, so that a signal delay occurs when the size is increased. there were.

Further, there has been a problem that a large field emission cold cathode cannot be manufactured at low cost.

An object of the present invention is to provide a field emission type cold cathode capable of suppressing a signal delay of resistance of a gate electrode and a method of manufacturing the same.

Another object of the present invention is to provide a field emission type cold cathode which can be made large in area and can be manufactured at a low cost, and a method of manufacturing the same.

[0010]

Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object.

(1) A field emission cold cathode according to the present invention (Claim 1) has a cathode electrode formed on an insulating substrate and an emitter formed on the cathode electrode and having a sharp projection at the tip. An electrode layer, an insulating layer formed along the surface of the emitter electrode layer, and having a tip region of the projection removed, and an opening formed on the insulating layer and having a tip region of the projection. And a gate electrode having a flat surface.

(2) The field emission type cold cathode of the present invention (claim 2) is formed by arranging a plurality of cathode electrodes on an insulating substrate along a row direction, and is electrically connected to each of the cathode electrodes. Convex portions with sharp tips are 2 in the row and column directions.
A field emission cold cathode including a two-dimensionally arranged emitter electrode layer, a plurality of emitter electrodes arranged along the column direction, extracting electrons from the tips of the respective protrusions, and a gate electrode having an opening on the tips. The emitter electrode layer is formed on each of a plurality of structural bases closely arranged on the cathode electrode, and on the emitter electrode layer of each structural base, a tip region of each projection is removed. An insulating layer is formed along the surface of the electrode layer, and the gate electrode is continuously formed on the insulating layer of the structural base adjacent in the column direction, and has a flat surface.

A preferred embodiment of the invention described in the configuration (2) will be described below.

(2-1) Part of the gate electrode is buried in the gap between the joints of the adjacent structural substrates. (2-2) Intersection between the joint of the adjacent structural base and each gate electrode. A gate electrode connection conductive layer is selectively formed on the gate electrode in a region including:

(2-3) In the gap between the adjacent structural bases, a first isolation insulator for closing an opening of the gap is formed.

(2-4) The joint between the adjacent structural bases is formed on the second isolation insulator formed on the insulating substrate.

(2-5) A cathode electrode connecting conductive layer is formed below the cathode electrode in a region including a junction between adjacent structural bases.

(3) In the method of manufacturing a field emission cold cathode according to the present invention (claim 7), a step of forming a recess having a sharp bottom in a mold substrate, and a step of forming an insulating layer on the mold substrate are provided. Forming an emitter electrode layer on the insulating layer; forming a cathode electrode on the emitter electrode layer; forming a structural base; and forming the structural base and the insulating substrate with the emitter electrode layer. A step of bonding so as to interpose, removing the mold substrate, the emitter electrode layer and the insulating layer formed in the concave portion project from a flat portion of the insulating layer, and the tip has a sharp convex portion. Forming a gate electrode on the insulating layer, the gate electrode covering the tip of the projection, and substantially uniformly etching or polishing the surface of the gate electrode to expose the insulating layer of the projection. And the process Selectively etching the exposed insulating layer to expose the tip of the projection of the emitter electrode layer.

(4) In the method of manufacturing a field emission cold cathode according to the present invention (claim 8), a step of providing a concave portion having a sharp bottom in a mold substrate; and a step of forming an insulating layer on the mold substrate. A step of forming a structural base from a step of forming an emitter electrode layer on the insulating layer; and a step of bonding the structural base and a cathode electrode formed on the insulating substrate so that the emitter electrode layer intervenes. Removing the mold substrate, the emitter electrode layer and the insulating layer formed in the concave portion project from a flat portion of the insulating layer, the step of forming a sharp tip convex portion, Forming a gate electrode on the insulating layer, the gate electrode covering the tip of the projection; etching or polishing the surface of the gate electrode substantially uniformly; exposing the insulating layer of the projection; Select insulating layer And exposing the tips of the projections of the emitter electrode layer.

(5) In the method of manufacturing a field emission cold cathode according to the present invention (claim 9), a step of forming a plurality of concave portions having a sharp bottom in a mold substrate, and forming an insulating layer on the mold substrate. Forming a plurality of structural bases including a step of forming an emitter electrode layer on the insulating layer, and a cathode electrode formed along the row direction on each of the structural bases and the insulating substrate And a step of adhering the emitter electrode layer so that the adjacent structural bases are in close contact with each other, removing each mold substrate, and forming the emitter electrode layer and the insulating layer formed in the concave portion, Forming a plurality of convex portions having a sharp tip protruding from a flat portion of the insulating layer; forming a gate electrode material on the insulating layer to cover a tip portion of the convex portion; Almost uniform surface of electrode material Etching or polishing to expose the insulating layer of the convex portion, forming a plurality of gate electrodes along the column direction by patterning the gate electrode material,
Selectively exposing the exposed insulating layer to expose the tips of the projections of the emitter electrode layer.

A preferred embodiment of the invention described in the constitution (5) will be described below.

(5-1) Before the step of forming the gate electrode, a first isolation insulator for closing a gap between adjacent structural bases is formed.

(5-2) After the surface of the gate electrode is substantially uniformly etched or polished, the surface of the gate electrode is selectively placed on the region including the intersection between the junction of the adjacent structural base and the gate electrode. A gate electrode connection conductive layer is formed.

(5-3) When bonding each of the structural bases to the cathode electrode formed on the insulating substrate, the bonding portion between the adjacent structural bases is bonded to the second electrode formed on the insulating substrate.
Formed on the isolation insulator.

(6) In the method of manufacturing a field emission cold cathode of the present invention (claim 13), a step of forming a plurality of concave portions having a sharp bottom in a mold substrate and a step of forming an insulating layer on the mold substrate Forming a plurality of structural bases including: forming an emitter electrode layer on the etching stop layer; forming each of the structural bases on a support substrate, forming each mold substrate and the support substrate. Contacting, and arranging the adjacent structural bases in close contact with each other; forming a cathode electrode on the emitter electrode layer along the row direction; and bonding the cathode electrode to a structural substrate.
Removing the supporting substrate and the mold substrate, and forming the projecting portion in which the emitter electrode layer and the insulating layer formed in the concave portion project from a flat portion of the insulating layer stop layer; Forming a gate electrode on the layer to cover the tip of the projection; etching or polishing the surface of the gate electrode substantially uniformly to expose an insulating layer of the projection; Patterning to form a plurality of gate electrodes along the column direction, and selectively exposing the exposed insulating layer to expose the tips of the projections of the emitter electrode layer.

A preferred embodiment of the invention described in the constitution (6) will be described below.

(6-1) The structural substrate is formed of an insulating substrate and a cathode electrode connecting conductive layer formed on the insulating substrate, and a joining portion of a structural base adjacent to the cathode electrode conductive connecting layer is formed. The cathode electrode and the structural substrate are bonded so that an intersection between the cathode electrode and the cathode electrode is located.

Preferred embodiments of the invention described in the constitutions (3) to (6) are shown below.

(3-6-1) The mold substrate is a silicon single crystal substrate.

(3-6-2) In polishing the gate electrode material, a chemical mechanical polishing method is used.

(3-6-3) The gate electrode material is deposited by a printing method, an electroplating method, an evaporation method or a sputtering method.

[Operation] The present invention has the following operation / effect by the above configuration.

In the field emission cold cathode of the present invention, the gate having a flat surface is formed on the emitter electrode layer having a sharp projection at the tip via an insulating layer formed so that the projection is exposed. Electrodes are formed.

That is, the gate electrode is a very thick film as compared with the gate electrode of the conventional structure. Therefore, the thickness of the gate electrode is much smaller than that of the related art, and signal delay can be suppressed even when a large-area field emission cold cathode is formed.

The flat gate electrode is formed by depositing a gate electrode covering the projection and then uniformly polishing or etching the surface, that is, a CMP method or an etch-back method. At this time, when the surface of the gate electrode is polished by using the CMP method, the polishing can be performed while accurately measuring the film thickness with a laser or the like, so that the end point of polishing can be accurately determined.

By controlling the thickness of the silicon oxide film and the thickness of the gate electrode, the distance between the gate and the emitter can be controlled extremely accurately. Further, by increasing the thickness of the gate electrode, the distance between the gate and the emitter can be made smaller than the mask size of the exposure apparatus. Reducing the gate / emitter distance greatly improves the efficiency and uniformity of emission of electrons from the emitter.

Further, each structural base having a plurality of emitters formed therein and a cathode electrode formed on an insulating substrate are connected to each other such that the emitter electrode layer is interposed and the adjacent structural bases are in close contact with each other. After the substrates are two-dimensionally arranged and bonded (tiling), the mold substrate is removed, and a gate electrode is deposited, whereby a large-area field emission cold cathode can be formed.

In the present method, the gate electrode is formed after the tiling, so that the steps such as wire bonding are not required as compared with the conventional method. Cold cathodes can be formed. In addition, since the gate electrode is deposited after the tiling of the structural base, there is no possibility that the gate electrode is broken between adjacent structural bases and electrical connection cannot be established. Therefore, the area of the field emission cold cathode can be easily increased, and the productivity can be greatly improved.

Further, the manufacturing cost can be reduced by depositing the gate electrode material using a printing method or an electroplating method.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a sectional view showing the structure of a field emission cold cathode according to a first embodiment of the present invention.

An emitter electrode layer 13 is formed on a quartz glass substrate 11 via an ITO electrode layer 12 serving as a cathode electrode. The emitter electrode layer 13 has a protrusion 20 projecting in a pyramid shape with respect to the plane thereof. A thin silicon oxide film 14 is formed on emitter electrode layer 13. The silicon oxide film 14 is formed except for the tip of the projection 20 of the emitter electrode layer 13, and
3 is exposed. A gate electrode 16 made of a tungsten film having a flat surface is formed on the silicon oxide film 14. The gate electrode 16 has an opening formed on the tip of the projection 20.

Since the gate electrode 16 is formed thick, its resistance is low. Therefore, when a large field emission cold cathode is formed, signal delay can be suppressed.

The manufacturing process of the field emission type cold cathode shown in FIG. 1 will be described with reference to the process sectional views of FIGS.

First, as shown in FIG. 2A, an inverted pyramid pointed recess 18 is formed on one surface of a p-type (100) silicon single crystal substrate 17. As a method for forming such a concave portion 18, there is a method utilizing anisotropic etching of a silicon single crystal substrate as described below. That is, first, a silicon oxide film having a thickness of 0.1 μm is formed on a silicon single crystal substrate having a (100) crystal plane orientation by a dry oxidation method, and a resist is applied by a spin coating method. Next, patterning such as exposure and development is performed using a stepper to obtain an opening of, for example, 1 μm square, and then the silicon oxide film is etched with a mixed solution of NH ₄ F and HF. After removing the resist, anisotropic etching of the silicon substrate is performed using a 30 wt% KOH aqueous solution to form a concave portion on the inverted pyramid having a depth of 0.71 μm in the silicon single crystal substrate. Then, the silicon oxide film may be selectively removed using a mixed solution of NH ₄ F and HF.

Next, as shown in FIG. 2B, a silicon oxide film 14 is formed on the Si single crystal substrate 17 including the surface of the recess 18. In this embodiment, the silicon oxide film 14 is formed by a wet oxidation method so as to have a thickness of 0.3 μm.

The silicon oxide film 14 can also be formed by depositing silicon oxide by a CVD method or the like. However, when formed by thermal oxidation,
It is preferable to form a silicon oxide film by thermal oxidation because it is dense and it is easy to control the thickness. . Also. In addition, due to the growth action inside the concave portion 18, the tip of the concave portion 18 becomes sharper than when a silicon oxide film is formed by deposition by a CVD method or the like, and the tip of an emitter formed in a later step becomes sharper.

Then, as shown in FIG. 2C, a W film is formed on the silicon oxide
m is deposited to form an emitter electrode layer 13. In addition, other than W, a material such as a W layer, a Mo layer, and a Ta layer can be used for the emitter electrode layer 13.

Next, on the emitter electrode layer 13, an ITO electrode layer 12 having a thickness of about 1 μm to be a cathode electrode is formed by a sputtering method. Note that depending on the material of the emitter electrode layer 13, the formation of the ITO electrode layer 12 can be omitted. When the ITO layer 12 was not formed,
The emitter electrode layer 13 also functions as a cathode electrode.

Next, as shown in FIG. 2D, the quartz glass substrate 11 and the ITO layer 12 are bonded. For this bonding, for example, an electrostatic bonding method can be applied. The electrostatic bonding method contributes to a reduction in the weight and thickness of the cold cathode device.

It is also possible to form the present structure by bonding the emitter electrode layer 13 and the ITO electrode layer 13 formed on the quartz glass substrate 11 in advance.

An aqueous solution comprising ethylenediamine / pyrocatechol / pyrazine (ethylenediamine: 75)
cc, pyrocatechol: 12 g, pyrazine: 3 mg,
The silicon single crystal substrate 17 is selectively removed with water (10 cc) to expose the silicon oxide film 14. Up to this step, a projection 20 is formed in which the emitter electrode layer 13 and a part of the silicon oxide film 14 project in a pyramid shape with respect to the flat surface of the silicon oxide film 14. The removal of the silicon single crystal substrate 17 may be performed by mechanical force other than etching, by using the silicon oxide film 14 and the silicon single crystal substrate 1.
7 can also be carried out.

Next, as shown in FIG. 2E, a gate electrode 16 is formed on the silicon oxide film 14 by sputtering.
Is formed until the tip of the projection 20 is covered.

Next, as shown in FIG.
The gate electrode 16 is polished using a method to expose the tip of the silicon oxide film 14 protrusion 20. At this time, the polishing is performed while measuring the polishing end point using a laser or the like so that the emitter electrode layer 13 is not polished.

[0055] Then, as shown in FIG. 3 (g), NH ₄
The silicon oxide film 14 is selectively removed using a mixed solution of F and HF. Through the above steps, an opening is formed in the gate electrode 16, the tip of the pyramid-shaped projection 20 of the emitter electrode layer 13 is exposed, and a pyramid-shaped cold cathode, that is, an emitter is formed. You.

According to the field emission cold cathode of this embodiment,
Since the gate electrode is thick, the wiring resistance is reduced and the signal delay can be suppressed. Further, when the gate electrode is polished to expose the silicon oxide film, etching or polishing can be performed without using a mask.

Further, since the thickness of the gate electrode is extremely large, the strength of the gate electrode is improved. Therefore, the displacement of the gate electrode with respect to the electric field induced stress is small, and the gate electrode and the emitter electrode layer are not electrically connected.

Further, when the pillar or the focus electrode is formed on the cathode, the surface is flattened by the CMP, so that the manufacturing becomes easy.

[Second Embodiment] FIG. 4 is a sectional view showing the structure of a field emission cold cathode according to a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The feature of this embodiment is that an emitter electrode layer 35 is formed on the ITO electrode layer 12 with a core-shaped resistance layer 34 interposed therebetween. The emitter electrode layer 35 includes a projection 33
Each of the core-shaped resistance layers 3
4 electrically connects to the ITO electrode layer 12.

Since the shape of the emitter electrode layer 35 may be different due to variations at the time of manufacture, the gate electrode 16
A large amount of current flows from the emitter electrode layer 35 having a short distance between the gate electrode 16 and the emitter electrode layer 3.
5 may be short-circuited. However, by inserting the core-shaped resistive layer 34 between the emitter electrode layer 35 and the ITO electrode layer 12, the current flowing from the ITO electrode layer 12 to the emitter electrode layer 35 can be limited, and a short circuit can be suppressed.

The manufacturing process of the cold cathode shown in FIG. 4 will be described with reference to FIGS. FIG. 5 (a),
(B) is the same as the process shown in FIGS. 2A and 2B of the second embodiment, and a description thereof will be omitted. And
As shown in FIG. 5C, an electrode material is deposited on the silicon oxide film 14. Then, after a resist (not shown) is formed on the electrode material in a region including the concave portion 18, the electrode material is etched by using the resist as a mask by RIE to form an emitter electrode layer 35, and the resist is removed.

Next, as shown in FIG. 5D, a core-shaped resistance layer 34 is deposited on the silicon oxide film 14 and the emitter electrode layer 35. Then, the ITO is formed on the core-shaped resistance layer 34.
An electrode 12 is formed.

Next, as shown in FIG. 5E, after bonding the quartz glass substrate 11 and the cathode electrode, the silicon single crystal substrate 17 is removed as in the second embodiment. Up to this step, the emitter electrode layer 35 and the silicon oxide film 1
Part 4 is formed with a convex portion 20 that protrudes in a pyramid shape with respect to the flat surface of the silicon oxide film 14.

Next, as shown in FIG. 5F, a gate electrode 16 is formed on the silicon oxide film 14 by sputtering.
Is formed until the tip of the projection 20 is covered.

Next, as shown in FIG.
The gate electrode 16 is polished by using the
The silicon oxide film 14 at the leading end of the substrate 0 is exposed. Then, as shown in FIG. 6 (h), the silicon oxide film 14 is selectively removed using an NH ₄ F.HF mixed solution. Through the above steps, an opening is formed in the gate electrode 16 and the pyramid-shaped emitter electrode layer 3 is formed.
5 are exposed to form a pyramid-shaped cold cathode, that is, an emitter.

According to the present embodiment, by inserting the core-shaped resistive layer between the emitter electrode layer and the ITO electrode, the current flowing from the ITO electrode to the emitter electrode layer can be limited, and the short circuit can be suppressed.

[Third Embodiment] FIG. 7 is a sectional view showing the structure of an FEA (Field Emission Array) according to a third embodiment of the present invention. 7, the same parts as those in FIG. 5 are denoted by the same reference numerals, and the description thereof will be omitted.

The feature of this embodiment is that the projection 2 has a sharp tip.
The structure base 43 (43a-d) in which a plurality of emitter electrode layers 35 having zero are formed is a quartz glass substrate 4
1, cathode electrodes 42a formed along the row direction,
b, two-dimensionally arranged in close contact with each other in the row direction and the column direction. The gate electrodes 44a and 44b are formed on the structural base 43 along the column direction.

FIG. 7 is an enlarged view of a joint of the structural bases 43a to 43d.
Many emitter electrode layers 35 are formed other than the illustrated part. Further, although one structural base is illustrated as being disposed at the intersection of the cathode electrode 42 and the gate electrode 44, the cathode electrode 42 is provided on one structural base.
And a plurality of intersections between the gate electrode 44 and the gate electrode 44 are formed.

The manufacturing process of the cold cathode will be described with reference to FIGS.

First, as shown in FIG. 8A, a plurality of emitter electrode layers 35 are formed by using the steps shown in FIGS. Structural bases 43a to 43d on which the layer 34 has been formed and patterned are prepared. Further, a quartz glass substrate 41 having cathode electrodes 42a and 42b formed on the surface thereof along the row direction is prepared.

Next, as shown in FIG. 9B, the structural bases 43a to 43d and the cathode electrode 42 of the quartz glass substrate 41 are formed.
The surface on which a and b are formed is bonded so that the emitter electrode layer 35 is interposed. That is, the core-shaped resistance layer 34 and the cathode electrodes 42a and 42b are bonded.

Next, as shown in FIG. 9C, an aqueous solution comprising ethylenediamine / pyrocatechol / pyrazine (ethylenediamine: 75 cc, pyrocatechol: 12
g, pyrazine: 3 mg, water: 10 cc) to selectively remove the silicon single crystal substrate 17 by etching to expose the silicon oxide film 14. Up to this step, a plurality of convex portions are formed in which the emitter electrode layer 35 and a part of the silicon oxide film 14 project in a pyramid shape with respect to the flat portion of the silicon oxide film 14.

Next, as shown in FIG. 10D, after depositing a gate electrode 44 covering the convex portion on the silicon oxide film 14, the gate electrode 44 is polished by the CMP method to form the convex portion. The silicon oxide film 14 is exposed. At this time, if the gate electrode is deposited such that the gate electrode is buried in the gap between the adjacent structural bases, the gate electrode is not broken.

Then, as shown in FIG. 10E, after the gate electrode 44 is patterned to form gate electrodes 44a and 44b along the column direction, the silicon oxide film 14 is selectively etched and Is a sharp emitter electrode layer 35
Is exposed, FEA is formed.

After the silicon oxide film 14 is selectively etched, the gate electrode 44 can be patterned to form the electrodes 44a and 44b along the column direction.

According to the present embodiment, by depositing, CMP and patterning the gate electrode after the structural base before forming the gate electrode is formed on the cathode electrode, the gate electrode is formed between the adjacent structural bases. Since the possibility of cutting is small, a large-area FEA can be formed at lower cost.

[Fourth Embodiment] FIG. 11 shows a fourth embodiment of the present invention.
FIG. 1 is a cross-sectional view illustrating a configuration of a field emission cold cathode according to an embodiment. 11, the same parts as those in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

The features of the field emission cold cathode of this embodiment are as follows.
The gate electrode connection layer 51 (51a, b) is
4 (44a, b). Each of the gate electrode connection layers 51 is formed on the adjacent structural base 43.
Is selectively formed on the gate electrode 44 located in a region including the junction. By forming the gate electrode connection layer 51, the gate electrodes can be electrically connected reliably.

The manufacturing process of the FEA shown in FIG.
The process will be described with reference to FIGS. First, as shown in FIG. 12A, the gate formed in the region including the junction of the adjacent structural base 43 with respect to the structure formed through the steps shown in FIGS. 8A to 10D. The gate electrode connection layers 51a and 51b are formed on the electrodes 44 by using a screen printing method.

Next, as shown in FIG. 12B, the gate electrode 44 is patterned. Then, as described above, the FEA shown in FIG. 11 is completed by selectively removing the silicon oxide film 14.

After patterning the gate electrode 44, the gate electrode connection layer 51 may be formed. Further, the formation of the gate electrode connection layer 51 is not limited to the screen printing method, but may be formed by depositing an electrode material and then patterning it.

[Fifth Embodiment] FIG. 13 shows a fifth embodiment of the present invention.
It is a sectional view showing the composition of FEA concerning an embodiment. In FIG. 13, the same parts as those in FIG.
The description is omitted.

This embodiment is characterized in that the adjacent structural base 6
Glass and SOG (Spin On Gl
ass), and an insulating layer 63 made of silicon oxide or silicon nitride is buried. Since the insulating layer 63 is embedded in the gap 62, when forming the gate electrodes 44 a and 44 b, the gate electrode 44 is connected to the cathode 42 in the gap 62 of the joint of the structural base 61.
The gate electrode 44 and the cathode electrode 42 are prevented from being short-circuited.

FIG. 1 shows the manufacturing process of the FEA shown in FIG.
This will be described with reference to process diagrams 4 and 15.

First, the structure shown in FIG. 14A is formed through the steps shown in FIGS. 8A to 9C described above. As shown, the structural base 61a
A gap 62 is formed between the substrate and the structural base 61b.

Next, as shown in FIG. 14B, the insulating layer 63 is filled so as to fill the gap 62 between the substrates 61a and 61b.
To form

Next, as shown in FIG. 15C, the insulating layer 62 on the silicon oxide film 14 is removed by using an etch-back method or the like, and the insulating layer is buried in the gap 62. In addition,
It is not necessary to embed the entire gap 62 with the insulating layer 63,
What is necessary is just to form so that the opening of the clearance part 62 may be closed.

Next, as shown in FIG.
After forming the gate electrodes 44a and 44b as in the embodiment,
By selectively removing silicon oxide film 14, F
EA is completed.

[Sixth Embodiment] FIG. 16 shows a sixth embodiment of the present invention.
It is a perspective view showing the composition of FEA concerning an embodiment. In FIG. 16, the same portions as those in FIG.
The description is omitted.

The feature of the FEA of the present embodiment is that an insulating layer 71 is formed below a joint between adjacent structural bases 43. Since the insulating layer 71 is formed below the junction of the adjacent structural base 43, the gate electrode 44
The gate electrode 44 is formed in the gap formed at the joint when forming the gate electrode 44.
Is formed, and the gate electrode 44 and the cathode electrode 42 are not electrically connected.

The manufacturing process of the FEA shown in FIG. 16 will be described with reference to FIGS.

First, as shown in FIG. 17A, a plurality of emitter electrode layers 35 are formed by using the steps shown in FIGS. 5A to 5D of the third embodiment, Structural bases 43a to 43d on which the layer 34 has been formed and patterned are prepared. Further, a structural substrate 70 having the cathode electrodes 42 a and 42 b and the insulating layer 71 formed on the quartz glass substrate 41 is prepared. It should be noted that the insulating layer 71 will be
When tiling the structural base 43 on top, the adjacent base 4
3 is formed at a portion in contact with the joint.

Next, as shown in FIG. 18B, the surfaces of the structural bases 43a to 43d on which the core-shaped resistive layer 34 is formed are bonded to the surfaces of the substrate 70 on which the cathode electrodes 42a and 42b are formed. I do. At this time, tiling is performed so that the joining portion between the adjacent structural bases 43 always exists on the insulating layer 71.

Next, as shown in FIG. 18C, the silicon single crystal substrate 17 is removed, the gate electrode 44 is deposited,
The FEA is completed by polishing, patterning, and etching the silicon oxide film 14.

[Seventh Embodiment] FIGS. 19 and 20 are sectional views showing the steps of manufacturing a field emission cold cathode according to a seventh embodiment of the present invention.

First, as shown in FIG. 19A, a temporary support substrate 81 and a plurality of emitter electrode layers 35 are formed by using the steps shown in FIGS. 5A to 5D of the third embodiment. After that, the structural bases 43a to 43d on which the core-shaped resistance layer 34 has been formed and patterned are prepared. Then, the support substrate 81 and the surface of the silicon substrate 17 of the structural bases 83a to 83d are temporarily bonded.

Next, as shown in FIG. 19B, cathode electrodes 83a and 83b are formed on the core-shaped resistance layer 34 in the row direction by using a screen printing method. The structural base before patterning the core-shaped resistance layer 34 (FIG. 6C)
Is temporarily bonded on the temporary support substrate 81, and then the core-shaped resistance layer 34 is
The cathode electrode 83 may be deposited thereon, and the core-shaped resistance layer 34 and the cathode electrode 83 may be patterned.

Next, as shown in FIG. 20C, the cathode electrodes 83a and 83b and the quartz glass substrate 84 are bonded. Then, the temporary support substrate 81 and the silicon single crystal substrate 1
By removing 7, a structure similar to the structure shown in FIG. 9C is formed. In the subsequent steps, the same steps as the steps shown in FIGS. 9C to 10E are performed to complete the FEA.

[Eighth Embodiment] FIG. 21 shows an eighth embodiment of the present invention.
It is a perspective view showing the composition of FEA concerning an embodiment. In FIG. 21, the same parts as those in FIG.
The description is omitted.

The feature of this embodiment is that a cathode electrode connection conductive layer 92a is formed below the cathode electrode 83 (83a, b) which is in contact with the joint between the adjacent structural base.

By forming the cathode electrode connection conductive layer 92, electrical connection of the cathode electrode 83 between adjacent structural bases 83 can be ensured.

The manufacturing process of the FEA shown in FIG.
The process will be described with reference to FIGS.

First, a plurality of structures formed through the steps shown in FIGS. 21A and 21B are prepared. Then, a quartz glass substrate 91 having the surface on which the cathode electrode connection electrode layers 92a and 92b are formed is prepared. The cathode electrode connection conductive layer 92 on the quartz glass substrate 41 is formed on the glass substrate 41 facing the intersection between the junction of the adjacent structural bases and the cathode electrodes 83a and 83b.

Next, after bonding the cathode electrode connection conductive layer 92 and the cathode electrode 83, the support substrate 81 and the silicon substrate 17 are removed, and the gate electrode is deposited, polished and patterned, and the silicon oxide film 14 is etched. Completes the FEA.

The present invention is not limited to the above embodiment. For example, by using the above-described FEA,
It is also possible to form a D (Field Emission Display) or an electron beam exposure apparatus.

Further, the material of the emitter electrode layer is not limited to tungsten, and various materials having a low work function can be used.

The deposition of the gate electrode is not limited to the sputtering method, but may be an evaporation method, a printing method, or an electroplating method.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0111]

As described above, according to the present invention, since the thickness of the gate electrode is large, the resistance of the gate wiring is low and no signal delay occurs. Further, since the thickness of the gate electrode is large, the gate electrode and the emitter do not come into contact with each other due to an electric field-induced stress and are not electrically connected.

Further, by tiling a plurality of structural bases on the substrate on which the cathode electrode is formed, and performing deposition and CMP of the gate electrode, it is possible to form the gate electrode continuously. The gate electrode does not break between the substrates.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a field emission cold cathode according to a first embodiment.

FIG. 2 is a process cross-sectional view showing a manufacturing process of the field emission cold cathode shown in FIG.

FIG. 3 is a process cross-sectional view showing a manufacturing process of the field emission cold cathode shown in FIG.

FIG. 4 is a cross-sectional view showing a configuration of a field emission cold cathode according to a second embodiment.

FIG. 5 is a process sectional view showing the configuration of the field emission cold cathode shown in FIG. 4;

FIG. 6 is a process sectional view showing the configuration of the field emission cold cathode shown in FIG. 4;

FIG. 7 is a perspective view illustrating a configuration of a field emission cold cathode according to a third embodiment.

FIG. 8 is a perspective view showing a step of manufacturing the field emission cold cathode shown in FIG.

FIG. 9 is a perspective view showing the configuration of an FEA according to a fourth embodiment.

FIG. 10 is a perspective view showing a manufacturing process of the FEA shown in FIG. 9;

FIG. 11 is a perspective view showing a manufacturing process of the FEA shown in FIG. 9;

FIG. 12 is a perspective view showing a manufacturing process of the FEA shown in FIG. 9;

FIG. 13 is an exemplary perspective view showing the configuration of an FEA according to a fifth embodiment;

FIG. 14 is a perspective view showing the configuration of the FEA shown in FIG. 13;

FIG. 15 is an exemplary perspective view showing the configuration of an FEA according to a sixth embodiment;

FIG. 16 is a perspective view showing a manufacturing process of the FEA shown in FIG. 14;

FIG. 17 is a perspective view showing a manufacturing process of the FEA shown in FIG. 14;

FIG. 18 is a perspective view showing the configuration of an FEA according to a seventh embodiment.

FIG. 19 is a perspective view showing the configuration of the FEA shown in FIG. 18;

FIG. 20 is an exemplary perspective view showing the configuration of the FEA shown in FIG. 18;

FIG. 21 is a perspective view showing a process of manufacturing the FEA according to the eighth embodiment.

FIG. 22 is a perspective view showing a manufacturing process of the FEA shown in FIG. 21;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Quartz glass substrate 12 ... ITO electrode layer (cathode electrode) 13 ... Emitter electrode layer 14 ... Silicon oxide film 16 ... Gate electrode 17 ... Silicon single crystal substrate 18 ... Concave part 19 ... Al layer 20 ... Convex part 21 ... Resist 34 ... Core-shaped resistive layer 35 Emitter electrode layer 41 Quartz glass substrate 42a, b Cathode electrode 43a-d Structural base 44a, b Gate electrode 51a, b Gate electrode connection conductive layer 61 Structural base 62 Gap 63 ... insulating layer 71 ... insulating separating layer 81 ... supporting substrate 83a, b ... cathode electrode 92a, b ... cathode electrode connecting conductive layer

Claims (17)

[Claims] A cathode electrode formed on the insulating substrate; an emitter electrode layer formed on the cathode electrode and having a sharp projection at a tip end; and formed along the surface of the emitter electrode layer; An insulating layer in which a tip region of the projection is removed, and a gate electrode formed with a flat surface on the insulating layer and having an opening in the tip region of the projection. A field emission type cold cathode characterized by the following. 2. A plurality of cathode electrodes arranged and formed in a row direction on an insulating substrate, and a plurality of convex portions which are electrically connected to the cathode electrodes and have sharp tips are formed in the row direction and the column direction.
A field emission cold cathode including a two-dimensionally arranged emitter electrode layer, a plurality of emitter electrodes arranged along the column direction, extracting electrons from the tips of the respective protrusions, and a gate electrode having an opening on the tips. The emitter electrode layer is formed on each of a plurality of structural bases closely arranged on the cathode electrode, and a tip region of each projection is removed on the emitter electrode layer of each structural base. An insulating layer is formed along the surface of the electrode layer; and the gate electrode is formed continuously on the insulating layer of the structural base adjacent in the column direction, and has a flat surface. Type cold cathode. 3. A gate electrode connecting conductive layer is selectively formed on the gate electrode in a region including an intersection between a junction of an adjacent structural base and each gate electrode. 3. The field emission cold cathode according to 2. 4. The field emission cold cathode according to claim 2, wherein a first isolation insulator for closing an opening of the gap is formed in a gap between adjacent structural bases. 5. The field emission cold cathode according to claim 2, wherein a joint between adjacent structural bases is formed on a second isolation insulator formed on the insulating substrate. . 6. The field emission cold cathode according to claim 2, wherein a cathode electrode connection conductive layer is formed below the cathode electrode in a region including a junction between adjacent structural bases. 7. A step of forming a recess having a sharp bottom in a mold substrate; a step of forming an insulating layer on the mold substrate; a step of forming an emitter electrode layer on the insulating layer; A step of forming a structural base from a step of forming a cathode electrode thereon; a step of bonding the structural base and an insulating substrate so that the emitter electrode layer intervenes; and The emitter electrode layer and the insulating layer formed on the insulating layer are projected to a flat portion of the insulating layer, and a step of exposing a sharp tip is formed on the insulating layer. A step of forming a covering gate electrode; a step of substantially uniformly etching or polishing the surface of the gate electrode to expose the insulating layer of the projection; and selectively etching the exposed insulating layer. Field emission cathode fabrication method, which comprises a step of exposing the protrusion of sharp said emitter electrode layer. 8. A structural base is formed from a step of providing a concave portion having a sharp bottom in a mold substrate; a step of forming an insulating layer on the mold substrate; and a step of forming an emitter electrode layer on the insulating layer. Bonding the structural substrate and a cathode electrode formed on an insulating substrate so that an emitter electrode layer is interposed therebetween; and removing the mold substrate and forming the emitter formed in the concave portion. A step of exposing the electrode layer and the insulating layer to a flat portion of the insulating layer and exposing a sharp tip, and a step of forming a gate electrode on the insulating layer to cover the tip of the convex portion. A step of substantially uniformly etching or polishing the surface of the gate electrode to expose the insulating layer of the projecting portion; and selectively etching the exposed insulating layer so that the tip of the projecting portion of the emitter electrode layer is sharp. Field emission cathode fabrication method, which comprises a step of exposing the. 9. A method comprising: forming a plurality of concave portions having sharp bottoms in a mold substrate; forming an insulating layer on the mold substrate; and forming an emitter electrode layer on the insulating layer. A step of forming a plurality of structural bases to be formed, and each of the structural bases and the cathode electrode formed along the row direction on the insulating substrate are brought into close contact with the adjacent structural bases with the emitter electrode layer interposed therebetween. And removing each mold substrate, the emitter electrode layer and the insulating layer formed in the concave portion project from a flat portion of the insulating layer, and a plurality of convex portions having a sharp tip. Exposing a portion; forming a gate electrode material on the insulating layer to cover a tip of the projection; etching or polishing the surface of the gate electrode material substantially uniformly; insulating the projection; Exposed layers Patterning the gate electrode material to form a plurality of gate electrodes along a column direction, selectively exposing the exposed insulating layer to expose a protruding portion of the emitter electrode layer having a sharp tip. A method for producing a field emission cold cathode, comprising: 10. The method according to claim 1, wherein before the step of forming the gate electrode,
The method for manufacturing a field emission cold cathode according to claim 9, wherein a first isolation insulator for closing a gap between adjacent structural substrates is formed. 11. The method according to claim 11, wherein after substantially uniformly etching or polishing the surface of the gate electrode, the gate electrode is selectively connected to the gate electrode in a region including the intersection of the junction of the adjacent structural base and the gate electrode. The method according to claim 9, wherein a conductive layer is formed. 12. When bonding each of the structural bases to the cathode electrode formed on the insulating substrate, the bonding portion between the adjacent structural bases is formed on the second isolation insulator formed on the insulating substrate. The method according to claim 9, wherein the cold cathode is formed. 13. A method comprising: forming a plurality of concave portions having sharp bottoms on a mold substrate; forming an insulating layer on the mold substrate; and forming an emitter electrode layer on the insulating layer. Forming a plurality of structural bases to be formed; arranging each of the structural bases on a supporting substrate in such a manner that each mold substrate and the supporting substrate are in contact with each other and the adjacent structural bases are brought into close contact with each other; Forming a cathode electrode along a row direction thereon; bonding the cathode electrode to a structural substrate; removing the support substrate and the mold substrate; and forming the emitter electrode layer formed in the recess. And an insulating layer, exposing a plurality of convex portions protruding from a flat portion of the insulating layer; and forming a gate electrode material on the insulating layer to cover a tip portion of the convex portion, Previous A step of substantially uniformly etching or polishing the surface of the gate electrode material to expose the insulating layer of the convex portion; Selectively etching the layer to expose a protruding portion of the emitter electrode layer having a sharp tip. 14. The structure substrate is formed of an insulating substrate and a cathode electrode connecting conductive layer formed on the insulating substrate, and a joining portion of a structural base adjacent to the cathode electrode conductive connecting layer and the cathode are formed. 14. The method according to claim 13, wherein the cathode electrode and the structural substrate are bonded so that an intersection with the electrode is located. 15. The method according to claim 7, wherein the mold substrate is a silicon single crystal substrate. 16. A polishing method according to claim 7, wherein said gate electrode material is polished by a chemical mechanical polishing method.
14. The method for producing a field emission cold cathode according to any one of 8, 9, and 13. 17. The method according to claim 7, wherein said gate electrode material is formed by a printing method or an electroplating method.
14. The method for producing a field emission cold cathode according to any one of 8, 9, and 13.