JP3529612B2 - Field emission cold cathode and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission cold cathode and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, field emission type cold cathodes utilizing the developed Si semiconductor processing technology have been actively developed.

A field emission type cold cathode is formed by a conical or pyramidal emitter electrode layer formed on a cathode electrode and a gate electrode for extracting electrons from the tip of the emitter electrode layer.

There are roughly two methods of forming a field emission type cold cathode, a Spindt method and a transfer molding method. When formed by the Spindt method, the gate electrode is formed on the insulating layer formed so as to surround the conical emitter. Further, when formed by the transfer molding method, the gate electrode is formed via the insulating film formed on the side surface of the emitter. In any structure, the gate electrode is a thin film. Therefore, the resistance of the gate electrode is high, and there is a problem that signal delay occurs when the gate electrode is increased in size.

Also, after tiling a small panel on a substrate, adjacent gate electrodes are electrically connected by wire bonding to form a large area field emission cold cathode to form a field emission cold cathode. Technology has been reported. However, there is a problem that the manufacturing cost is high when the wire bonding is used.

[0006]

As described above, the conventional field emission type cold cathode has a problem that a signal delay occurs when it is enlarged because of its thin gate electrode film and high wiring resistance. there were.

In addition, conventionally, there is a problem that a large-sized field emission cold cathode cannot be manufactured at low cost.

An object of the present invention is to provide a field emission type cold cathode capable of suppressing the signal delay of the resistance of the gate electrode and a method for manufacturing the same.

Another object of the present invention is to provide a field emission cold cathode which can be manufactured in a large size and can be manufactured at low cost, and a method for manufacturing the same.

[0010]

[Configuration] The present invention is configured as follows to achieve the above object.

[0011]

(2) The field emission type cold cathode of the present invention has a plurality of cathode electrodes arranged on the insulating substrate along the row direction, and a convex tip having a sharp tip electrically connected to each cathode electrode. Parts are arranged two-dimensionally in the row direction and the column direction, and a plurality of parts are arranged in the column direction,
A field-emission cold cathode including electrons drawn from the tip of each protrusion and a gate electrode having an opening on the tip, wherein the emitter electrode layer is closely arranged on the cathode electrode. Formed on each of the plurality of structural bases, the tip end region of each projection is removed on the emitter electrode layer of each structural base, and an insulating layer is formed along the surface of the electrode layer. Is continuously formed on the insulating layer of the structural base adjacent to each other in the column direction and has a flat surface.

A preferred embodiment of the invention described in structure (2) will be described below.

(2-1) Part of the gate electrode is embedded in a gap between the joints of the adjacent structural substrates. (2-2) Intersections between the junctions of the adjacent structural bases and the respective gate electrodes. A gate electrode connecting conductive layer is selectively formed on the gate electrode in a region including the.

(2-3) In the gap between the adjacent structural bases, the first separation insulator for closing the opening of the gap is formed.

(2-4) The joint portion between the adjacent structural bases is formed on the second isolation insulator formed on the insulating substrate.

(2-5) A cathode electrode connecting conductive layer is formed under the cathode electrode in a region including a joint portion between adjacent structural bases.

[0018]

[0019]

(5) The method for manufacturing a field emission cold cathode according to the present invention comprises the steps of forming a plurality of concave portions having a sharp bottom on a mold substrate, forming an insulating layer on the mold substrate, and insulating the same. A step of forming a plurality of structural bases including a step of forming an emitter electrode layer on a layer; and a step of forming each of the structural bases and a cathode electrode formed on an insulating substrate in a row direction, The electrode layer is interposed,
And a step of adhering so that the adjacent structural bases are in close contact with each other, each mold substrate is removed, and the emitter electrode layer and the insulating layer formed in the recess are projected to the flat portion of the insulating layer, Forming a plurality of convex portions having sharp tips; forming a gate electrode material on the insulating layer to cover the tip portions of the convex portions; etching or polishing the surface of the gate electrode material substantially uniformly Then, the step of exposing the insulating layer of the convex portion is performed, and the gate electrode material is patterned to form a plurality of gate electrodes along the column direction, and the exposed insulating layer is selectively etched to form a convex portion of the emitter electrode layer. And a step of exposing a tip portion of the portion.

Preferred embodiments of the invention described in the constitution (5) are shown below.

(5-1) Before the step of forming the gate electrode, a first isolation insulator for closing the gap between the adjacent structural substrates is formed.

(5-2) After etching or polishing the surface of the gate electrode substantially uniformly, selectively, on the gate electrode in the region including the intersection between the junction of the adjacent structural substrate and the gate electrode, A gate electrode connecting conductive layer is formed.

(5-3) When the respective structural bases and the cathode electrode formed on the insulating substrate are adhered, the joint portion of the adjacent structural bases is formed on the insulating substrate by the second portion.
Formed on the isolation insulator.

(6) In the method for manufacturing a field emission cold cathode according to the present invention, a step of forming a plurality of concave portions having a sharp bottom on the mold substrate, a step of forming an insulating layer on the mold substrate, and the etching stop. Forming a plurality of structural bases including a step of forming an emitter electrode layer on a layer, and forming the structural bases on a supporting substrate such that each mold substrate is in contact with and adjacent to the supporting substrate. A step of arranging the structural bases in close contact with each other, a step of forming a cathode electrode on the emitter electrode layer along the row direction, a step of adhering the cathode electrode and the structural substrate, and a supporting substrate and a mold substrate. A step of removing the emitter electrode layer and the insulating layer formed in the recess to form a protrusion protruding from the flat portion of the insulating layer stop layer; and forming the protrusion on the insulating layer. Tip of A step of forming a gate electrode that covers the gate electrode, a step of etching or polishing the surface of the gate electrode substantially uniformly to expose the insulating layer of the protrusion, and Forming a gate electrode and selectively etching the exposed insulating layer to expose the tip of the protrusion of the emitter electrode layer.

Preferred embodiments of the invention described in the structure (6) are shown below.

(6-1) The structural substrate is formed of an insulating substrate and a cathode electrode connecting conductive layer formed on the insulating substrate, and a joint portion of a structural base adjacent to the cathode electrode conductive connecting layer. The cathode electrode and the structural substrate are adhered so that the intersection of the cathode electrode and the cathode electrode is located.

Preferred embodiments of the invention described in the structures (5) and (6) are shown below.

( 5, 6-1) The mold substrate is a silicon single crystal substrate.

( 5, 6-2) When polishing the gate electrode material, a chemical mechanical polishing method is used.

( 5, 6-3) The gate electrode material is deposited by printing, electroplating, vapor deposition or sputtering.

[Operation] The present invention has the following operations and effects due to the above configuration.

In the field emission type cold cathode of the present invention, the gate having a flat surface is formed on the emitter electrode layer having the projection having a sharp tip through the insulating layer formed so that the projection is exposed. Electrodes are formed.

That is, the gate electrode is an extremely thick film as compared with the gate electrode having the conventional structure. Therefore, the film thickness of the gate electrode is remarkably lower than the conventional one, and the signal delay can be suppressed even if a field emission type cold cathode having a large area is formed.

The flat gate electrode is formed by uniformly polishing or etching the surface after depositing the gate electrode covering the convex portion, that is, by the CMP method or the etchback method. At this time, when the surface of the gate electrode is polished by the CMP method, the polishing can be performed while the film thickness is precisely measured with a laser or the like, and thus the polishing end point can be accurately determined.

By controlling the thickness of the silicon oxide film and the thickness of the gate electrode, the gate-emitter distance can be controlled extremely accurately. Further, by increasing the thickness of the gate electrode, the gate / emitter distance can be made smaller than the mask size of the exposure device. Reducing the gate / emitter distance significantly improves the efficiency and uniformity of electron emission from the emitter.

In addition, the structure base having a plurality of emitters formed therein and the cathode electrode formed on the insulating substrate are arranged such that the emitter electrode layer is interposed and the adjacent structure bases are in close contact with each other. After the bases are two-dimensionally arranged and bonded (tiled), the mold substrate is removed and the gate electrode is deposited, whereby a field emission cold cathode having a large area can be formed.

In this method, since the gate electrode is formed after tiling, the number of steps is reduced as compared with the conventional method, and thus the number of steps is reduced, and a large-area field emission type which is inexpensive. Cold cathodes can be formed. Further, since the gate electrode is deposited after tiling the structural substrate, there is no possibility that the gate electrode is cut off between the adjacent structural substrates and electrical connection is lost. Therefore, it is possible to easily increase the area of the field emission cold cathode and to significantly improve the productivity.

Further, by depositing the gate electrode material by using the printing method or the electroplating method, the manufacturing cost can be reduced.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a sectional view showing the structure of a field emission cold cathode according to the first embodiment of the present invention.

An emitter electrode layer 13 is formed on a quartz glass substrate 11 with an ITO electrode layer 12 serving as a cathode electrode interposed therebetween. The emitter electrode layer 13 has a convex portion 20 protruding in a pyramid shape with respect to the plane. A thin silicon oxide film 14 is formed on the emitter electrode layer 13. The silicon oxide film 14 is formed on the emitter electrode layer 13 excluding the tips of the protrusions 20.
3 is exposed. A gate electrode 16 made of a tungsten film having a flat surface is formed on the silicon oxide film 14. The gate electrode 16 has an opening formed on the tip of the protrusion 20.

Since the gate electrode 16 is formed thick, its resistance is low. Therefore, when a large field emission cold cathode is formed, it is possible to suppress signal delay.

The manufacturing process of the field emission type cold cathode shown in FIG. 1 will be described with reference to the process sectional views of FIGS.

First, as shown in FIG. 2A, an inverted pyramid-shaped pointed recess 18 is formed on one surface of a p-type (100) silicon single crystal substrate 17. As a method of forming such a recess 18, there is a method of utilizing anisotropic etching of a silicon single crystal substrate as described below. That is, first, a silicon oxide film having a thickness of 0.1 μm is formed on a silicon single crystal substrate having a (100) crystal plane orientation by a dry oxidation method, and then a resist is applied by a spin coating method. Next, using a stepper, patterning such as exposure and development is performed so as to obtain an opening of 1 μm □, and then the silicon oxide film is etched with a NH ₄ F / HF mixed solution. After removing the resist, anisotropic etching of the silicon substrate is performed using a 30 wt% KOH aqueous solution to form a recess on the inverted pyramid having a depth of 0.71 μm in the silicon single crystal substrate. Then, the silicon oxide film may be selectively removed using a NH ₄ F / HF mixed solution.

Next, as shown in FIG. 2B, a silicon oxide film 14 including the surface of the recess 18 is formed on the Si single crystal substrate 17. In this embodiment, the silicon oxide film 14 is formed by the Wet oxidation method so as to have a thickness of 0.3 μm.

The silicon oxide film 14 can also be formed by depositing silicon oxide by the CVD method or the like. However, when formed by thermal oxidation,
It is preferable to form the silicon oxide film by thermal oxidation because it is dense and the thickness can be easily controlled. . Also. Moreover, due to the growth action inside the recess 18, the tip of the recess 18 becomes sharper as compared with the case where a silicon oxide film is formed by deposition by the CVD method or the like, and the tip of the emitter formed in a later step becomes sharper.

Then, as shown in FIG. 2C, a W film is formed on the silicon oxide film 14 by a sputtering method to a thickness of 0.9 μm.
m is deposited to form the emitter electrode layer 13. In addition to W, a material such as a W layer, a Mo layer, or a Ta layer can be used as the emitter electrode layer 13.

Then, the ITO electrode layer 12 having a thickness of about 1 μm to be a cathode electrode is formed on the emitter electrode layer 13 by the sputtering method. The formation of the ITO electrode layer 12 can be omitted depending on the material of the emitter electrode layer 13. If the ITO layer 12 is not formed,
The emitter electrode layer 13 also serves as the cathode electrode.

Next, as shown in FIG. 2D, the quartz glass substrate 11 and the ITO layer 12 are bonded. For this adhesion, for example, an electrostatic adhesion method can be applied. The electrostatic adhesion method contributes to weight reduction and thickness reduction of the cold cathode device.

The emitter electrode layer 13 and the ITO electrode layer 13 previously formed on the quartz glass substrate 11 can be adhered to form this structure.

An aqueous solution containing ethylenediamine / pyrocatechol / pyrazine (ethylenediamine: 75
cc, pyrocatechol: 12 g, pyrazine: 3 mg,
The silicon single crystal substrate 17 is selectively removed with water: 10 cc) to expose the silicon oxide film 14. Up to this step, a protrusion 20 is formed in which a part of the emitter electrode layer 13 and the silicon oxide film 14 protrudes in a pyramid shape with respect to the flat surface of the silicon oxide film 14. The silicon single crystal substrate 17 is removed by mechanical force other than etching by the silicon oxide film 14 and the silicon single crystal substrate 1.
It can also be carried out by peeling 7 and 7.

Then, as shown in FIG. 2E, the gate electrode 16 is formed on the silicon oxide film 14 by the sputtering method.
Is formed until the tip of the convex portion 20 is covered.

Then, as shown in FIG.
Method is used to polish the gate electrode 16 to expose the tip of the convex portion 20 of the silicon oxide film 14. At this time, the polishing is performed while measuring the polishing end point using a laser or the like so that the emitter electrode layer 13 is not polished.

Then, as shown in FIG. 3 (g), NH ₄
The silicon oxide film 14 is selectively removed using an F / HF mixed solution. Through the above steps, the opening is formed in the gate electrode 16, the tip of the pyramid-shaped convex portion 20 of the emitter electrode layer 13 is exposed, and a pyramidal cold cathode, that is, an emitter is formed. It

According to the field emission cold cathode of this embodiment,
Since the gate electrode is thick, the wiring resistance is reduced and the signal delay can be suppressed. Further, when the gate electrode is polished to expose the silicon oxide film, etching or polishing can be performed without using a mask.

Further, since the thickness of the gate electrode is extremely large, the strength of the gate electrode is improved. Therefore, the displacement of the gate electrode with respect to the electric field induced stress is small, and the gate electrode and the emitter electrode layer are not electrically connected.

Furthermore, when the pillar or the focus electrode is formed on the cathode, the surface is flattened by CMP, which facilitates the manufacturing.

[Second Embodiment] FIG. 4 is a sectional view showing the structure of a field emission cold cathode according to the second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The feature of this embodiment is that the emitter electrode layer 35 is formed on the ITO electrode layer 12 with the core-shaped resistance layer 34 interposed therebetween. The emitter electrode layer 35 has a convex portion 33.
The core resistance layer 3 is formed separately from each other.
4 electrically connects to the ITO electrode layer 12.

Since the shape of the emitter electrode layer 35 may be different due to variations in manufacturing, the gate electrode 16
A large amount of current flows from the emitter electrode layer 35 having a short distance between the gate electrode 16 and the emitter electrode layer 3
There is a possibility that a short circuit will occur between the two. However, by inserting the core-shaped resistance layer 34 between the emitter electrode layer 35 and the ITO electrode layer 12, the current flowing from the ITO electrode layer 12 to the emitter electrode layer 35 can be limited and a short circuit can be suppressed.

The manufacturing process of the cold cathode shown in FIG. 4 will be described with reference to the process sectional views of FIGS. FIG. 5 (a),
Since (b) is the same as the step shown in FIGS. 2A and 2B of the second embodiment, description thereof will be omitted. And
As shown in FIG. 5C, an electrode material is deposited on the silicon oxide film 14. Then, after forming a resist (not shown) on the electrode material in the region including the recess 18, the electrode material is etched by RIE using the resist as a mask to form the emitter electrode layer 35, and the resist is removed.

Next, as shown in FIG. 5D, a core resistance layer 34 is deposited on the silicon oxide film 14 and the emitter electrode layer 35. Then, ITO is formed on the core resistance layer 34.
The electrode 12 is formed.

Next, as shown in FIG. 5E, after the quartz glass substrate 11 and the cathode electrode are bonded together, the silicon single crystal substrate 17 is removed as in the second embodiment. Up to this step, the emitter electrode layer 35 and the silicon oxide film 1
A convex portion 20 is formed in which a part of 4 protrudes in a pyramid shape with respect to the flat surface of the silicon oxide film 14.

Next, as shown in FIG. 5F, the gate electrode 16 is formed on the silicon oxide film 14 by the sputtering method.
Is formed until the tip of the convex portion 20 is covered.

Then, as shown in FIG. 6 (g), CMP is performed.
The gate electrode 16 is polished by using the
The silicon oxide film 14 at the tip of 0 is exposed. Then, as shown in FIG. 6H, the silicon oxide film 14 is selectively removed using an NH ₄ F / HF mixed solution. Through the above steps, an opening is formed in the gate electrode 16 and the emitter electrode layer 3 is formed in a pyramid shape.
The tip of 5 is exposed to form a pyramidal cold cathode, that is, an emitter.

According to the present embodiment, by inserting the core-shaped resistance layer between the emitter electrode layer and the ITO electrode, the current flowing from the ITO electrode to the emitter electrode layer can be limited and the short circuit can be suppressed.

[Third Embodiment] FIG. 7 is a sectional view showing the structure of an FEA (Field Emission Array) according to the third embodiment of the present invention. 7, parts that are the same as those shown in FIG. 5 are given the same reference numerals, and descriptions thereof will be omitted.

The feature of this embodiment is that the projection 2 has a sharp tip.
The structure base body 43 (43a to 43d) in which a plurality of emitter electrode layers 35 having 0 are formed is arranged on the quartz glass substrate 4
1, a cathode electrode 42a formed in the row direction,
Two-dimensionally arranged on b in close contact with each other in the row direction and the column direction. The gate electrodes 44a and 44b are formed on the structural base body 43 along the column direction.

FIG. 7 is an enlarged view of the joint portion of the structural bases 43a to 43d.
Many emitter electrode layers 35 are formed in the portions other than the illustrated portion. Further, although one structural base is arranged at the intersection of the cathode electrode 42 and the gate electrode 44, the cathode electrode 42 is provided on one structural base.
And a plurality of intersecting portions of the gate electrode 44 are formed.

The manufacturing process of this cold cathode will be described with reference to the process diagrams of FIGS.

First, as shown in FIG. 8A, a plurality of emitter electrode layers 35 are formed by using the steps shown in FIGS. 5A to 5D of the second embodiment, and then the core-shaped resistor is formed. Structural bases 43a to 43d on which the layer 34 has been formed and patterned are prepared. Further, a quartz glass substrate 41 having cathode electrodes 42a and 42b formed on the surface along the row direction is prepared.

Next, as shown in FIG. 9B, the structural bases 43a to 43d and the cathode electrode 42 of the quartz glass substrate 41.
The surface on which a and b are formed is bonded so that the emitter electrode layer 35 is interposed. That is, the core resistance layer 34 and the cathode electrodes 42a and 42b are adhered.

Then, as shown in FIG. 9C, an aqueous solution containing ethylenediamine / pyrocatechol / pyrazine (ethylenediamine: 75 cc, pyrocatechol: 12).
g, pyrazine: 3 mg, water: 10 cc) to selectively remove the silicon single crystal substrate 17 by etching to expose the silicon oxide film 14. Up to this step, a plurality of protrusions are formed in which a part of the emitter electrode layer 35 and the silicon oxide film 14 protrudes in a pyramid shape with respect to the flat portion of the silicon oxide film 14.

Next, as shown in FIG. 10D, after depositing the gate electrode 44 covering the convex portion on the silicon oxide film 14, the gate electrode 44 is polished by the CMP method to form the convex portion. Of the silicon oxide film 14 is exposed. At this time, if the gate electrode is deposited so that the gate electrode is embedded in the gap between the adjacent structural bases, the gate electrode is not interrupted.

Then, as shown in FIG. 10E, the gate electrode 44 is patterned to form the gate electrodes 44a and 44b along the column direction, and then the silicon oxide film 14 is selectively etched to obtain the tip. Sharp emitter electrode layer 35
The FEA is formed by exposing the.

It is also possible to selectively etch the silicon oxide film 14 and then pattern the gate electrode 44 to form the electrodes 44a and 44b along the column direction.

According to this embodiment, the gate electrode is deposited, CMP, and patterned after tiling the structural substrate before forming the gate electrode on the cathode electrode, so that the gate electrode is formed between the adjacent structural substrates. Since the possibility of cutting is small, a large area FEA can be formed at lower cost.

[Fourth Embodiment] FIG. 11 shows a fourth embodiment of the present invention.
It is sectional drawing which shows the structure of the field emission type cold cathode concerning embodiment. 11, parts that are the same as those shown in FIG. 7 are given the same reference numerals, and descriptions thereof will be omitted.

The feature of the field emission cold cathode of this embodiment is that
The gate electrode connection layer 51 (51a, b) is the gate electrode 4
4 (44a, b). Each of the gate electrode connection layers 51 has an adjacent structure base 43.
Is selectively formed on the gate electrode 44 located in the region including the junction portion of the. By forming the gate electrode connection layer 51, the gate electrode can be surely electrically connected.

FIG. 12 shows the manufacturing process of the FEA shown in FIG.
This will be described with reference to the process chart of FIG. First, as shown in FIG. 12A, with respect to the structure formed through the steps shown in FIGS. 8A to 10D, the gate of the region including the bonding portion of the adjacent structural base 43 is formed. Gate electrode connection layers 51a and 51b are formed on the electrodes 44 by screen printing.

Next, as shown in FIG. 12B, the gate electrode 44 is patterned. Then, as described above, the FEA shown in FIG. 11 is completed by selectively removing the silicon oxide film 14.

The gate electrode connection layer 51 may be formed after the patterning of the gate electrode 44. The formation of the gate electrode connection layer 51 is not limited to the screen printing method, and the electrode material may be deposited and then patterned.

[Fifth Embodiment] FIG. 13 shows the fifth embodiment of the present invention.
It is sectional drawing which shows the structure of FEA concerning embodiment. 13, the same parts as those in FIG. 7 are designated by the same reference numerals,
The description is omitted.

The feature of this embodiment is that the structure base 6 adjacent to each other is used.
Glass, SOG (Spin On Gl) is formed in the gap 62 between 1a and 1b.
an insulating layer 63 made of silicon oxide or silicon oxide. Since the insulating layer 63 is embedded in the gap 62, when the gate electrodes 44a and 44b are formed, the gate electrode 44 and the cathode electrode 42 are formed in the joint gap 62 of the structural base 61.
This prevents the gate electrode 44 and the cathode electrode 42 from being short-circuited and prevents the gate electrode 44 and the cathode electrode 42 from being short-circuited.

The manufacturing process of the FEA shown in FIG. 13 is shown in FIG.
It demonstrates using the process drawing of No. 4,15.

First, the structure shown in FIG. 14A is formed through the steps shown in FIGS. 8A to 9C described above. As shown, the structural substrate 61a
There is a gap 62 between the structure and the structural base 61b.

Next, as shown in FIG. 14B, the insulating layer 63 is filled so as to fill the gap 62 between the substrates 61a and 61b.
To form.

Then, as shown in FIG. 15C, the insulating layer 62 on the silicon oxide film 14 is removed by an etch back method or the like, and the insulating layer is filled in the gap 62. In addition,
It is not necessary to fill the entire gap 62 with the insulating layer 63,
It may be formed so as to close the opening of the gap 62.

Then, as shown in FIG.
After forming the gate electrodes 44a and 44b as in the embodiment,
By selectively removing the silicon oxide film 14, F
EA is completed.

[Sixth Embodiment] FIG. 16 shows a sixth embodiment of the present invention.
It is a perspective view showing the composition of FEA concerning an embodiment. 16, the same parts as those in FIG. 7 are designated by the same reference numerals,
The description is omitted.

The feature of the FEA of this embodiment is that the insulating layer 71 is formed below the bonding portion of the adjacent structural base body 43. Since the insulating layer 71 is formed under the junction between the adjacent structural bases 43, the gate electrode 44
The gate electrode 44 in the gap formed at the junction when the gate electrode is formed.
Is formed, and the gate electrode 44 and the cathode electrode 42 are not electrically connected.

The manufacturing process of the FEA shown in FIG. 16 will be described with reference to the process charts of FIGS.

First, as shown in FIG. 17A, a plurality of emitter electrode layers 35 are formed by using the steps shown in FIGS. 5A to 5D of the third embodiment, and then the core-shaped resistor is formed. Structural bases 43a to 43d on which the layer 34 has been formed and patterned are prepared. Further, the structural substrate 70 in which the cathode electrodes 42a, 42b and the insulating layer 71 are formed on the quartz glass substrate 41 is prepared. The insulating layer 71 will be formed on the structural substrate 70 in a later step.
When tiling the structural substrate 43 on top, the adjacent substrate 4
It is formed at a portion in contact with the joint portion 3.

Then, as shown in FIG. 18B, the surface of the structural base bodies 43a to 43d on which the core-shaped resistance layer 34 is formed and the surface of the substrate 70 on which the cathode electrodes 42a and 42b are formed are bonded. To do. At this time, the tiling is performed so that the bonding portion of the adjacent structural base body 43 is always present on the insulating layer 71.

Then, as shown in FIG. 18C, the silicon single crystal substrate 17 is removed, the gate electrode 44 is deposited,
The FEA is completed by polishing and patterning and etching the silicon oxide film 14.

[Seventh Embodiment] FIGS. 19 and 20 are process sectional views showing a manufacturing process of a field emission type cold cathode according to a seventh embodiment of the present invention.

First, as shown in FIG. 19A, a plurality of emitter electrode layers 35 are formed by using the temporary support substrate 81 and the steps shown in FIGS. 5A to 5D of the third embodiment. After that, the structural base bodies 43a to 43d on which the core resistance layer 34 is formed and patterned are prepared. Then, the support substrate 81 and the silicon substrate 17 surface of the structural bases 83a to 83d are temporarily bonded.

Next, as shown in FIG. 19B, the cathode electrodes 83a and 83b are formed on the cored resistance layer 34 along the row direction by screen printing. The structural base body before patterning the core resistance layer 34 (FIG. 6C)
Is temporarily adhered to the temporary support substrate 81, and then the core resistance layer 34 is formed.
The cathode electrode 83 may be deposited on the core resistance layer 34 and the cathode electrode 83 may be patterned.

Next, as shown in FIG. 20C, the cathode electrodes 83a and 83b and the quartz glass substrate 84 are bonded. Then, the temporary support substrate 81 and the silicon single crystal substrate 1
By removing 7, a structure similar to that shown in FIG. 9C is formed. In the subsequent steps, the FEA is completed by performing the same steps as those shown in FIGS. 9C to 10E.

[Eighth Embodiment] FIG. 21 shows an eighth embodiment of the present invention.
It is a perspective view showing the composition of FEA concerning an embodiment. 21, the same parts as those in FIG. 7 are designated by the same reference numerals,
The description is omitted.

The feature of this embodiment is that the cathode electrode connecting conductive layer 92a is formed under the cathode electrode 83 (83a, b) which is in contact with the adjacent structural base and the junction.

By forming the cathode electrode connecting conductive layer 92, electrical connection of the cathode electrode 83 between the adjacent structural bases 83 can be ensured.

FIG. 22 shows the manufacturing process of the FEA shown in FIG.
This will be described with reference to the process chart of FIG.

First, a plurality of structures formed through the steps shown in FIGS. 21A and 21B are prepared. Then, a quartz glass substrate 91 having cathode electrode connection electrode layers 92a and 92b formed on its surface is prepared. The cathode electrode connecting conductive layer 92 on the quartz glass substrate 41 is formed on the glass substrate 41 facing the intersection of the cathode electrode 83a and the junction of the adjacent structural bases.

Next, after adhering the cathode electrode connecting conductive layer 92 and the cathode electrode 83, the supporting substrate 81 and the silicon substrate 17 are removed, and the gate electrode is deposited, polished and patterned, and the silicon oxide film 14 is etched. The FEA is completed by.

The present invention is not limited to the above embodiment. For example, using the above-mentioned FEA, FE
It is also possible to form a D (Field Emission Display) or electron beam exposure apparatus.

The material for the emitter electrode layer is not limited to tungsten, but various materials having a low work function can be used.

The gate electrode can be deposited not only by the sputtering method but also by the vapor deposition method, the printing method or the electroplating method.

Besides, the present invention can be variously modified and implemented without departing from the gist thereof.

[0111]

As described above, according to the present invention, since the thickness of the gate electrode is large, the resistance of the gate wiring is low and the signal delay does not occur. Further, since the gate electrode is thick, the electric field-induced stress prevents the gate electrode and the emitter from coming into contact with each other to be electrically connected.

Further, by tiling a plurality of structural bases on the substrate on which the cathode electrode is formed, and depositing and CMP of the gate electrode, it is possible to form the gate electrode continuously, and the adjacent structure is formed. The gate electrode is not broken between the substrates.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a field emission cold cathode according to a first embodiment.

2A to 2D are process cross-sectional views showing a manufacturing process of the field emission cold cathode shown in FIG.

3A to 3D are process cross-sectional views showing a manufacturing process of the field emission cold cathode shown in FIG.

FIG. 4 is a sectional view showing the structure of a field emission cold cathode according to a second embodiment.

5A to 5C are process cross-sectional views showing the configuration of the field emission cold cathode shown in FIG.

6A to 6C are process cross-sectional views showing the structure of the field emission cold cathode shown in FIG.

FIG. 7 is a perspective view showing the structure of a field emission cold cathode according to a third embodiment.

8 is a perspective view showing a manufacturing process of the field emission cold cathode shown in FIG.

FIG. 9 is a perspective view showing the configuration of FEA according to the fourth embodiment.

10 is a perspective view showing a manufacturing process of the FEA shown in FIG.

11 is a perspective view showing a manufacturing process of the FEA shown in FIG.

12 is a perspective view showing a manufacturing process of the FEA shown in FIG.

FIG. 13 is a perspective view showing a configuration of FEA according to the fifth embodiment.

14 is a perspective view showing the configuration of the FEA shown in FIG.

FIG. 15 is a perspective view showing the configuration of FEA according to the sixth embodiment.

16 is a perspective view showing a manufacturing process of the FEA shown in FIG.

FIG. 17 is a perspective view showing a manufacturing process of the FEA shown in FIG.

FIG. 18 is a perspective view showing the configuration of FEA according to the seventh embodiment.

19 is a perspective view showing the configuration of the FEA shown in FIG.

20 is a perspective view showing the configuration of the FEA shown in FIG.

FIG. 21 is a perspective view showing a manufacturing process of the FEA according to the eighth embodiment.

22 is a perspective view showing a manufacturing process of the FEA shown in FIG. 21. FIG.

[Explanation of symbols]

11 ... Quartz glass substrate 12 ... ITO electrode layer (cathode electrode) 13 ... Emitter electrode layer 14 ... Silicon oxide film 16 ... Gate electrode 17 ... Silicon single crystal substrate 18 ... Recess 19 ... Al layer 20 ... Projection 21 ... Resist 34 ... Core resistance layer 35 ... Emitter electrode layer 41 ... Quartz glass substrate 42a, b ... Cathode electrodes 43a-d ... Structural substrate 44a, b ... Gate electrode 51a, b ... Conductive layer for connecting gate electrode 61 ... Structural substrate 62 ... Gap 63 ... Insulating layer 71 ... Insulation separation layer 81 ... Support substrate 83a, b ... Cathode electrodes 92a, b ... Conductive layer for connecting cathode electrode

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Claims (14)

(57) [Claims] 1. A plurality of cathode electrodes formed in an array on an insulating substrate along the row direction, and a projection having a sharp tip and electrically connected to the cathode electrodes are provided in the row and column directions.
A field emission cold cathode including a three-dimensionally arranged emitter electrode layer and a plurality of gate electrodes arranged along the column direction, each of which draws out electrons from the tip of each protrusion and has an opening on the tip. The emitter electrode layer is formed on each of a plurality of structural bases closely arranged on the cathode electrode, and the tip region of each protrusion is removed on the emitter electrode layer of each structural base. An insulating layer is formed along the surface of the electrode layer, and the gate electrode is continuously formed on the insulating layer of the structural base adjacent in the column direction, and the surface is flat. Type cold cathode. 2. A gate electrode connecting conductive layer is selectively formed on the gate electrode in a region including a crossing portion between a junction of adjacent structural bases and each gate electrode. 1. The field emission cold cathode according to 1. 3. The field emission type cold cathode according to claim 1, wherein a first isolation insulator is formed in a gap between adjacent structural bases to close an opening of the gap. 4. The field emission type cold cathode according to claim 1 , wherein a joint portion between adjacent structural bases is formed on a second isolation insulator formed on the insulating substrate. . 5. The field emission type cold cathode according to claim 1 , wherein a cathode electrode connecting conductive layer is formed below the cathode electrode in a region including a joint portion between adjacent structural bases. 6. A step of forming a plurality of concave portions having a sharp bottom in a mold substrate, a step of forming an insulating layer on the mold substrate, and a step of forming an emitter electrode layer on the insulating layer. The step of forming a plurality of structural bases to be formed and the respective structural bases and the cathode electrodes formed along the row direction on the insulating substrate are interposed by the emitter electrode layer, and the adjacent structural bases are in close contact with each other. And the step of adhering each mold substrate, the emitter electrode layer and the insulating layer formed in the recess are protruded with respect to the flat portion of the insulating layer, and a plurality of protrusions having sharp tips are formed. The step of exposing the portion, the step of forming a gate electrode material covering the tip of the convex portion on the insulating layer, and the surface of the gate electrode material is etched or polished substantially uniformly to insulate the convex portion. Exposed layers And a step of patterning the gate electrode material to form a plurality of gate electrodes along the column direction and selectively etching the exposed insulating layer to expose a convex portion of the emitter electrode layer having a sharp tip. A method for manufacturing a field emission cold cathode, comprising: 7. The field emission type cold cathode according to claim 6 , wherein before the step of forming the gate electrode, a first isolation insulator for closing a gap between adjacent structural substrates is formed. Manufacturing method. 8. After the surface of the gate electrode is etched or polished substantially uniformly, the gate electrode is selectively connected to the gate electrode in the region including the intersection between the junction of the adjacent structural bases and the gate electrode. 7. The method for manufacturing a field emission cold cathode according to claim 6 , wherein a conductive layer is formed. 9. When adhering the respective structural bases to the cathode electrode formed on the insulating substrate, the bonding portion of the adjacent structural bases is formed on the second isolation insulator formed on the insulating substrate. A contract characterized by being formed into
7. The method for manufacturing a field emission cold cathode according to claim 6 . 10. A process comprising: forming a plurality of concave portions having a sharp bottom on a mold substrate; forming an insulating layer on the mold substrate; and forming an emitter electrode layer on the insulating layer. Forming a plurality of structural substrates described above, arranging the structural substrates on a supporting substrate by contacting each mold substrate with the supporting substrate and adhering the adjacent structural substrates to each other, and the emitter electrode layer A step of forming a cathode electrode on the substrate in a row direction; a step of adhering the cathode electrode and a structural substrate; a step of removing the support substrate and the mold substrate; and the emitter electrode layer formed in the recess And an insulating layer exposing a plurality of protrusions protruding with respect to a flat portion of the insulating layer; and a step of forming a gate electrode material on the insulating layer, the gate electrode material covering a tip of the protrusion, Previous A step of etching or polishing the surface of the gate electrode material substantially uniformly to expose the insulating layer of the convex portion; and patterning the gate electrode material to form a plurality of gate electrodes along the column direction, and exposing the exposed insulating layer And a step of selectively etching the layer to expose a convex portion of the emitter electrode layer having a sharp tip, a method for manufacturing a field emission cold cathode. 11. The structural substrate is formed of an insulating substrate and a cathode electrode connecting conductive layer formed on the insulating substrate, and a junction of a structural base adjacent to the cathode electrode conductive connecting layer and the cathode. 11. The method for manufacturing a field emission cold cathode according to claim 10 , wherein the cathode electrode and the structural substrate are bonded so that an intersection with the electrode is located. 12. The method for manufacturing a field emission cold cathode according to claim 6, wherein the mold substrate is a silicon single crystal substrate. Upon 13. polishing the gate electrode material, or claim 6, characterized by using a chemical mechanical polishing method
10. The method for manufacturing a field emission cold cathode according to 10 . 14. The method according to claim 6, wherein the gate electrode material is formed by a printing method or an electroplating method.
10. The method for manufacturing a field emission cold cathode according to 10 .