JP3559440B2 - Field emission cold cathode and method of manufacturing the same - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a field emission cold cathode and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, field emission cold cathodes utilizing Si semiconductor processing technology have been actively developed.
[0003]
The field emission cold cathode is formed of a conical or pyramid-shaped emitter formed on a cathode electrode, and a gate electrode for extracting electrons from the tip of the emitter electrode layer.
[0004]
Field emission cold cathode formation methods are roughly classified into two, a Spindt method and a transfer molding method. When formed by the Spindt method, a gate electrode is formed on an insulating layer formed so as to surround a conical emitter. Further, when formed by a transfer molding method, a gate electrode is formed via an insulating film formed on a side surface of the emitter.
[0005]
When a voltage difference is applied between the gate electrode and the emitter to extract electrons from the conical emitter, abnormal discharge occurs due to shape non-uniformity, etc., and electric field induced stress occurs between the gate electrode and the emitter. Works, and the gate electrode and the emitter come into electrical contact with each other to cause a short circuit, so that there is a problem that electrons are not emitted from the emitter.
[0006]
In addition, a technology has been reported in which a small field emission array (FEA) in which field emission cold cathodes are two-dimensionally arranged in a row direction and a column direction is formed by tiling on a substrate. However, there is a problem that it is difficult to electrically connect a gate electrode formed on a small FEA.
[0007]
A technique has been reported in which adjacent gate electrodes are electrically connected using wire bonding to form a large-area FEA. However, the use of wire bonding has a problem that the manufacturing cost is high.
[0008]
[Problems to be solved by the invention]
As described above, the conventional field emission cold cathode has a problem that the gate electrode and the emitter come into contact with each other due to the electric field-induced stress, causing a short circuit, so that electrons are not emitted from the emitter.
[0009]
Further, conventionally, there has been a problem that a large-area FEA cannot be manufactured at low cost.
[0010]
SUMMARY OF THE INVENTION It is an object of the present invention to prevent a short circuit between a gate electrode and an emitter, to improve reliability, and to easily and inexpensively manufacture a large-area FEA. And a method for producing the same.
[0011]
[Means for Solving the Problems]
[Constitution]
The present invention is configured as described below to achieve the above object.
[0014]
(1The field emission cold cathode according to the present invention has a plurality of cathode electrodes arrayed and formed on an insulating substrate along a row direction, and a convex portion, which is electrically connected to the cathode electrodes and has a sharp tip, is formed in the row direction. An emitter electrode layer two-dimensionally arranged in a column direction, a plurality of emitter electrode layers formed along the column direction, extracting electrons from the tips of the respective projections, and a gate electrode having an opening on the tips of the projections; Wherein the emitter electrode layer is formed on each of a plurality of structural bases closely arranged on the cathode electrode, and the electrode is formed on the emitter electrode layer of each structural base. An insulating layer formed along the surface of the layer and having the tip region of the protrusion removed; and an array formed on the insulating layer along the column direction and having an opening in the tip region of the protrusion. Rigid layers are sequentially laminated, and It is characterized in that it is continuously formed on the rigid layer of the structure body adjacent to each other in the column direction.
[0015]
Preferred embodiments of the invention described in the configuration (3) are shown below.
[0016]
A gate electrode connection conductive layer is selectively formed on the gate electrode in a region including the intersection between the junction of the adjacent structural base and each gate electrode.
[0017]
A cathode electrode connecting conductive layer is formed below the cathode electrode in a region including a junction between adjacent structural bases.
[0018]
Preferred embodiments of the invention described in the constitutions (2) and (3) are shown below.
[0019]
A first isolation insulator that covers an opening of the gap is formed in a gap between adjacent structural bases.
[0020]
The joint between adjacent structural bases is formed on a second isolation insulator formed on the insulating substrate.
[0021]
Constitution(1The preferred embodiments of the invention described in (1) are shown below.
[0022]
The etching stop layer is silicon doped with impurities.
[0023]
The surface of the etching stop layer is flat.
[0028]
(2The method for manufacturing a field emission cold cathode according to the present invention includes the steps of: forming a plurality of concave portions having sharp bottoms on a mold substrate; forming a rigid etching stop layer on the mold substrate; Forming a plurality of structural bases including a step of forming an insulating layer on the stop layer, and a step of forming an emitter electrode layer on the insulating layer; and forming each of the structural bases on the insulating substrate. A step of arranging and adhering a plurality of cathode electrodes formed along the row direction, arranging the respective structural bases so that the emitter electrode layer is interposed, and adjoining the adjacent structural bases; Etching, the emitter electrode layer, the insulating layer and the etching stop layer formed in each concave portion project from a flat portion of the etching stop layer, and a plurality of convex portions having sharp tips are formed. Exposing, forming a plurality of gate electrodes having openings at the tips of the respective protrusions on the etching stop layer of the arranged structural base in the column direction, and forming the tips of the respective protrusions Removing the etching stop layer and the insulating layer formed on the substrate to expose the emitter electrode layer having a sharp tip.
[0029]
(3The method for manufacturing a field emission cold cathode according to the present invention includes a step of forming an etching stop layer made of a rigid body on a mold substrate, the method having an opening in the etching stop layer, and the mold substrate having a sharp bottom. Forming a plurality of concave portions, forming an insulating layer on the mold substrate and the etching stopper layer, and forming an emitter electrode layer on the insulating layer. Forming each of the structural bases and a plurality of cathode electrodes formed in a row direction on the insulating substrate so that the emitter electrode layer is interposed and the adjacent structural bases are in close contact with each other. Arranging and adhering the bases, etching each mold substrate, and forming the emitter electrode layer, the insulating layer and the etching stop layer formed in each concave portion by the etching; A step of exposing a plurality of projections having a sharp tip protruding from a flat portion of the stop layer, and a gate having an opening at the tip of each projection on the etching stop layer of the arrayed structural base. Forming a plurality of electrodes in the column direction, and removing the etching stop layer and the insulating layer formed at the tips of the respective protrusions to expose the emitter electrode layer having a sharp tip. Features.
[0030]
Constitution(2), (3The preferred embodiments of the invention described in (1) are shown below.
[0031]
Before the step of forming the gate electrode, a first isolation insulator for closing an opening in a gap between adjacent structural bases is formed.
[0032]
The first isolation insulator is glass, SOG (spin-on-glass), silicon oxide, or silicon nitride.
[0033]
After forming the gate electrode, a gate electrode connection conductive layer is selectively formed on the gate electrode in a region including a junction between the adjacent structural base and the gate electrode.
[0034]
When each structural base is bonded to the cathode electrode formed on the insulating substrate, a joint between adjacent structural bases is formed on the second isolation insulator formed on the insulating substrate.
[0035]
(4The method for manufacturing a field emission cold cathode according to the present invention includes a step of forming a plurality of concave portions having a sharp bottom in a mold substrate; a step of forming a rigid etching stop layer on the mold substrate; Forming an insulating layer on the layer;Insulating layerForming a plurality of structural bases including a step of forming an emitter electrode layer thereon; and forming each of the structural bases on a supporting substrate, wherein each mold substrate and the supporting substrate are in contact with and adjacent to each other. Arranging the substrates in close contact with each other, forming a plurality of cathode electrodes along the row direction on the emitter electrode layer, bonding the cathode electrodes to a structural substrate, The mold substrate is removed, and the emitter electrode layer, the insulating layer, and the etching stop layer formed in each of the recesses protrude from a flat portion of the etching stop layer and form a plurality of sharp protrusions having sharp tips. Exposing; and forming a plurality of gate electrodes having openings at the tips of the respective protrusions in the column direction on the etching stop layers of the arranged structural bases. It formed at the tip portion of the protrusionetchingRemoving the stop layer and the insulating layer and exposing the projection of the emitter electrode layer having a sharp tip.
[0036]
(5The method for manufacturing a field emission cold cathode according to the present invention includes a step of forming an etching stop layer made of a rigid body on a mold substrate, an opening in the etching stop layer, and a bottom of the mold substrate having a sharp bottom. Forming a plurality of structural bases including a step of forming a recess, a step of forming an insulating layer on the mold substrate and the etching stop layer, and a step of forming an emitter electrode layer on the insulating layer A step of arranging the respective structural bases on a supporting substrate such that each mold substrate and the supporting substrate are in contact with each other and the adjacent structural bases are in close contact with each other; Forming a plurality of lines along the line, bonding the cathode electrode to the structural substrate, removing the support substrate and the respective mold substrates, and forming Exposing the emitter electrode layer, the insulating layer, and the etching stop layer to a flat portion of the etching stop layer, thereby exposing a plurality of sharp projections, and stopping the etching of the arranged structural base. Forming a plurality of gate electrodes having openings at the tips of the respective protrusions in the column direction on the layer, and forming the gate electrodes at the tips of the respective protrusions.etchingRemoving the stop layer and the insulating layer and exposing the projection of the emitter electrode layer having a sharp tip.
[0037]
Constitution(4), (5The preferred embodiments of the invention described in (1) are shown below.
[0038]
The structural substrate is formed from an insulating substrate and a cathode electrode connecting conductive layer formed on the insulating substrate, and a junction between the adjacent structural base on the cathode electrode conductive connecting layer and the cathode electrode has an intersection. The cathode electrode and the structural substrate are bonded so as to be positioned.
[0039]
Constitution(2) ~ (5The preferred embodiments of the invention described in (1) are shown below.
[0040]
The mold substrate is a silicon single crystal substrate, and the etching stop layer is formed by doping the mold substrate with an impurity.
[0041]
The gate electrode is formed by a printing method, an electroplating method, a vapor deposition method, or a sputtering method.
[0042]
[Action]
The present invention has the following operations and effects by the above configuration.
[0043]
Since the gate electrode is formed on the insulating layer via the rigid layer, the gate electrode is not displaced even if it acts on the electric field induced stress. Therefore, since the gate electrode and the emitter do not come into contact with each other, electrons are reliably emitted from the emitter, and reliability can be improved.
[0044]
In addition, a plurality of structural bases on which a plurality of emitters are formed are closely attached and two-dimensionally arranged (tiling) such that tiles are attached, and a gate electrode or a cathode electrode is formed. Since there is no possibility that electrical connection cannot be established due to the cutting, an FEA having a large area can be easily formed. Further, the productivity can be significantly improved.
[0045]
Also,At the time of tiling, the insulating layer, the etching stop layer, and the mold substrate are formed on the protruding portion having a sharp tip. Therefore, the tip of the emitter is protected, and handling of each structural base is easy.
[0046]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0047]
[First Embodiment]
FIG. 1 is a cross-sectional view showing a configuration of a field emission cold cathode according to the first embodiment of the present invention.
[0048]
An emitter electrode layer 13 is formed on a glass substrate 11 via an ITO electrode layer (cathode electrode) 12. A part of the emitter electrode layer 13 is formed with a protrusion 20 projecting in a pyramid shape with respect to the plane thereof. A silicon oxide film 14 is formed on emitter electrode layer 13. The silicon oxide film 14 is formed except for the tip of the projection 20, and the tip of the projection 20 is exposed. A gate electrode 16 made of a tungsten film is formed on the silicon oxide film 14 via a diffusion layer 15 (etching stop layer) in which boron is doped in silicon.
[0049]
Next, a manufacturing process of the field emission cold cathode shown in FIG. 1 will be described with reference to perspective views of FIGS.
[0050]
First, as shown in FIG. 2A, an inverted pyramid-shaped recess 18 having a sharpened bottom is formed on one surface of a p-type (001) silicon single crystal substrate (mold substrate) 17. As a method of forming the concave portion 18 in the silicon single crystal substrate 17, there is a method utilizing anisotropic etching of the silicon single crystal substrate.
[0051]
That is, first, a silicon oxide film having a thickness of 0.1 μm is formed on the surface of a silicon single crystal substrate having a (100) crystal orientation by a dry oxidation method, and a resist is applied by a spin coating method. Next, after patterning is performed on the resist so that an opening of, for example, 0.8 μm is obtained, NH 3 is formed using the resist as a mask.₄The silicon oxide film is selectively etched by the F / HF mixed solution. After removing the resist, anisotropic etching is performed on the silicon single crystal substrate using a 30 wt% KOH aqueous solution using the silicon oxide film as a mask. Formed on a crystal substrate.
[0052]
Next, the surface of the silicon single crystal substrate 17 is 3 × 10¹⁹cm^-3Boron is doped to the above concentration to form a diffusion layer (rigid layer) 15 having a thickness of 0.3 μm and serving as an etching stop layer.
[0053]
Next, as shown in FIG. 2B, a silicon oxide film (insulating layer) 14 having a thickness of about 0.2 μm is formed on the surface of the diffusion layer 15 by using a dry oxidation method. Note that the silicon oxide film 14 can also be formed by depositing silicon oxide by a CVD method or the like.
[0054]
Since the silicon oxide film formed by thermal oxidation is dense and easily controlled in thickness, it is preferable to form the silicon oxide film by thermal oxidation. By controlling the thickness of the silicon oxide film, the distance between the gate electrode and the emitter formed later can be accurately adjusted.
[0055]
Further, when the silicon oxide film 14 is formed by thermal oxidation, the tip of the bottom of the recess 18 becomes sharper due to the growth of the silicon oxide film 14 inside the recess 18 than when silicon oxide is formed by deposition. The tip of the emitter formed in a later step becomes sharper.
[0056]
Next, as shown in FIG. 2C, a W film is deposited to a thickness of 0.9 μm on the silicon oxide film 14 by a sputtering method to form an emitter electrode layer 13. In addition, other than W, a material such as Mo or Ta can be used for the emitter electrode layer 13.
[0057]
Next, on the emitter electrode layer 13, an ITO electrode layer 12 having a thickness of about 1 μm to be a cathode electrode is formed by a sputtering method. The formation of the ITO electrode layer 12 can be omitted depending on the material of the emitter electrode layer 13. When the ITO electrode layer 12 is not formed, the emitter electrode layer 13 also serves as a cathode electrode.
[0058]
Next, as shown in FIG. 2D, a 1 mm-thick quartz glass substrate 11 having an Al layer 19 having a thickness of 0.4 μm formed on one surface was prepared as an insulating substrate. The electrode layer 12 is bonded. For this bonding, for example, an electrostatic bonding method can be applied. The electrostatic bonding method contributes to a reduction in the weight and thickness of the cold cathode device.
[0059]
Next, as shown in FIG. 2E, the Al layer 19 formed on the surface of the glass₃・ CH₃After selective removal using a mixed acid solution of COOH and HF, a silicon single crystal substrate was prepared using an aqueous solution composed of ethylenediamine, pyrocatechol, and pyrazine (ethylenediamine: 75 cc, pyrocatechol: 12 g, pyrazine: 3 mg, water: 10 cc). 17 is selectively removed by etching to expose the diffusion layer 15. Up to this step, a projection 20 is formed in which a part of the emitter electrode layer 13, the silicon oxide film 14, and the diffusion layer 15 protrudes in a pyramid shape with respect to the flat portion of the diffusion layer 15.
[0060]
When etching the Si single crystal substrate 17, the diffusion layer 15 having a thickness of 0.3 μm has a role of an etching stop layer for terminating the erosion by the above-mentioned etching solution, and at the same time, serves as the emitter electrode layer 13 having a sharp tip. It serves to protect the projections 20 from erosion of the etching solution. Therefore, even when the thickness of the silicon oxide film 14 is small, the emitter electrode layer 13 can be protected from the erosion of the etching solution, and the field emission efficiency from the tip of the projection 20 and its uniformity can be greatly improved.
[0061]
Next, as shown in FIG. 3F, a tungsten layer is deposited to a thickness of 0.5 μm on the diffusion layer 15 by using a sputtering method, and a gate electrode 16 is formed. Note that the boron concentration of the diffusion layer 15 is, for example, 10²⁰-10²¹cm^-3High and the resistivity is 10^-4When the resistance is as low as Ω · cm, the diffusion layer 15 also plays a role of a gate electrode, and greatly contributes not only to reduction in the number of steps and cost but also to reduction in the distance between the gate and the emitter.
[0062]
Next, as shown in FIG. 3G, a photoresist 21 is applied on the gate electrode 16 by using a spin coating method, and a photoresist 21 of about 0.9 μm is formed on the tip of the pyramid-shaped protrusion 20. To be formed.
[0063]
Next, as shown in FIG. 3H, the surface layer of the resist layer 21 is removed by dry etching using oxygen plasma so that the tip of the projection 20 appears by about 0.7 μm. Then, the gate electrode 16 and the diffusion layer 15 at the tip of the projection 20 are etched using the reactive ion etching method.
[0064]
Next, as shown in FIG. 3I, after the resist 21 is removed, NH 3 is removed.₄The silicon oxide film 14 is selectively removed using a mixed solution of F and HF. Through the above steps, an opening is formed in the gate electrode 16 and the tip of the projection 20 of the emitter electrode layer 13 is exposed, so that a pyramid-shaped cold cathode, that is, an emitter is formed.
[0065]
Note that, without forming the ITO electrode layer on the emitter electrode layer, the ITO electrode layer and the emitter electrode layer formed on quartz glass in advance can be bonded to each other.
[0066]
According to the present embodiment, since the gate electrode is formed from the diffusion layer made of a rigid body, there is no short circuit between the gate electrode and the projection of the emitter electrode layer.
[0067]
The gate wiring is formed of two layers, that is, a gate electrode and a diffusion layer, and has a lower resistivity than in the related art. Therefore, the signal delay can be suppressed when the area is increased.
[0068]
[Second embodiment]
FIG. 4 is a sectional view showing the configuration of a field emission cold cathode according to the second embodiment of the present invention. 4, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
[0069]
The feature of this embodiment is that the n-type diffusion layer 31 is formed up to the vicinity of the tip of the pyramid-shaped projection 20 of the emitter electrode layer 12, and the surface of the diffusion layer 31 is substantially flat. It is.
[0070]
In the present cold cathode, the thickness of the diffusion layer 31 is larger than that of the cold cathode of the first embodiment, the resistance of the gate wiring is further reduced, and a signal delay hardly occurs even when a large-area FEA is formed.
[0071]
The manufacturing process of the field emission cold cathode shown in FIG. 4 will be described with reference to the process sectional views of FIGS. First, as shown in FIG. 5A, an n-type diffusion layer 31 is formed on a surface layer of a p-type (001) silicon single crystal substrate 17 by using a thermal diffusion method or an ion implantation method.
[0072]
Next, as shown in FIG. 5B, an inverted pyramid-shaped concave portion 32 is formed on the diffusion layer 31 and the silicon substrate 17. When forming the recess 32, the opening of the recess 32 is formed in the diffusion layer 31, and the tip of the bottom of the recess 32 is formed in the silicon substrate 17. The recess 32 can be formed in the silicon substrate 17 using the method described in the first embodiment.
[0073]
Next, as shown in FIG. 5C, a silicon oxide film 14 is formed on the surface of the diffusion layer 31 and the silicon substrate 17 by using a dry oxidation method. Next, as shown in FIG. 7D, an emitter electrode layer 13 and an ITO electrode layer 12 serving as a cathode electrode are sequentially stacked on the silicon oxide film 14. The emitter electrode layer 13 is formed until the inside of the recess is filled.
[0074]
Next, as shown in FIG. 5E, a 1 mm-thick quartz glass substrate 11 having a 0.4 μm-thick Al layer 19 formed on the back surface is prepared, and the glass substrate 11 and the silicon single crystal substrate 17 are separated. Adhesion is performed with the emitter electrode layer 13 interposed therebetween. For this bonding, for example, an electrostatic bonding method can be applied. The electrostatic bonding method contributes to a reduction in the weight and thickness of the cold cathode device.
[0075]
Next, as shown in FIG. 5F, after removing the Al layer 19 on the back surface of the quartz glass substrate 11, the silicon single crystal substrate 17 is selectively etched away using an electrochemical etching method, and the diffusion layer 31 is formed. At the same time, the tip of the pyramid-shaped projection 33 by the emitter electrode layer 13 covered with the diffusion layer 31 and the silicon oxide film 14 is exposed.
[0076]
In the electrochemical etching method, for example, in a KOH aqueous solution, a reverse voltage is applied to a pn junction generated at an interface between the n-type diffusion layer 31 and the p-type silicon single crystal substrate 17 to form a p-type silicon single crystal. This is a method of selectively etching a substrate.
[0077]
Next, as shown in FIG. 6G, the gate electrode 16 is formed on the diffusion layer 31 by using an electroplating method. When the gate electrode 16 is formed by using the electrolytic plating method, the gate electrode 16 is selectively formed only on the surface of the diffusion layer 31 having conductivity. Not formed on top.
[0078]
Next, as shown in FIG.₄The silicon oxide film 14 is selectively removed using a mixed solution of F and HF. Up to this step, openings are formed in the gate electrode 16, the diffusion layer 31, and the silicon oxide film 14, and the tips of the pyramid-shaped projections 33 formed by the emitter electrode layer 13 are exposed. That is, an emitter is formed.
[0079]
Note that, without forming the ITO electrode layer on the emitter electrode layer, the ITO electrode layer and the emitter electrode layer formed on quartz glass in advance can be bonded to each other.
[0080]
[Third embodiment]
FIG. 7 is a cross-sectional view showing a configuration of a field emission cold cathode according to the third embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
[0081]
The feature of this embodiment is that a core-shaped resistance layer 34 is formed between the ITO electrode layer 12 and the emitter electrode layer 35. The emitter electrode layer 35 is formed separately for each protrusion 33, and is electrically connected to the ITO electrode layer 12 by the core-shaped resistance layer 34.
[0082]
Since the shape of the emitter electrode layer 35 may be different due to manufacturing variations, a large amount of current flows from the emitter electrode layer 35 having a short distance from the gate electrode 16, and the gap between the gate electrode 16 and the emitter electrode layer 35 may be reduced. A short circuit may occur between them. However, by inserting the core-shaped resistance layer 34 between the emitter electrode layer 35 and the ITO electrode layer 12, the current flowing from the ITO electrode layer 12 to the emitter electrode layer 35 can be limited, and the short circuit can be suppressed.
[0083]
The manufacturing process of the cold cathode shown in FIG. 7 will be described with reference to the process sectional view of FIG. FIGS. 8A and 8B are the same as the steps shown in FIGS. 5A and 5B of the second embodiment, and a description thereof will be omitted. Then, as shown in FIG. 8C, an electrode material is deposited on the silicon oxide film 14. Then, after a resist (not shown) is formed on the electrode material in the region including the concave portion 32, the electrode material is etched using the resist as a mask by RIE to form an emitter electrode layer 35, and the resist is removed.
[0084]
Next, as shown in FIG. 8D, a core-shaped resistance layer 34 is deposited on the silicon oxide film 34 and the emitter electrode layer 35.
[0085]
Next, as shown in FIG. 8E, after the ITO electrode layer 12 is formed on the core-shaped resistance layer 34, the adhesion between the quartz glass substrate 11 and the ITO electrode layer 12, The selective removal of the crystal substrate 17 and the formation of the gate electrode 16 are sequentially performed.
[0086]
Then, as shown in FIG. 8F, similarly to the second embodiment, the emitter electrode layer 35 is exposed by selectively etching the diffusion layer 31 and the silicon oxide film 14, and the field emission type cold cathode is formed. Is completed.
[0087]
Instead of forming the ITO electrode layer on the core-shaped resistive layer, it is also possible to bond and form the ITO electrode layer and the emitter electrode layer previously formed on quartz glass.
[0088]
[Fourth embodiment]
FIG. 9 is a sectional view showing the configuration of the FEA according to the fourth embodiment of the present invention. 9, the same parts as those in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.
[0089]
The feature of the present embodiment is that a cathode electrode line is formed in which a plurality of structural bases 43a to 43d in which a plurality of emitter electrode layers 35 each having a sharp tip are formed in a row are formed on a quartz glass substrate 41 in a row direction. That is, the two-dimensional arrangement is made on the surfaces 42a and 42b in close contact with each other in the row direction and the column direction. Gate electrodes 44a and 44b are arranged and formed along the column direction on the structural bases 43a to 43d.
[0090]
FIG. 7 is an enlarged view of a junction between the structural bases 43a to 43d, and each structural base 43 has a large number of emitter electrode layers 35 in addition to the illustrated portions. Further, although one structural base is illustrated as being disposed at the intersection of the cathode electrode 42 and the gate electrode 44, a plurality of intersections of the cathode electrode 42 and the gate electrode 44 are formed on one structural base. ing.
[0091]
The manufacturing process of this cold cathode will be described with reference to FIGS.
[0092]
First, as shown in FIG. 10A, after forming a plurality of emitter electrode layers 35 by using the steps shown in FIGS. 8A to 8D of the third embodiment, The structural bases 43a to 43d which have been formed and patterned are prepared. Further, a quartz glass substrate 41 having cathode electrodes 42a and 42b formed on the surface thereof along the row direction is prepared.
[0093]
Next, as shown in FIG. 11B, the structural bases 43a to 43d are bonded to the surface of the quartz glass substrate 41 on which the cathode electrodes 42a and 42b are formed, with the emitter electrode layer 35 interposed therebetween. That is, the core-shaped resistance layer 34 and the cathode electrodes 42a and 42b are bonded.
[0094]
Next, as shown in FIG. 11C, the silicon single crystal substrate 11 is selectively etched away as in the third embodiment to expose the projections 33 of the diffusion layer 35.
[0095]
Next, as shown in FIG. 12D, gate electrodes 44a and 44b are formed on the diffusion layer 31 by using a screen printing method in the column direction. Since the surface of the diffusion layer 31 has only a protrusion and is flat, the gate electrodes 44a and 44b can be easily formed by screen printing.
[0096]
At this time, if the gap between the adjacent structural bases 43 is large, the gate electrode 44 may be cut off. Therefore, when the gate electrode 44 is formed so as to fill the gap, disconnection can be prevented. Further, when formed so as to fill the gap, the gate electrode 44 may be formed on the glass substrate as long as the gate electrode 44 is insulated from the cathode electrode 42. In addition, when a connection electrode is formed on the glass substrate at a position where the gate electrode 44 is formed, and the gate electrode is formed on the connection electrode, it is possible to further ensure electrical connection of the gate electrode. it can.
[0097]
Then, as shown in FIG. 12E, after patterning the gate electrodes 44a and 44b and exposing the diffusion layer 31, the diffusion layer 31 and the silicon oxide film 14 are sequentially etched so that the tip of the emitter electrode layer 35 is Exposing the sharp projections. The FEA of this embodiment is formed by the steps described above.
[0098]
According to the present embodiment, after arranging a structural base on which a plurality of emitters are formed in advance on a quartz glass substrate on which a cathode electrode is formed in advance, a silicon single crystal substrate on the emitter is selectively removed, and a gate electrode is formed. , A large-area FEA can be formed without using wire bonding.
[0099]
In addition, by using a printing method for forming the gate electrode, the gate electrode can be easily formed along the column direction.
[0100]
Note that the structural base 43 is a structure formed through the steps shown in FIGS. 2A to 2C of the first embodiment, or shown in FIGS. 5A to 5D of the second embodiment. Even if you use the structure formed through the processgood.
[Fifth Embodiment]
FIG. 13 is a sectional view showing the configuration of the FEA according to the fifth embodiment of the present invention. In FIG. 13, the same portions as those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.
[0101]
The feature of the FEA of this embodiment is that the gate electrode connection conductive layer 51 (51a, b) is formed on the gate electrode 44 (44a, b). Each of the gate electrode connection conductive layers 51 a and 51 b is selectively formed on the gate electrode 44 located on the junction of the adjacent structural base 43. By forming the gate electrode connection layer 51, electrical connection of the gate electrode between the adjacent structural bases 43 can be reliably performed.
[0102]
The manufacturing process of the FEA shown in FIG. 13 will be described with reference to the process chart of FIG. First, as shown in FIG. 14 (a), the gate formed in the region including the junction of the adjacent structural base 43 with respect to the structure formed through the steps shown in FIGS. 10 (a) to 12 (d). The gate electrode connection conductive layers 51a and 51b are formed on the electrodes 44 by using a screen printing method. Note that it is also possible to form the gate electrode connection conductive layer 51 by patterning after depositing an electrode material on the entire surface.
[0103]
Next, as shown in FIG. 14B, the tip of the convex portion of the emitter electrode layer 35 is etched by etching the gate electrode 44, the diffusion layer 31, and the silicon oxide film 14 in the same manner as the process described in the previous embodiment. By exposing, the FEA of this embodiment is completed.
[0104]
It is also possible to form the gate electrode connection conductive layer after exposing the tip of the projection of the emitter electrode layer 35.
[0105]
[Sixth embodiment]
FIG. 15 is a sectional view showing the configuration of the FEA according to the sixth embodiment of the present invention. 15, the same parts as those in FIG. 9 are denoted by the same reference numerals, and the description thereof will be omitted.
[0106]
The feature of this embodiment is that an insulating layer 63 made of glass, SOG (Spin On Glass), silicon oxide or silicon nitride is buried in the gap 62 between the adjacent structural bases 61a and 61b. Since the insulating layer 63 is embedded in the gap 62, when depositing the gate electrodes 44a, b, the gate electrodes 44a, b are formed on the ITO electrode layer 44a in the gap 62 at the joint of the structural base. To prevent short circuit between the gate electrodes 44a and 44b and the ITO electrode layer 42a.
[0107]
The manufacturing process of the FEA shown in FIG. 15 will be described with reference to FIGS.
[0108]
First, the structure shown in FIG. 16A is formed through the steps shown in FIGS. 10A to 11C described above. As illustrated, a gap 62 is formed between the structural base 61a and the structural base 61b.
[0109]
Next, as shown in FIG. 16B, an insulating layer 63 is formed so as to fill a gap 62 between the substrates 61a and 61b.
[0110]
Next, as shown in FIG. 17C, the insulating layer 63 on the diffusion layer 31 is removed using an etch-back method or the like, and the insulating layer 63 is buried in the gap 62. Note that it is not necessary to embed the entire gap 62 with the insulating layer 63, and it is sufficient that the gap 62 is formed so as to cover the opening of the gap 62.
[0111]
Next, as shown in FIG. 17D, after the gate electrodes 44a and 44b are formed in the same manner as in the fourth embodiment, the gate electrode, the diffusion layer 31 and the silicon oxide film 14 are selectively removed to reduce the FEA. Complete.
[0112]
Note that the structural base 61 is a structure formed through the steps shown in FIGS. 2A to 2C of the first embodiment, or shown in FIGS. 5A to 5D of the second embodiment. Even if you use the structure formed through the processgood.
[Seventh embodiment]
FIG. 18 is a perspective view showing the configuration of the FEA according to the seventh embodiment of the present invention. In FIG. 18, the same portions as those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.
[0113]
The feature of the FEA of the present embodiment is that the insulating layer 71 is formed below a region including a joint between adjacent structural bases 43. Since the insulating layer is formed below the junction between the adjacent structural bases 43, it is possible to prevent the gate electrode 44 and the cathode electrode 42 from being electrically connected.
[0114]
The manufacturing process of the FEA shown in FIG. 18 will be described with reference to the process charts of FIGS.
[0115]
First, as shown in FIG. 19A, for the structure formed through the steps shown in FIGS. 8A to 8D, structural bases 43a to 43d in which the core-shaped resistance layer 34 is patterned are prepared. I do. Further, a structural substrate 70 having the cathode electrode lines 42a and 42b and the insulating layer 71 formed on the quartz glass substrate 41 is prepared. Note that the insulating layer 71 is formed at a portion that comes into contact with a region including a joint portion of the adjacent base 43 when the structural base 43 is tiled on the structural substrate 70 in a later step.
[0116]
Next, as shown in FIG. 20B, the surface of each structural base 43 on which the resistance layer 34 is formed and the surface of the substrate 70 on which the cathode electrodes 42a and 42b are formed are bonded. At this time, tiling is performed so that the joining portion between the adjacent structural bases 43 always exists on the insulating layer 71.
[0117]
Next, as shown in FIG. 20C, the removal of each silicon single crystal substrate 17, the formation of gate electrodes 44a and 44b, and the etching of the gate electrode 44, the diffusion layer 31, and the silicon oxide film 14 are sequentially performed. The FEA of the embodiment is completed.
[0118]
Note that the structural base 43 is a structure formed through the steps shown in FIGS. 2A to 2C of the first embodiment, or shown in FIGS. 5A to 5D of the second embodiment. Even if you use the structure formed through the processgood.
[Eighth Embodiment]
FIGS. 21 and 22 are cross-sectional views showing the steps of manufacturing the field emission cold cathode according to the eighth embodiment of the present invention.
[0119]
First, as shown in FIG. 21A, a support substrate 81 and a structure base obtained by patterning a core-shaped resistive layer 34 with respect to the structure formed through the steps shown in FIGS. 8A to 8D. The surfaces of the silicon substrates 17 of 82a to 82d are temporarily bonded.
[0120]
Next, as shown in FIG. 21B, the cathode electrodes 83a and 83b are formed on the core-shaped resistance layer 34 in the row direction by using a screen printing method.
[0121]
Next, as shown in FIG. 22C, the cathode electrodes 83a and 83b and the quartz glass substrate 84 are bonded. Then, by removing the support substrate 81 and the silicon single crystal substrate 17, the structure shown in FIG. 11C is formed. In the subsequent steps, the same steps as those shown in FIGS. 11C to 12E are performed to complete the FEA of the present embodiment.
[0122]
[Ninth embodiment]
FIG. 23 is a perspective view showing the configuration of the FEA according to the ninth embodiment of the present invention. 23, the same parts as those in FIG. 9 are denoted by the same reference numerals, and the description thereof will be omitted.
[0123]
The feature of this embodiment is that a cathode electrode connection conductive layer 92 (92a, b) is formed below the cathode electrode 83 which is in contact with the adjacent structural base and the joint. By forming the cathode electrode connection conductive layer 92, electrical connection of the cathode electrode 83 between adjacent structural bases 83 can be ensured.
[0124]
The manufacturing process of the FEA shown in FIG. 23 will be described with reference to the process chart of FIG. .
[0125]
First, a structure formed through the steps shown in FIGS. 21A and 21B is prepared. Then, a quartz glass substrate 91 having the surface on which the cathode electrode connection electrode layers 92a and 92b are formed is prepared. The cathode electrode connection conductive layer 92 on the quartz glass substrate 91 is formed on the glass substrate 91 facing an area including the intersection between the junction of the adjacent structural base and the cathode electrodes 83a and 83b.
[0126]
Next, after bonding the cathode electrode connection conductive layer 92 and the cathode electrode 83, the support substrate 81 and the silicon substrate 17 are removed, and the gate electrode 44 is formed, and the diffusion layer 31 and the silicon oxide film 14 are etched to perform FEA. Is completed.
[0127]
Note that the present invention is not limited to the above embodiment. For example, an FED (Field Emission Display) or an electron beam exposure apparatus can be formed using the above-described FEA.
[0128]
The rigid layer (etching stop layer) is not limited to a diffusion layer in which silicon is doped with impurities, but may be any material as long as it is harder than the gate electrode and does not displace due to electric field induced stress. Further, a rigid layer may be deposited on a silicon substrate (mold substrate).
[0129]
Further, the material of the emitter electrode layer is not limited to tungsten, and various materials having a low work function can be used.
[0130]
Further, the FEA can be formed by appropriately combining the manufacturing methods described in the fourth to ninth embodiments.
[0131]
In forming the gate electrode, an evaporation method, a sputtering method, or the like can be used.
[0132]
Further, after cold cathodes formed by the Spindt method or the like are two-dimensionally arranged, and a plurality of structural bases in which gate electrodes are formed in the column direction are closely arranged, the gate electrodes of the structural bases adjacent in the column direction are connected. It is also possible to electrically connect with a film-like gate electrode connection layer. It is also possible to similarly tile a structural base on which a flat cold cathode in which a gate electrode and a cathode electrode are formed in the same plane is formed.
[0133]
When the gate electrode connection layer is formed, disconnection may occur at the junction between adjacent structural bases as described in the above embodiment. Therefore, when the gate electrode connection layer is formed so as to fill the gap, disconnection can be prevented. Further, when formed so as to fill the gap, the gate electrode connection layer may be formed on the structural substrate as long as it is insulated from the cathode electrode. In addition, when a connection electrode is formed on the structure substrate at a position where the gate electrode is to be formed, and the gate electrode connection layer is formed on the connection electrode, the electrical connection of the gate electrode is further ensured. Can be.
[0134]
Further, it is also possible to two-dimensionally arrange a plurality of structural substrates on which structural bases are arranged to form an FEA having a larger area. In this case, it is possible to provide a through hole connected to the cathode electrode in the structural substrate, and to electrically connect the cathode electrodes of the adjacent structural substrates using the through hole.
[0135]
In addition, the present invention can be variously modified and implemented without departing from the gist thereof.
[0136]
【The invention's effect】
As described above, according to the present invention, since the gate electrode is formed on the rigid layer, the gate electrode and the emitter are not short-circuited by the electric field induced stress, and the reliability is improved.
[0137]
Further, by forming a plurality of structural bases on a substrate and forming a gate electrode or a cathode electrode, the electrodes can be continuously formed, and the electrodes may be cut between adjacent structural substrates. Therefore, a field emission cold cathode having a large area can be easily formed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration of a field emission cold cathode according to a first embodiment.
FIG. 2 is a process cross-sectional view showing a manufacturing process of the field emission cold cathode shown in FIG.
FIG. 3 is a process cross-sectional view showing a process of manufacturing the field emission cold cathode shown in FIG.
FIG. 4 is a sectional view showing a configuration of a field emission cold cathode according to a second embodiment.
FIG. 5 is a process sectional view showing the configuration of the field emission cold cathode shown in FIG. 4;
FIG. 6 is a process sectional view showing the configuration of the field emission cold cathode shown in FIG. 4;
FIG. 7 is a cross-sectional view illustrating a configuration of a field emission cold cathode according to a third embodiment.
8 is a process cross-sectional view showing a manufacturing process of the field emission cold cathode shown in FIG.
FIG. 9 is a perspective view showing the configuration of an FEA according to a fourth embodiment.
FIG. 10 is a process chart showing a manufacturing process of the FEA shown in FIG. 9;
FIG. 11 is a process chart showing a manufacturing process of the FEA shown in FIG. 9;
FIG. 12 is a process chart showing a manufacturing process of the FEA shown in FIG. 9;
FIG. 13 is a perspective view showing the configuration of an FEA according to a fifth embodiment.
FIG. 14 is a process chart showing a manufacturing process of the FEA shown in FIG. 13;
FIG. 15 is an exemplary perspective view showing the configuration of an FEA according to a sixth embodiment;
16 is a process chart showing a manufacturing process of the FEA shown in FIG.
FIG. 17 is a process chart showing a manufacturing process of the FEA shown in FIG. 15;
FIG. 18 is a perspective view showing the configuration of an FEA according to a seventh embodiment.
FIG. 19 is a perspective view showing a manufacturing process of the FEA shown in FIG. 18;
FIG. 20 is a process chart showing a manufacturing process of the FEA shown in FIG. 18;
FIG. 21 is a process chart showing a process of manufacturing the FEA according to the eighth embodiment.
FIG. 22 is a process chart showing a process of manufacturing the FEA according to the eighth embodiment.
FIG. 23 is an exemplary perspective view showing the configuration of an FEA according to a ninth embodiment;
FIG. 24 is a process chart showing a manufacturing process of the FEA shown in FIG. 23;
[Explanation of symbols]
11 ... Glass substrate
12: ITO electrode layer (cathode electrode)
13 ... Emitter electrode layer
14. Silicon oxide film
15 ... Diffusion layer
16 ... Gate electrode
17 ... Silicon single crystal substrate
18 ... recess
19 ... Al layer
20 ... convex part
21 ... Resist
31 ... Diffusion layer
32 ... recess
33 ... convex part
34: core-shaped resistance layer
35 ... Emitter electrode layer
41 ... Quartz glass substrate
42a, b ... cathode electrodes
43a-d ... structural base
44a, b ... gate electrodes
51a, b ... gate electrode connection conductive layer
61 ... Structure base
62: gap
63 ... insulating layer
71 ... Insulation separation layer
81 ... Support substrate
83a, b ... cathode electrodes
91 ... Quartz glass substrate
92a, b ... cathode electrode connection conductive layer

Claims (17)

A plurality of cathode electrodes arrayed and formed in a row direction on an insulating substrate, and an emitter electrode layer electrically connected to the cathode electrodes and having two-dimensionally arranged convex portions having sharp tips in the row direction and the column direction. A field emission cold cathode comprising: a plurality of electrodes formed along the column direction; extracting electrons from the tips of the projections; and a gate electrode having an opening on the tips of the projections.
The emitter electrode layer is formed on each of a plurality of structural substrates closely arranged on the cathode electrode,
An insulating layer formed on the emitter electrode layer of each structural base along the surface of the electrode layer, the tip region of the protrusion is removed, and an insulating layer is formed on the insulating layer along the column direction. A rigid layer having an opening in the tip region of the convex portion is sequentially laminated,
The field emission cold cathode, wherein the gate electrode is continuously formed on the rigid layer of the structural base adjacent in the column direction. 2. The electric field according to claim 1 , wherein a gate electrode connection conductive layer is selectively formed on the gate electrode in a region including a junction between the adjacent structural base and each gate electrode. 3. Emission cold cathode. 2. The field emission cold cathode according to claim 1, wherein a first isolation insulator for closing an opening of the gap is formed in a gap between adjacent structural bases. 2. The field emission cold cathode according to claim 1 , wherein a junction between adjacent structural bases is formed on a second isolation insulator formed on the insulating substrate. 2. The field emission cold cathode according to claim 1 , wherein a cathode electrode connection conductive layer is formed under a cathode electrode in a region including a junction between adjacent structural bases. The field emission cold cathode according to claim 1 , wherein the rigid layer is silicon doped with an impurity. 2. The field emission cold cathode according to claim 1 , wherein the surface of the rigid layer is flat. A step of forming a plurality of concave portions with sharp bottoms on the mold substrate,
Forming a rigid etching stop layer on the mold substrate,
Forming an insulating layer on the etching stop layer;
Forming a plurality of structural substrates formed including the step of forming an emitter electrode layer on the insulating layer,
Each structural base and a plurality of cathode electrodes formed along the row direction on the insulating substrate are arranged by arranging the respective structural bases such that the emitter electrode layer is interposed and the adjacent structural bases are in close contact with each other. Bonding step,
Each of the mold substrates is etched, and the emitter electrode layer, the insulating layer, and the etching stop layer formed in each of the concave portions project from a flat portion of the etching stop layer, and a plurality of convex portions having sharp tips are formed. Exposing the
A step of forming a plurality of gate electrodes having openings at the tips of the respective protrusions in the column direction on the etching stop layer of the arranged structure base,
Removing the etching stop layer and the insulating layer formed at the tips of the respective projections to expose the projections of the emitter electrode layer with sharp tips. Method. Forming a rigid etching stop layer on the mold substrate;
Forming an opening in the etching stop layer, and forming a plurality of sharp recesses at the bottom of the mold substrate;
Forming an insulating layer on the mold substrate and the etching stop layer,
Forming a plurality of structural bases formed including a step of forming an emitter electrode layer on the insulating layer;
The respective structural bases and a plurality of cathode electrodes formed along the row direction on the insulating substrate are bonded by arranging the respective structural bases such that the emitter electrode layer is interposed and the adjacent structural bases are in close contact with each other. The process of
Each of the mold substrates is etched, and the emitter electrode layer, the insulating layer, and the etching stop layer formed in each of the concave portions project from a flat portion of the etching stop layer, and a plurality of convex portions having sharp tips are formed. Exposing the
A step of forming a plurality of gate electrodes having openings at the tips of the respective protrusions in the column direction on the etching stop layer of the arranged structure base,
Removing the etching stop layer and the insulating layer formed at the tips of the respective projections to expose the projections of the emitter electrode layer with sharp tips. Method. 10. The field emission cooling according to claim 8 , wherein a first isolation insulator for closing an opening of a gap between adjacent structural bases is formed before the step of forming the gate electrode. Manufacturing method of cathode. After forming the gate electrode, according to claim, characterized by forming on the gate electrode region including the intersection of the joint and the gate electrode of the adjacent structural substrate, selectively a gate electrode connecting conductive layer 8 Or a method for producing a field emission cold cathode according to item 9 . When bonding each structural base and the cathode electrode formed on the insulating substrate,
The method according to claim 8 , wherein the joint between adjacent structural bases is formed on a second isolation insulator formed on an insulating substrate. A step of forming a plurality of concave portions with sharp bottoms on the mold substrate,
Forming a rigid etching stop layer on the mold substrate;
Forming an insulating layer on the etching stop layer;
Forming a plurality of structural substrates formed including the step of forming an emitter electrode layer on the insulating layer ,
A step of arranging each of the structural bases on the support substrate, in which each mold substrate and the support substrate are in contact, and the adjacent structural bases are brought into close contact with each other;
Forming a plurality of cathode electrodes along the row direction on the emitter electrode layer;
Bonding the cathode electrode and a structural substrate,
The support substrate and the respective mold substrates are removed, and the emitter electrode layer, the insulating layer and the etching stop layer formed in the respective recesses protrude with respect to a flat portion of the etching stop layer, and have a sharp tip. Exposing a plurality of protrusions,
A step of forming a plurality of gate electrodes having openings at the tips of the respective protrusions in the column direction on the etching stop layer of the arranged structure base,
Removing the etching stop layer and the insulating layer formed at the tips of the respective projections to expose the projections of the emitter electrode layer with sharp tips. Method. Forming a rigid etching stop layer on the mold substrate;
Forming an opening in the etching stop layer, and forming a concave recess having a sharp bottom in the mold substrate;
Forming an insulating layer on the mold substrate and the etching stop layer,
Forming a plurality of structural bases formed including a step of forming an emitter electrode layer on the insulating layer;
A step of arranging the respective structural bases on the support substrate such that each mold substrate and the support substrate are in contact with each other and the adjacent structural bases are in close contact with each other;
Forming a plurality of cathode electrodes along the row direction on the emitter electrode layer;
Bonding the cathode electrode and a structural substrate,
The support substrate and the respective mold substrates are removed, and the emitter electrode layer, the insulating layer and the etching stop layer formed in the respective recesses protrude with respect to a flat portion of the etching stop layer, and have a sharp tip. Exposing a plurality of protrusions,
A step of forming a plurality of gate electrodes having openings at the tips of the respective protrusions in the column direction on the etching stop layer of the arranged structure base,
Removing the etching stop layer and the insulating layer formed at the tips of the respective projections to expose the projections of the emitter electrode layer with sharp tips. Method. The structural substrate is formed from an insulating substrate and a cathode electrode connection conductive layer formed on the insulating substrate,
15. The structure according to claim 13 , wherein the cathode electrode and the structural substrate are bonded so that a junction between the adjacent structural base and the intersection of the cathode electrode is located on the cathode electrode conductive connection layer. 3. The method for producing a field emission cold cathode according to item 1. The mold substrate is a silicon single crystal substrate,
15. The method of claim 8, 9, 13 or 14 , wherein the etching stop layer is formed by doping the mold substrate with an impurity. 15. The method according to claim 8, wherein the gate electrode is formed by a printing method or an electroplating method.

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