KR20000016555A - Gate-controlled electron emitter using injection particle for restricting gate opening and fabricating method thereof - Google Patents

Abstract

PURPOSE: A fabricating method of a gate-controlled electron emitter is provided to make particles restrict a gate opening through a gate layer and form a dielectric opening through an insulating layer through the opening. CONSTITUTION: The method comprises the steps of injecting many particles into a structure, utilizing the particles for restricting a corresponding position for many gate openings extended through an electrical conductive gate layer supplied around an electrical insulating layer in the structure, supplying a spacer material into the gate opening to leave a corresponding aperture extended downwardly toward the insulating layer through a spacer material although generally covering a side end thereof, etching the insulating layer through the aperture to form a dielectric opening, and injecting an electrical conductive emitter material into the dielectric opening to form an electron emitting device.

Description

Gate-controlled electron-emitting device using sprayed particles to define gate openings and method for manufacturing same

Cross Reference of Related Application

This application contains subject matter that is partly similar to Haven et al., International Patent Application No., Representative Serial Number M-3850 PCT.

A field emission cathode (or field emitter) emits electrons when it receives an electric field of sufficient strength. An electric field is produced by applying an appropriate voltage between an electrode and an electrode, generally referred to as an anode or gate electrode, located short distance away from the cathode.

When field emission cathodes are used in flat panel CRT displays, electron emission from the cathode occurs over a scalable region. The electron emission regions are commonly divided into two-dimensional arrays of electron emission portions, each positioned over a corresponding light emitting portion to form part or all of the pixels. The electrons emitted by each of the electron emission parts collide with the corresponding light emission parts to emit visible light.

In general, it is desirable that the illumination be uniform (constant) over each light emitting region. One way to achieve uniform illumination is to arrange the electrons to be evenly distributed over the corresponding electron emitting region. This generally involves the fabrication of electron emitting portions as many small, closely spaced electron emitting devices.

Various methods have been studied for manufacturing electron emitting devices including small, closely spaced electron emitting devices. Spindt et al. "Research in Micron-Sized Field-Emission Tubes" (IEEE Conf. Rec. 1966 Eighth Conf. Tube Techniques, Sept. 20, 1996, pp. 143-147) are flat field emission cathodes with small randomly spherical particles. The method used to define a location for a conical electron-emitting device is described. The size of the spherical particles strongly controls the basic diameter of the conical electron-emitting device.

1A-1G (collectively "FIG. 1") illustrate a spherical-based process used in Spindt et al. To document an electron emitting diode having a thick anode. In FIG. 1A, the starting point is the sapphire substrate 20. A sandwich composed of a lower molybdenum layer 22, an insulating layer 24, and an upper molybdenum layer 26 is positioned on the substrate 20.

Polystyrene spheres 28, one of those shown in FIG. 1B, are sprayed over the top of the molybdenum layer 26. As shown in FIG. "Resist" is deposited to form resist layer 30A on the uncovered portion of layer 26. Referring to FIG. 1C, a portion 30B of the resist, generally alumina (aluminum oxide layer), accumulates on the spherical particles 28 during resist deposition. The spherical body 28 is continuously removed, thereby removing the resist portion 30B. Referring to FIG. 1D, the opening 32 extends through the resist layer 30A at the location of the removed sphere 28.

The placement portion of the molybdenum layer 26 is etched through the resist opening 32 to form the opening 34 through the molybdenum 26, the remainder of which is indicated by item 26A in FIG. 1E. Similarly, the placement of the insulating layer 24 is etched through the opening 34 to form the cavity 36 through the remaining insulating layer 24A. Referring to FIG. 1F, the resist layer 30A is typically removed during cavity etching.

Finally, molybdenum is deposited on the top of the structure and by evaporation into the cavity 36. Evaporation is carried out in such a way that the openings in which molybdenum accumulates therein in the cavity 36 are gradually approached. As shown in FIG. 1G, the conical molybdenum electron-emitting device 38A is formed in the cavity 36, while the continuous molybdenum layer 38B is formed on top of the molybdenum layer 26A. Layers 38B and 26A together form an anode for the diode.

The use of spherical particles to determine the basic size and location of the electron-emitting device of Spindt et al. In many of the above documents is a unique approach to creating an electron-emitting device. However, electrons emitted by the element 38A are collected by the anodes 26A / 38B and are therefore not used to directly activate the light emitting region. It is desirable to use spherical particles to define locations for small, closely spaced electron emitting devices that emit electrons that can be used to directly activate light emitting devices in a flat panel device in a very uniform manner. .

The present invention relates to the manufacture of an electron emitting device, commonly referred to as a cathode, suitable for an article such as a flat panel type "cathode-ray tube" display.

1A-1G are cross-sectional structural diagrams illustrating steps in a prior art process for manufacturing a diode field emitter;

2A and 2G are cross-sectional structural diagrams illustrating a set of steps in a process in accordance with the techniques of the present invention for producing gate controlled field emitters having conical electron-emitting devices;

3A and 3I are cross-sectional structural views showing one set of steps in another process in accordance with the techniques of the present invention for producing field emitters having conical electron-emitting devices,

4A-4F, FIG. 4G (1), and FIG. 4G (2) are cross-sectional structural diagrams illustrating a set of front end steps in a process for manufacturing a gate controlled field emitter in accordance with the present invention;

5A-5G show a set of front end structures of (1) of FIG. 4E, 4F, or 4G being processed in accordance with the present invention to produce a gate controlled field emitter having a fibrous electron-emitting device. Cross-sectional structural diagram showing the latter stage,

6A-6H show another set in which the front end structure of (1) of FIG. 4E, 4F, or 4G is processed in accordance with the present invention to produce a gate controlled field emitter having a fibrous electron-emitting device. Cross-sectional structural diagram showing the later stages of

7A-7J are cross-sectional structural diagrams illustrating a set of steps in a process according to the present invention for producing a gate controlled field emitter having a fibrous electron-emitting device;

8A and 8B are enlarged cross-sectional structural views of a portion of FIGS. 7F and 7H focusing on the manufacture of one of the electron-emitting devices;

9A-9C are enlarged cross-sections illustrating a set of steps that may be substituted for the steps of FIGS. 7H-7J in fabricating a gate controlled field emitter having a fibrous electron-emitting device in accordance with the present invention. Structural Diagram,

10A-10G are cross-sections illustrating a later set of steps in which the front end structure of FIG. 3F (or FIG. 3E) is processed in accordance with the present invention to produce gate controlled field emitters having a fibrous electron-emitting device. Structural Diagram,

11A-11H are cross-sectional structural views showing one set of steps in another process according to the present invention for producing a gate controlled field emitter having a fibrous electron-emitting device;

12A-12I are cross-sectional structural diagrams illustrating a set of steps in a further process according to the present invention for producing a gate controlled field emitter having a fibrous electron-emitting device;

13A-13G are cross-sectional structural diagrams illustrating a set of front end steps in a process for manufacturing a gate controlled field emitter in accordance with the present invention;

FIG. 14 is a cross-sectional structural view illustrating a method in which the initial structure of FIGS. 2A, 3A, 4A, 7A, or 12A is shown when the lower non-insulated region is composed of an electrical resistance portion and an electrical conductive portion;

15A and 15B are cross-sectional structural views illustrating how the last field emission structure of FIGS. 2G and 5G is shown when the lower non-insulated region is composed of an electrical resistance portion and an electrically conductive portion, and

FIG. 16 is a cross-sectional structural diagram of a flat panel CRT display device embodying a gate controlled field emitter as in FIG. 5G, manufactured in accordance with the present invention.

In the above, the front end process sequence of FIGS. 4A-4F may be completed with the steps of FIG. 4G (1) or (2) of FIG. 4G. The field emitter is applied by applying the latter stages of FIGS. 2D to 2G, or the latter stages of FIGS. 3F to 3H to the front end stages of FIGS. 4A to 4F and 4G (1) and 4G (2). It can be provided in the conical electron-emitting device according to.

The front end structure of FIG. 2D or FIG. 3E can be processed in accordance with the present invention by using the latter step of FIGS. 5B-5G to produce a gate controlled field emitter having a fibrous electron-emitting device.

The front end structure of FIG. 2D or FIG. 3E can be processed in accordance with the present invention by using the latter steps of FIGS. 6A-6H to produce gate controlled field emitters having a fibrous electron-emitting device.

The front end structure of Fig. 2D (or Fig. 2C), Fig. 4G (1) or Fig. 4G (2) shows the arrangement of Figs. 10A-10G to produce a gate controlled field emitter having a fibrous electron-emitting device. By using the latter step it can be processed according to the invention.

The front end process sequence of FIGS. 13A-13G may be completed, for example, according to the latter process sequence of FIGS. 7E-7J.

Like reference numerals are used in the drawings and the description of the appropriate embodiments to refer to the same or very similar item (s).

The present invention provides a group of manufacturing processes in which particles, which are generally spherical, are used to make gate controlled electron emitting devices. The particles define the position of the electron-emitting device in the gate controlled electron emitter. Importantly, the manufacturing process of the present invention is arranged such that the electrons emitted by the electron-emitting device are effective for direct active devices such as light emitting regions in the flat panel device.

The surface density of the particles defines (the same) the surface density of the electron-emitting device. The particle surface density can easily be set to a high value. Therefore, high surface density of the electron-emitting device can be easily obtained. Although the particles and electron-emitting devices are generally located at positions arbitrarily associated with each other, the number of electron-emitting devices per unit area is relatively uniform over the entire electron-emitting area.

In addition, the particles can be easily selected to have a strict size injection-that is, the standard deviation of the mean particle diameter is extremely small. By properly adjusting the values for parameters of a particular size, such as a specific thickness, the electron-emitting devices can become very similar to each other. The net result is that the use of particles according to the manufacturing process of the present invention results in very uniform electron emission, so that the luminescent region can be directly activated in a very uniform manner.

When producing a gate controlled electron emitter according to the present invention, a number of particles are sprayed over a suitable starting structure. Importantly, the size of the sides of the starting structure generally has little effect on the ability to spray particles in a (optional) relatively uniform manner over the starting structure. Thus, the manufacturing process of the present invention can be easily used to make large area electron emitters.

The particles generally have a spherical shape. After spraying over the starting structure, the particles are used to define a location for the corresponding gate opening that extends through the electrically non-insulating gate layer provided over the electrically insulating layer in the structure. As described below, "electrically non-insulated" means electrically conductive or electrically resistant.

The particles can be sprayed over an insulating or gate layer, leading to another sequence in using the particles to define the gate opening. When particles are sprayed over the insulating layer, an electrically non-insulating gate material is provided over the insulating layer at least in the spaces between the particles. And particles are removed. During the particle removal operation, any gate material superimposed on the particles is removed at the same time. The remaining gate material forms a gate layer that extends at the location of the particles from which the gate opening has been removed.

When particles are sprayed across the gate layer, additional material is provided over the gate layer in at least the space between the particles. The particles are removed to remove any additional material that overlaps the particles at the same time. The gap then extends through the remaining additional material at the removed particle location. The gate layer is continuously etched through the openings in the remaining additional material to form the gate openings.

The first layer can be formed over the gate layer. The first layer is generally composed of an inorganic dielectric material. If additional material is also present, the first layer is located between the gate layer and the additional material. The plurality of first openings extend through the first layer. Each gate opening is aligned perpendicular to the corresponding one of the first openings. When the first layer is used to make the gate controlled electron emitter according to the present invention, the particles may be sprayed over the insulating layer, the gate layer, or the first layer. Depending on which of these three layers receives the particles, the particles are used to define the gate opening according to a process sequence of a type similar to that described in the two paragraphs above.

The pattern transfer layer may be provided over the insulating layer. The particles are ejected over the pattern moving layer after the pedestal is created from the pattern moving layer by removing a portion of the pattern moving layer that is not blocked by the particles. The gate material is deposited over the insulating layer at least in the spaces between the pedestals. Any overlapping material, including the pedestal and particles, is removed. The remaining gate material forms a gate layer that extends at the location of the pedestal from which the gate mechanism is removed.

Regardless of how the particles are used to define the gate openings, additional processes can be performed to facilitate the production of generally filament-shaped electron-emitting devices. For example, a spacer material may be provided in the gate opening to cover the side ends of the gate opening, but may leave a corresponding gap extending through the spacer material under the insulating layer. The insulating layer is continuously etched through the gaps in the spacer material to form a corresponding dielectric opening generally through the insulating layer below the lower non-insulating region provided below the insulating layer. Instead, the insulating layer can be etched through the gate opening to form a dielectric opening through the insulating layer. And the spacer material is generally provided in the dielectric opening to cover its side ends, but leaves a corresponding gap extending through the spacer material under the lower non-insulated region.

The electron-emitting device is formed over the lower non-insulated region by injecting an electrically non-insulated emitter material through the spacer material into the gap or dielectric opening, depending on whether the insulating layer is etched through the gap in the gate opening or spacer material. As a result, the electron-emitting device is generally in the form of a filament. The spacer material controls the lateral spacing between the gate layer and each electron-emitting device.

In the process flow using the first layer described above, it can be formed on a structure having a first layer, a gate layer, and an insulating layer to easily produce a generally conical electron-emitting device. In particular, the insulating layer may be etched through the first and gate openings to form a corresponding dielectric opening through the insulating layer under the lower electrically non-insulating region provided below the insulating layer. Each first opening is generally no larger than the corresponding gate opening. Thus, the first opening defines the side size of the electron-emitting device (formed later). By selecting particles with strict size injection as in the general case, the size injection of the first opening is equally strict up to the first approximation.

Electrically non-insulating emitter material is deposited over the first layer through the first and gate openings and through the first and gate openings to form corresponding electron-emitting devices over the lower non-insulating region. The electron-emitting device generally has a conical shape. Since the first openings are generally subjected to strict size injections, the side regions occupied by the electron-emitting devices are generally mostly the same. The first layer can be continuously removed to raise the excess emitter material accumulated over the first layer.

Contrary to what occurs in Spindt et al., A number of documents, the movement of electrons emitted by electron-emitting devices in electron emitters made in accordance with the present invention is generally not inhibited by the electrically conductive material deposited over the insulating layer. The electrons can travel beyond the electron emitter to activate a device, such as a light emitting phosphor region, located at a suitable distance above the electron emitter. In short, the present invention provides a group of saving processes for fabricating high performance electronic emitters that can be readily embodied in flat panel CRT devices, particularly wide area flat panel CRT displays.

An important feature of the present invention is that as a gate material candidate in any of the processes of this fabrication process, it contains a small, generally difficult to etch submicrometer opening accurately. In particular, when the gate material is deposited over the particles, the gate openings are formed at the positions of the particles deposited during the gate material deposition. There is no need to perform etching to form the gate openings. Thus, the gate material can be a metal that is difficult to etch.

General consideration

The present invention utilizes particles injected over the surface of the structure to define the openings in the gate electrode for the gate controlled field emission cathode. Each field emitter made in accordance with the present invention is suitable for excitation of the phosphor area on the screen in the CRT of a flat panel device such as a flat panel video monitor or flat panel television for a PC, laptop computer, or workstation.

The present invention provides a number of other methods that utilize particles that are generally spherical in defining gate openings. The present invention also provides a variety of methods using finite gate openings to produce electron emitting devices of various shapes such as cones and filaments. Each electron-emitting device emits electrons through the corresponding one of the gate openings. As long as the particles define the position of the gate opening, the particles also define the position of the electron-emitting device.

In some embodiments, particles may be subjected to various late process sequences to define gate openings in partially provided structures that can be completed according to any one of several late process sequences to produce a gate controlled field emission cathode. Can be used according to any one. Partially provided structures can often be used when producing either conical electron emitting devices or fibrous electron emitting devices. Thus, the present invention is directed to any one of several later manufacturing sequences in order to create an efficient overall field emitter manufacturing process in which any one of the various onset manufacturing sequences yields a customized field emitter tailored to the particular material selection and particular needs. It provides a mix-and-match in what can be combined with one of the following.

In the following description, the term "electrical insulation" (or "dielectric") generally applies to materials having a resistance of greater than 10 ¹⁰ μs-cm. The term "electrically non-insulated" thus refers to a material having a resistance of 10 ¹⁰ kPa-cm or less. The electrically non-insulating material is divided into (a) an electrically conductive material having a resistance of 1 kV-cm or less, and (b) an electrically resistive material having a resistance of 1 kV-cm to 10 ¹⁰ kPa-cm. This category is determined at an electric field of only 1V / μm.

Examples of electrically conductive materials (or electroconductors) are metals, metal-semiconductor composites (such as metal silicides), and metal-semiconductor eutectics. Electrically conductive materials also include semiconductors that are moderately or highly doped (n-type or p-type). Electrically resistive materials include inherently weakly doped (n-type or p-type) semiconductors. Additional examples of electrically resistive materials include (a) metal-insulator composites, such as conductive alloys (ceramic with embedded metal particles), (b) graphite, amorphous carbon, and modified (eg doped or laser modulated) diamonds. Carbon forms, and (c) specific silicon-carbon composites, such as silicon-carbon-nitrogen.

Except for the exceptions mentioned above, the following applies to the anisotropic etching performed in the manufacturing process of the present invention. All anisotropic etchings are very multidirectional and occur as a result of the movement of ions in a direction generally perpendicular to the top side of the emitter / gate electrode dielectric layer. Thus, generally no undercutting occurs during the anisotropic etch. All anisotropic etch are dry etch performed, for example, with plasma or in accordance with reactive ion etching.

Fabrication of Field Emitters Using Electron Emission Cones

2A-2G (collectively "FIG. 2") illustrate a gate controlled field emission cathode using spherical particles to define a gate opening for a conical electron-emitting device according to the techniques of the present invention. The manufacturing process is explained. In the manufacturing process of Figure 2, the starting point is generally an electrically insulating substrate 40 formed of ceramic or glass. Referring to FIG. 2A, the substrate 40 providing support for the field emitter is configured as a plate. In a flat panel CRT display, the substrate 40 constitutes at least part of the backplate.

The lower electrically non-insulating emitter region 42 lies along the top of the substrate 40. The lower non-insulated region 42 can be constructed in a number of ways. At least a portion of the non-insulated region 42 is patterned with a group of generally parallel emitter electrode lines referred to as row electrodes. When the non-isolated region 42 is constructed in this way, the last field emission cathode is particularly suitable for exciting light emitting phosphor elements in flat panel CRT displays. Nevertheless, the non-insulated region 42 may be arranged in a different pattern or may not be patterned.

A very homogeneous electrically insulating layer 44 is provided on the top of the structure. The insulating layer 44 is generally composed of a silicon oxide layer. Instead, layer 44 may be formed of a silicon nitride layer. Although not shown in FIG. 2A, the bottom surface of the insulating layer 44 may contact the substrate 40 according to the configuration of the bottom non-insulating region 42. Part of the insulating layer 44 later becomes an emitter / gate electrode dielectric.

The thickness of the insulating layer 44 should be large enough so that the resulting electron-emitting device will be shaped like a cone whose tip extends slightly above the top surface of the layer 44. The height of each electron emitting cone is dependent on its base diameter, which is determined by the diameter of the spherical particles used to define the gate opening for that electron emitting cone, as described below. The thickness of the insulating layer 44 is generally 1-2 times the spherical particle diameter. The general range in the insulation layer thickness is 0.1-3 mu m.

Hard spherical particles 46 are sprayed in any manner over the top surface of insulating layer 44 as shown in FIG. 2B. Spherical particles 46 generally consist of polystyrene. Alternative materials for the particle 46 include glass (eg silicon oxide), polymers other than polystyrene (eg emulsion), and polymers encoded with functional groups such as alcohol, acid, amide, and sulfonate groups. Included.

When the particles 46 are composed of polystyrene, they have an average diameter in the range of 0.1-3 μm, generally 0.3 μm. The standard deviation in the average particle diameter is generally very small, less than 10% and 2%. The average surface density of the particles 46 over the insulating layer 44 is in the range of 10 ⁶ -10 ¹⁰ particles / cm 2, usually 10 ⁷ -10 ⁹ particles / cm 2. Typical values are 10 ⁸ particles / cm 2. The average spacing between the particles 46 is generally 2-3 times the average particle diameter. At 0.3 μm at 10 ⁸ particles / cm 2, the average spacing is on the order of 0.6-0.9 μm.

The spherical particles 46 are very strongly attached to the insulating layer 44. Van der Waals' forces are believed to at least partially provide an attachment technique. Some or all of the spheres 46 may be negatively filled, for example if the spheres 46 are composed of polystyrene. In the polystyrene case, each sphere 46 generally comprises at least one double negative electrode charge, with each double negative electrode charge occurring at the attachment of a carboxyl group to that sphere 46. Filling of reverse polarity on the initial structure 40/42/44 may assist the attachment technique. In any case, once attached with the insulating layer 44, the particles 46 do not move easily over the top surface of the layer 44.

Various methods can be used to spray the spherical particles 46 over the insulating layer 44. In one method, deionized water containing moderately small polystyrene spheres is first combined with reagent grade alcohols in a beaker. The alcohol is generally isopropanol. Ethanol is an alternative candidate for alcohol.

In the case of isopropanol, the resulting liquid in the isopropanol / water solution is generally at least 99% isopropanol per dose. Polystyrene spheres are suspended in isopropanol / water solution. Nitrogen bubbles through the solution to make the spraying of the spheres more uniform in the solution. Instead, the solution requires ultrasonic fluctuations to improve the uniformity of the spheres in the solution.

In the first half structure 40/42/44, which is generally manufactured in the form of a circular wafer, the wafer is located in a rotating chamber. While the wafer is in the chamber, a controlled amount of isopropanol / water solution, including floating polystyrene spheres, is deposited onto the top surface of the wafer to cover selected portions of the surface of the upper wafer, but does not flow over the top surface of the wafer. Do not. The wafer is then rotated for a short time to remove most of the solution. Rotational speed is 200-2000 rpm, generally 750 rpm. Rotation time is 5-120 seconds, generally 20 seconds.

During rotation, almost all residual isopropanol / water solution is evaporated, leaving behind a polystyrene sphere 46. If any isopropanol / water solution remains, the wafer is dried to remove residual isopropanol / water. The drying operation may for example consist of a nitrogen jet. Whether the drying operation is performed or not, the wafer is usually removed from the rotating chamber. In this way, the structure of FIG. 2B is produced.

Electrically non-insulated gate material is deposited into insulating layer 44 and spherical particles 46. Gate material deposition is generally performed in a direction generally perpendicular to the top surface of layer 44 using methods such as evaporation or parallel sputtering. Gate material accumulates on layer 44 in the space between particles 46 to form an electrically non-insulating gate layer 48A of relatively uniform thickness. Referring to FIG. 2C, a portion 48B of the gate material accumulates simultaneously on the upper half (semisphere) of the particle 46. The gate material is generally a metal such as chromium, nickel, molybdenum, titanium, tungsten or gold.

Appropriately etchable material, referred to herein as the first material, is deposited on the gate layer 48A and the gate material portion 48B. As with gate material deposition, the first material deposition is again normally conducted on the upper surface of electrode dielectric layer 44 using techniques such as evaporation or parallel sputtering. The first material accumulates on the gate layer 48A at intervals between the spherical particles 46 to form a first layer 50A of relatively uniform thickness as shown in FIG. 2C. A portion 50B of the first material accumulates simultaneously on the gate material portion 48B located on the sphere 46. To avoid having the first material portion 50B bridge to the first layer 50A, the overall thickness of the gate layer 48A and the first layer 50A is generally smaller than the average radius of the sphere 46. .

The first material is generally composed of an inorganic dielectric material such as silicon nitride, aluminum oxide, and / or silicon oxide. The first layer 50A is later used as a lift-off layer in the process of FIG. 2 and any process variations described below. In any other process variation described below, layer 50A does not perform a synergistic function. If layer 50A supports as a rising layer, the first material may alternatively be a metal such as aluminum, tungsten, or gold. The first material may also be a salt or metal dielectric mixture, such as magnesium fluoride, magnesium chloride, or sodium chloride, if layer 50A functions as an elevated layer.

Spherical particles 46 are now removed. During removal of the particles 46, the gate material portion 48B and the first material portion 50B are simultaneously removed to produce the structure shown in FIG. 2D. The first opening 52 extends through the first layer 50A at the removed particle 46 location. Gate opening 54 extends through gate layer 48A at the location of similarly removed particles 46. In this way, the particles 46 directly define the position of both the first opening 52 and the gate opening 54. Since the formation of the gate opening 54 occurs during the deposition of the gate material over the particles 46 and is not accomplished by etching the gate material, the gate material candidate has a small opening, i.e., its diameter, that later exposes the electron-emitting cone. It typically contains gold that is difficult to etch accurately openings that are less than 1 micron.

Each gate opening 54 is vertically concentrated in the corresponding first opening 52 and is thus vertically aligned. Since the removed particles 46 are spherical, the first opening 52 is almost spherical. In the case where deposition for forming the layers 48A, 50A is performed substantially perpendicular to the upper surface of the insulating layer 44, the diameters of the corresponding openings 50, 52 of each pair are approximately the same, and thus corresponding Is approximately equal to the diameter of the spherical body 46 removed.

Mechanical processes are generally used to remove spherical particles 46. For example, particles 46 may be removed by ultrasonic / megasonic operation. Most of the spheres 46 are removed during the removal operation of the ultrasonic portion. Ultrasonic operation generally involves placing a wafer in a solution of deionized water with a small volume ratio (eg 1%) of Valtron SP2200 alkaline cleaners (2-butylexethanol and nonionic surfactant), and placing the ultrasonic frequency in the solution. It is done by receiving it. The megasonic operation, which is generally performed after the ultrasonication operation and removes the remainder of the spherical body 46, is generally carried out in another solution of deionized water having a small volume ratio (eg 0.5%) of the Valtron 2200 alkaline cleaner. Positioning the wafer and subjecting the solution to ultrasonic frequencies.

A neutral charge cleaner on the particles 46 may be used in place of the Valtron 2200 cleaner during both megasonic and ultrasonic operation. Charge neutral detergents generally include ionic surfactants. High pressure water jets may instead be used to remove the spheres 46.

Using first layer 50A as an etch mask, insulating layer 44 passes through corresponding layer of dielectric openings (or dielectric aperture openings) 56 through layer 44 below lower non-insulating emitter regions 42. It is etched through the gate opening 54 and the first opening to form a. See FIG. 2E where item 44A is the remainder of insulating layer 44. While the first layer 50A may be slightly impeded by the etching material used to form the dielectric openings 56, the impaired amount is not large enough to significantly affect the shape or size of the first openings 52. Is not. Thus, each first opening 52 remains generally circular, although it has a slightly different diameter than the corresponding gate opening 54.

Electrode dielectric etching to create the dielectric opening space 56 is performed in such a way that the dielectric opening 56 cuts out a portion of the gate layer 48A. The cut out amount is sufficient to avoid depositing later on the emitter cone material accumulated on the sidewall (or side end) of the dielectric opening 56 and to provide an electrical leakage path between the electron-emitting device and the gate layer 48A. Is selected.

The electrode dielectric etch can be performed in a variety of ways, including: undercut etching, wet and dry, (a) isotropic wet etching using one or more chemical etching materials, and (b) undercutting (and thus overall anisotropy). Dry etching, and (c) non-subcutaneous (overall anisotropic) dry etching. When the insulating layer 44 and the first layer 50A are each composed of silicon oxide and silicon nitride, etching is usually performed in two steps. Anisotropic plasma etching is generally performed with carbon tetrafluoride to create vertical openings through insulating layer 44 after an isotropic wet etching is performed with hydrofluoric acid to buffer the initial openings and to form dielectric openings 56. Is performed.

Electrically non-insulating emitter cone material is deposited by evaporation on top of the structure in a direction generally perpendicular to the top surface of insulating layer 44A. The emitter cone material accumulates in the first layer 50A and passes through the gate opening 54 to accumulate on the lower non-insulating region 42 in the dielectric opening space 56. Due to the accumulation of the cone material on the first layer 50A, the opening through which the cone material enters the opening space 56 is gradually approached. As a result, cone bridges accumulate in the dielectric aperture space 56 to form the corresponding conical electron-emitting devices 58A as shown in FIG. 2F. A continuous layer 58B of conical material is formed simultaneously on the first layer 50A. Cone materials are generally metals such as molybdenum, nickel, chromium, or niobium, or refractory metal carbides such as titanium carbide.

The first layer 50A is now removed with a suitable etching material. During removal of layer 50A, excess cone material layer 58B is raised at the same time. 2 shows the resulting electron emitter. Since conical material deposition was generally performed perpendicular to the insulating layer 44A, each electron emitting cone 58A is concentrated vertically on the corresponding first opening 52 and the corresponding gate opening 54.

The gate layer 48A may be patterned into a group of gate line implementations perpendicular to the emitter row electrodes of the lower non-insulated region 42. The gate line is then supported together with the column electrode. With suitable patterning applied to gate layer 48A, the field emitter of FIG. 2G may alternatively be provided with a separate column electrode that contacts gate layer 48A and runs perpendicular to the row electrode. If included, such gate patterning and separated column electrode formation are generally performed prior to etching the insulating layer 44 to form the dielectric opening 56, but may be performed in a later step in the process.

Instead of limiting the gate opening to spherical particles 46 sprayed over the top of the insulating layer 44, the gate openings may be defined by spherical particles sprayed over the gate 읓. Doing so helps to relieve the constraints imposed by the particle diameter on the gate layer thickness.

3 shows one embodiment of a process in which spherical particles are used in accordance with the present invention to produce a gate controlled field emission cathode having a conical electron-emitting device. In the process of FIG. 3, an initial structure consisting of the substrate 40, the bottom non-insulating region 42, and the insulating layer 44 is formed in the same manner as in the process of FIG. 2. 3A, which repeats FIG. 2A, illustrates the initial structure 40/42/44 in the process of FIG.

Electrically non-insulated gate material is deposited on insulating layer 44 to form electrically non-insulating gate layer 60 of relatively uniform thickness. See FIG. 3B. As the gate material in the process of Figure 3, a metal such as chromium, nickel, molybdenum, titanium, or tungsten is generally used. Gate metal deposition can be performed according to one of a number of deposition methods, such as evaporation, sputtering, and “chemical vapor deposition” (CVD). In contrast to the process of FIG. 2, the deposition of the gate material in the process of FIG. 3 need not be performed generally perpendicular to the top surface of the electrode dielectric layer 44. For reasons described below, at a spherical diameter given in the process of FIG. 3, gate layer 60 may be thicker than the maximum allowable thickness of gate layer 48A of the process of FIG. 2.

Hard spherical particles 46 are sprayed over the top of the gate layer 60 as shown in FIG. 3C. In general, the spherical particles 46 are composed of polystyrene again. The particle spraying step is generally carried out in the same manner as in the process of FIG. Injection of particles 46 is optional over the top of gate layer 60. The spheres 46 in the process of FIG. 3 generally have the same characteristics, including the standard diameter with average diameter and average diameter, as in the process of FIG.

A suitably etchable material, again referred to as the first material, is deposited on the gate layer 60 and the spherical particles 46. In the process of FIG. 3, the first material deposition is performed in a direction generally perpendicular to the upper surface of the electrode dielectric 44 using a method such as evaporation or parallel sputtering. Similar to the method of FIG. 2, the first material in the method of FIG. 3 accumulates in the gate layer 60 in the space between the particles 46 to form a first layer 62A of relatively uniform thickness. . See FIG. 3D. The first layer 62A is later supported as a rising layer in the process of FIG. A portion 62B of the first material accumulates simultaneously on the upper half of the sphere 46.

As in the process of FIG. 2, the first material herein generally consists of an inorganic dielectric material such as silicon nitride, aluminum oxide, and / or silicon oxide. Similarly, when the first layer 62A performs a synergistic function, the first material may be either (a) a metal such as aluminum, (b) a metal / dielectric composite, or (c) magnesium fluoride, magnesium chloride, or sodium It can be salt, such as chloride.

In order to prevent the first material portion 62B from being bridged to the first layer 62A, the thickness of the first layer 62A is generally less than the average radius of the sphere 46. Compared to the process of FIG. 2, the overall combined thickness of gate layer 48A and first layer 50A should generally be less than the average radius of spherical body 46 to prevent unwanted bridging. Avoiding is less constrained on the gate layer thickness in the process of FIG. 3 than in the process of FIG. This is particularly the case when the selective etching of the gate layer 60 to the first layer 62A is high during the etching described below to form the gate opening through the layer 60 using the layer 62A as an etching mask. More so when layer 60 is etched much more than layer 62A). For a given spherical diameter, gate layer 60 may thus be thicker than gate layer 48A.

In fact, the gate layer 60 in the process of FIG. 3 may be significantly thicker than the gate layer 48A in the process of FIG. For example, the thickness of the gate layer 60A may exceed the average radius, average diameter of the spheres 46. As the comparative examination of the entire manufacturing process of FIGS. 2 and 3 shows, the method of FIG. 3 requires some additional steps than the method of FIG. In short, compared to the method of FIG. 2, the method of FIG. 3 significantly mitigates the constraint on the gate layer thickness in exchange for a small amount of further fabrication.

Returning to the process of FIG. 3, the spherical particles 46 are now removed in the same manner as in the process of FIG. 2. During spherical removal, the first material portion 62B is simultaneously removed to produce the construct of FIG. 3E. The first opening 64 extends through the first layer 62A at the location of the removed particles 46. Since the particles 46 are spherical, the first opening 64 is nearly circular. In addition, the diameter of each first opening 64 is approximately equal to the diameter of the corresponding removed sphere 46.

Using the first layer 62A as an etch mask, the gate layer 60 is formed through the first opening 64 to form a corresponding gate opening 66 through the gate layer 60 under the insulating layer 44. Is etched through. See FIG. 3F. Item 60A is the remainder of gate layer 60.

Etching to create the gate opening 66 is performed anisotropically. The diameter of each gate opening 66 is approximately equal to the diameter of the corresponding first opening 64. Instead, the gate opening etch is sufficient to prevent the gate opening 66 from fully depositing the bottom of the first layer 62A to prevent subsequent deposition of emitter cone material on the side end of the gate layer 60A along the opening 66. Cutting may be performed in such a way. 3F illustrates a bottom cutting embodiment in which the diameter of each gate opening 66 is larger than the diameter of the corresponding first opening 64.

Without considering how the gate opening etch is performed, each gate opening 66 is vertically aligned and vertically aligned with a corresponding first opening 64. Since the first opening 64 is located at the location of the removed spherical body 46, the particles 46 define the location of the gate opening 66 as well as the first opening 64. Since the first opening 64 is circular, the gate opening 66 is also nearly circular.

The process of FIG. 3 is now completed in much the same way as the process of FIG. Using first layer 62A as an etch mask, insulating layer 44 forms a corresponding dielectric opening (or dielectric aperture opening) 56 through layer 44 below lower non-insulating region 42. To be etched through the gate openings 64 and 66 for the purpose. Reference is made to FIG. 3G where item 44B is the remainder of insulating layer 44. The dielectric aperture 68 is sufficient to avoid subsequent deposition of emitter cone material on the sidewalls of the dielectric aperture 68 and to undercut the layers 60A and 62A to short the electron emitting device and gate layer 60A. do. Etching to create dielectric opening space 56 may be performed by any of the methods described above in electrode dielectric etching in the process of FIG. 2.

The electrically non-insulating emitter cone material is evaporatively deposited on the upper surface of the structure in a direction generally perpendicular to the upper surface of the insulating layer 44B. The emitter cone is again a metal such as molybdenum, nickel, chromium, or niobium or a refractory metal carbide such as titanium carbide.

Conical material accumulates on the first layer 62A and passes through the openings 64 and 66 to accumulate on the lower non-insulating region 42 in the dielectric aperture space 68. Similar to the process of FIG. 2, the opening into which the conical material enters the opening space 68 is gradually approached during the conical material deposition course. The deposition is similarly performed until these openings are completely close. As a result, the cone material accumulates in the opening space 68 to form the corresponding conical electron-emitting device 70A as shown in FIG. 3H. A continuous layer 70B of cone material is formed on the first layer 60A at the same time.

The first layer 62A is removed. During its removal, the excess cone material layer 70B is raised. The resulting electron emitter is depicted in FIG. 3I. In view of the fact that conical material deposition is generally performed perpendicular to the insulating layer 44B, each conical electron-emitting device 70A is perpendicular to the corresponding first opening 64 and the corresponding gate opening 66. Is concentrated.

Patterning the gate layer 60A into a column electrode that runs perpendicular to the emitter row electrode of the lower non-insulating region 42 may be performed in the same way that the gate layer 48A is patterned in the method of FIG. Similarly, with suitable patterning applied to gate layer 60A, the field emitter of FIG. 3I may alternatively be provided with a separate column electrode that contacts a portion of gate layer 60A and runs perpendicular to the row electrode.

As an alternative to the process of FIGS. 2 and 3, the gate opening may be defined by spherical particles sprayed over the layer, referred to as the first layer, formed over the gate layer. In this case, the constraints imposed by the sphere diameter on the thickness of the first layer are generally weakened, depending on the thickness constraints imposed by the sphere diameter on the thickness of the gate layer.

4A-4F and 4G (1) or 4G (2) (collectively "FIG. 4"), a gate in which spherical particles deposited on a first layer are used to define a gate opening in accordance with the present invention. A first part of the process for making a controlled field emission cathode is described. In order to provide a field emitter to the conical electron-emitting device, the process of FIG. 4 can be completed in accordance with the present invention by the latter step of FIGS. 2D-2G or the latter step of FIGS. 3F-3I.

In the process of FIG. 4, an initial structure consisting of the substrate 40, the bottom non-insulating region 42, and the insulating layer 44 is usually formed in the manner described above. See FIG. 4A, which repeats FIG. 2A.

4B, an electrically non-insulated gate layer 60 is formed on the insulating layer 44 according to any one of the deposition methods described above in the method of FIG. For a given sphere diameter, gate layer 60 may be thicker than gate layer 48A in the method of FIG. Similarly, gate layer 60 is generally of a metal such as chromium, nickel, molybdenum, titanium, or tungsten.

A suitable etchable material, referred to as the first material, is deposited on the gate layer 60 to form a first layer 72 of relatively uniform thickness. When the first half process sequence of FIG. 4 is combined with the latter stages of FIGS. 2D-2G or 3F-3I, the first layer 72 is later used as the rising layer. The candidate for the first material consists of the first material candidate given above for the process of FIG. 3.

The first material deposition in the first half sequence of FIG. 4 is performed by various methods such as sputtering, evaporation, CVD, electrochemical deposition (provided when the first layer 72 is electrochemically depositable), rotation, and screen printing. Can be. In contrast to the process of FIGS. 2 and 3, the first material deposition in the process of FIG. 4 need not be performed in a direction generally perpendicular to the upper surface of the insulating layer 44. For the reasons described below, at a given sphere diameter, the first layer 72 may be thicker than one of the first layers 50A, 62A in the method of FIGS. 2 and 3. This is particularly necessary for the increased thickness of the first layer to cover the bumps in the gate layer 60 caused by factors such as the bumps in the insulating layer 44, for example.

Hard spherical particles 46 are sprayed over the top of the first layer 72 as shown in FIG. 4C. The particle spraying step is generally carried out in the manner described above. The spraying of the spheres 46 is thus optional over the top of the first layer 72. Particles 46 generally consist of polystyrene and have the other properties described above.

Appropriately etchable additional material is deposited in the first layer 72 and the spherical particles 46. Deposition of additional material is performed in a direction generally perpendicular to the upper surface of the insulating layer 44 using methods such as evaporation or parallel sputtering. Additional material accumulates in the spaces between the particles 46 to form the additional layer 74A. See FIG. 4D. Portions 74B of additional material accumulate simultaneously in the upper half of the sphere 46.

In order to prevent the additional material portion 74B from bridging to the additional layer 74A, the thickness of the additional layer 74A is generally less than the average spherical radius. However, preventing unwanted bridging along the surface of the sphere 46 is less constrained on the first layer thickness in the process sequence of FIG. 4 than in the process of FIGS. 2 and 3. This is especially the case when the etching selectivity of the first layer 72 to the additional layer 74A is high during the etching described below to form the first opening through the layer 72 using the additional layer 74A as an etching mask ( That is, if layer 72 is etched much more than layer 74A). At a given spherical diameter, the first layer 72 may thus be thicker than the first layer 62A in the process of FIG. 3 or the first layer 50A in the process of FIG. 2. Similarly, the need to avoid such unwanted bridging forces the gate layer to be less thick in the process sequence of FIG. 4 than in the process of FIG. 2 or 3.

If the first half of the process sequence of FIG. 4 is completed by the second half of FIGS. 2D-2G or the second half of FIGS. 3F-3I, the complete process step requires slightly more process operation than the complete process of each of FIGS. 2 and 3. This is a trade that mitigates the restraint on the first layer thickness and also reduces the restraint on the gate layer with respect to the process of FIG.

The material used to form the additional layer 74A can be used as an etch mask to etch the first layer 72A, and can also be selectively etched with respect to the layer 72A. Additional materials generally consist of metals. If the gate material is chromium, the additional material is generally nickel and vice versa. However, depending on the choice of other materials used to make the field emitter, the additional material may be either electrical resistance or electrical insulation.

Spherical particles 46 are now generally removed by the method described above. During spherical removal, the additional material portion 74B is removed simultaneously to create the structure of FIG. 4E. Further opening 76 extends through additional layer 74A at the location of removed particles 46. Since the particles 46 are spherical, the additional opening 76 is about the same diameter as the corresponding removed spherical body 46.

Using additional layer 74A as an etch mask, first layer 72 opens additional opening 76 to form corresponding first opening 78 through layer 72 under gate layer 60. Anisotropically etched through. Reference is made to FIG. 4F where item 72A is the remainder of first layer 72. Each first opening 78 is perpendicular to the corresponding additional opening 76 and has a diameter approximately equal to it. Since the additional opening 76 is placed in the position of the removed spherical body 46, the position of the first opening 78 is defined by the particles 46. In addition, the first opening 78 has a shape substantially the same as that of the additional opening 76 and is therefore almost circular.

With an additional layer 74A that serves as an etch mask, the gate layer 60 is further formed with an additional opening 76 and a first to form a corresponding gate opening 80 through the layer 60 under the insulating layer 44. It may be anisotropically etched through the opening 78. Fig. 4G (1) shows the resulting structure. Item 60B is the remainder of gate layer 60. Since the etching is anisotropic, the diameter of each gate opening 80 is approximately equal to the diameter of the corresponding (overlapping) opening pairs 78, 76. Gate opening etching may be performed as a continuation of the first opening etching or as another step using other anisotropic etching materials.

Each gate opening 80 is vertically concentrated in both the corresponding first opening 78 and the corresponding additional opening 76 and is thus vertically aligned. Since the additional opening 76 is placed in the position of the removed spherical body 46, the position of the gate opening 80 is defined by the position of the particles 46. In addition, the gate opening 80 is almost circular.

The additional layer 74A of (1) of FIG. 4G can now be removed to produce the same structure as the structure of FIG. 2D except for the potential difference in the gate layer and the first layer thickness and the partial difference in the label. have. Each item 60B, 72A, 78, 80 in (1) of FIG. 4G corresponds to item 48A, 50A, 52, 54 in FIG. 2D. Dependent on this label difference, the first half process sequence of FIG. 4 is completed according to the latter step described above from the structure of FIG. 2d to the last structure of FIG. 2g. Thus, conical electron-emitting device 58A extends through gate opening 52 (80) in gate layer 48A (60B) of the completed field emitter.

Instead, when applying the latter part of the method of FIG. 2 to the first half process sequence of FIG. 4, dielectric openings 56 may be formed in insulating layer 44 if additional layer 74A is still in place and supports as an etching mask. have. In this case, the additional layer 74A is immediately removed prior to the conical material deposition of FIG. 2F.

As another alternative, the additional layer 74A is after forming the first opening 78 in the step shown in FIG. 4F and thus before forming the gate opening 80 in the step shown in FIG. 4G (1). Can be removed directly. Using the first layer 72A as an etching mask, the gate opening 80 is partially different from the label (the gate opening 80 in FIG. 4 becomes the gate opening 54 in FIG. 2) and the gate layer and the first It is formed by anisotropically etching gate layer 60 through first opening 978 to produce the structure of FIG. 2D, which is dependent on the potential difference in layer thickness. The process steps from the structure of FIG. 2D to the structure of FIG. 2G are processed in the manner described above to form the field emitter.

Instead of performing anisotropy, etching through the openings 76, 78, without bottom cutting, is performed to form the corresponding gate opening 82 through the insulating layer 44 under the layer 60. It may be implemented in the gate layer of FIG. 4F through openings 76 and 78. Referring to FIG. 4G (2), item 60C is now the remainder of gate layer 60. For the first layer 72A cut below the gate opening 82, the diameter of each gate opening 82 is larger than the diameter of the pair (78) and 76 of the corresponding (overlapping) openings. Each gate opening 82 is largely circular and concentrated perpendicular to the corresponding pair of openings 78, 76. Since the additional opening 76 is placed in the position of the removed spherical body 46, the spherical particles 46 define the position of the gate opening 82.

The additional layer 74A in FIG. 4G (2) can be removed to make the structure, and is substantially the same as the structure of FIG. 3F, except for partial leveling differences and potentially differences in first layer thickness. Items 60C, 72A, 78, and 82 in FIG. 4G correspond to items 60A, 62A, 64, and 66 in FIG. 3F, respectively. Dependent on this leveling difference, the first half of the process sequence of FIG. 4 is now completed according to the above mentioned later steps, which become the structure of FIG. 3i in the structure of FIG. 3f. The conical electron-emitting device 70A is thereby exposed through the gate opening 66 (82) to the gate layer 60A (60C) of the nearly completed field emitter.

As a subsequent alternative to applying the latter part of the processor of FIG. 3 to the first half of the process series of FIG. 4, additional layer 74A may be removed directly after making the first opening 78 at the stage shown in FIG. 4F. Using the first layer 72A as an etch mask, the gate opening 82 is made by performing a bottom cut etch on the gate layer 60 through the first opening to make the structure of FIG. 3F, again partially different. Leveling (gate opening 82 in FIG. 4 becomes gate opening 66 in FIG. 3) and potentially depending on the difference in the first layer thickness. The process steps from the structure of FIG. 3F to the structure of FIG. 3I are then performed to end the field emitter in the method described above.

Now seeing that various electron emitters are manufactured according to the fabrication steps of FIGS. 2 to 4, including the aforementioned parameters, the positions of the cone-like electron-emitting atoms, such as cones 58A and 70A, are defined by the opening 52. Is determined by the position of the first opening, such as (64), (78). Since the position of the first opening is determined by the position of the spherical particles 46, the position of the electron-emitting cone is defined by the piece 46.

The electron-emitting cone is placed randomly or very randomly with respect to one another because the surface distribution of the piece 46 is random, or very random. Nevertheless, the number of electron emitting cones per unit area does not vary very much across the entire electron emitting area.

In each of the electron emitters produced according to the fabrication steps of FIGS. 2 to 4 (which again include the process variables mentioned above), the fundamental diameter of each electron-emitting cone is approximately equal to the diameter of the corresponding first opening and therefore approximately corresponding Is equal to the diameter of the removed opening 46. Therefore, the average fundamental diameter of the electron-emitting cone is controlled by adjusting the average diameter of the pieces 46. Reducing the average piece diameter causes the average cone diameter to be reduced by about the same amount. In this way, the piece 46 determines the lateral area occupied by the electron emitting cone. Since the sphere 46 defines the position of the electron-emitting cone, the average spacing between the cones is controlled by adjusting the average surface density and the average diameter of the sphere 46.

The standard deviation in the average diameter of the pieces 46 is quite small compared to the average piece diameter, as described above. The standard deviation in the mean fundamental diameter of the electron-emitting cone is equally small for the first approximation compared to the mean cone basic diameter. Since the piece 46 is spherical, the basis of each electron-emitting cone is mainly circular. The lateral area occupied by the cone is mainly the same. By appropriately adjusting parameters such as the thickness of the inter-electrode dielectric layer 44, electron emitting devices of a very uniform size and shape can be made.

The electron-emitting devices are usually manufactured to be small and placed close to each other. This is done by using spheres with moderately small average sphere diameters and by appropriately distributing the high density of the spheres 46 across the surface that the spheres receive. Since there is a small change in the size and shape of each electron emitting cone for a particular area electron emitter, the electron emission is relatively uniform over the electron emitting area. Importantly, this very desirable feature is mainly achieved by controlling the size and surface density of the piece 46, thereby making it possible to control the electron current well.

Fabrication of Field Emitters Using Electron-emitting Filaments

A gated field-emitting cathode having an electron-emitting device shaped more like a filament than a cone may be used to complete the first half of the process of FIG. 4 as shown in (1) of FIG. 4G, or a portion of the first half of the process of FIGS. It can be produced according to the techniques of the invention by using a suitable series of late filament processes to complete.

5A to 5G (collectively "FIG. 5") employ a spacer in accordance with the present invention for producing a gated field emitter having an electron-emitting device, applying the first half of FIGS. 4F and 4G1 to FIG. The latter process series is shown. With respect to (1) of FIG. 4G, the anisotropic etching is performed through the corresponding non-dielectric opening 100 through layer 44 under additional opening 76, first opening 78, and lower non-insulating region 42. It is carried out to the insulating layer 44 through the gate opening 80 using the additional layer 74 as an etching mask to form a. This results in the structure of FIG. 5A in item 44C, which is the remainder of insulating layer 44. Each non-dielectric opening 100 is vertically concentrated and is the same diameter as the three corresponding openings 76, 78 and 80. In addition, the non-dielectric opening 100 is mainly circular.

The additional layer 74A is removed with an etchant that does not significantly penetrate the first layer 72A or any other portion of the structure. 5B shows the resulting structure.

A suitably etchable spacer (or coating) material is used below the low non-insulating area 42 to form the blank spacer (or coating) layer 102 as shown in FIG. 5C and the first layer 72A. Properly settles into the composite opening 78/80/100 The spacer layer 102 covers the top of the structure but does not completely fill the opening 78/80/100. In the unfilled portion of / 80/100. Each depression 104 is vertically concentrated in the corresponding composite opening 78/80/100.

CVD is typically used to place on spacer material. Thus, the thickness of the spacer layer 102 along the lateral edges of the layers 72A, 60B, 44C along each composite opening 78/80/100 is relatively uniform (constant) at any given height.

The spacer material is typically chosen to be generally etchable using the primary material of layer 72A. The spacer material also usually has a high etch selectivity for the interelectrode non-dielectric, where layer 44C. In particular, the spacer material is typically the same as the main material and different from the interelectrode non-dielectric. For example, the spacer material is usually silicon nitride when (a) the main material consists of silicon nitride and (b) the interelectrode non-dielectric consists of silicon oxide.

Anisotropic etching includes (a) the side end of the first layer 72A along the first opening 78, (b) the side end of the gate layer 60B along the gate opening 80, and (c) the non-dielectric Except for the portion 102A that covers the side ends of the insulator layer 44C along the opening 100, all of the spacer layer 102 is implemented to be substantially removed. See FIG. 5D. Since a portion of the center of the spacer layer 102 at the bottom of the non-dielectric opening 100 is removed due to the etching, the depression 104 extends below the low non-insulating area 42 and slightly to the corresponding gap 104A. Widen (not shown in FIG. 5D). Since the depression 104 is concentrated vertically in the composite opening 78/80/100, each gap 104A is vertically concentrated in the corresponding composite opening 78/80/100.

The electrically non-insulating emitter filament material is electrochemically deposited (electroplated) into the gap 104A to form the corresponding precursor electron-emitting device 106 in contact with the low non-insulating region 42. 5E shows the resulting structure. During electrochemical precipitation, the combination of the first layer 72A, the spacer portion 102A, and the insulating layer 44C is the precursor of the gate layer 60B (except as far along the side of the structure as possible). The capsule is enclosed in order to prevent contact between the electron-emitting device 106 and the layer 60B. The lateral spacing between the gate layer 60B and the precursor element 106 is determined by the thickness of the spacer 102A.

Emitter filament materials are usually metals such as nickel or platinum. When the rolled filament 106 is later sharpened by electrogloss technology, the filament material is usually different from the gate material.

Electrochemical precipitation is typically done by the method described herein by Spindt et al. In US Pat. No. 5,564,959. During electrochemical precipitation, the low non-insulating area 42 is used as the precipitation cathode. The settling anode is placed in the settling electrolyte a short distance over the first layer 72A.

Electrochemical precipitation takes a long time to overfill the gap 104A but is not the cause for the precursor electron-emitting device 106 to meet another along the top of the first layer 72A. Thus, each rolling element 106 has a portion of the cap that is an extension of the corresponding gap 104A. Excessive filling of gap 104A helps to ensure final electron-emitting filaments will not be excessive filling of significantly different heights due to differences in nucleation and growth of filament material.

The first layer 72A and the spacer 102A are usually removed with an etchant but do not significantly penetrate the insulating layer 44C. See Figure 5f. As a result of etching, the precursor electron-emitting device 106 is separated into the gate layer 60B and the insulating layer 44C by the cylindrical gap 108.

When the first layer 72A and the spacer 102A are made of the same material (i.e. silicon nitride), etching is typically performed in one step with wet chemicals. Instead, a plasma having anisotropic components can be used to perform the etching. Etching may be done in two stages when layer 72A and spacer 102A are formed of different materials.

The precursor element 106 is processed to remove the cap 106A and provides with a sharp tip a portion of the remaining filament that at least partially extends through the gate opening 80. 5G shows that the final gate field emitter in the electron-emitting device 106B of the sharpened filament becomes the remainder of the precursor device 106. Since the gap 104A is vertically concentrated at the compound opening 78/80/100, each electron-emitting filament 106B is vertically concentrated at the corresponding gate opening 80.

The conversion of the precursor electron-emitting filament 106 to the electron-emitting filament 106B is usually done electrochemically according to the electro-gloss / sharpening technique of the kind described in the above-cited US Pat. No. 5,564,959. The low non-insulating emitter region 42 in the junction is used as the anode during the electropolished / sharpening operation with the precursor element 106. Gate layer 60B functions as a cathode. During electropolished / sharpening operation, the material of the precursor element 106 is generally removed along the plane of the gate layer 60B, causing the element 106 to fit tightly and form a sharpened tip. The cap portion 106A is washed out of the electropolished / sharpened electrolyte and the electron-emitting filament 106B remains as shown in FIG. 5G.

Since the gate opening 80 is vertically concentrated into the additional opening 76, each gate opening 80 is vertically concentrated at the position of the corresponding removed sphere 46. Therefore, the position of the electron-emitting filament 106B is defined by the spherical particle 46 (the position of).

In addition, the diameter of each gap 104A is obtained by subtracting twice the thickness of the corresponding spacer 102A from the diameter of the corresponding composite openings 70/80/100. Since the diameter of each composite opening is approximately equal to the corresponding removed spherical body 46, the side area occupied by the filament 106B is controlled by the size of the spherical body 46 and the thickness of the spacer 102A. do.

The spacer thickness varies slightly from spacer 102A to spacer 102A. As mentioned above, the size of the spherical fragments varies slightly from one sphere 46 to the other. Since the surface density of the spherical body 46 does not differ significantly over the first layer, the spherical size and surface density in the combination by spacer thickness is such that the filament 106B passes through the electron emission region at a controllable size of the electron current. It may be adjusted appropriately to provide electron emission.

Instead of starting the latter process series of FIG. 5 from the structure of FIG. 4G (1), the additional layer 74A can be removed directly after the step shown in FIG. 4F. The etching mask, gate layer 60, and insulating layer 44, together with the first layer 72A, are now formed through the first opening 78 (and through the gate opening 80) to produce the structure of FIG. 5B. Toward anisotropically). A two stage etch process typically uses one stage for layer 60 and a second stage for layer 44. In this regard, the structure of FIG. 5B is subsequently processed in the method described above in FIG. 5C to FIG. 5G.

Some of the first half of the method of FIGS. 2 and 3 can be combined with the latter process series of FIG. 5 in a manner similar to that described above. Starting from the structure of FIG. 2D, the non-dielectric opening 100 is insulated by performing anisotropic etching to the layer 44 through the openings 52 and the openings 54 using the first layer 50A as an etching mask. It may be made through layer 44. Except for the partially different leveling and dislocation differences in first layer and gate layer thickness, the structure of FIG. 5B is produced.

Similarly, starting with the structure of FIG. 3E, the gate opening 80 and the non-dielectric opening 100 may pass through the gate layer 60 and the insulating layer through the first opening using the first layer 62A as an etching mask. 44) can be made by anisotropically etching. Anisotropic etching is typically performed in two stages, one for layer 60 and the second stage is performed by layer 44. Depending on the partial difference in leveling and potentially different 쩨 2 layer thicknesses, the structure of FIG. 5B is produced again.

In the alternatives described in the three paragraphs above, since the gate openings were vertically concentrated with the first openings 78, 64, and 52, each gate opening 80, 66, and 54 has a corresponding removed sphere. It is concentrated vertically at the position of the sieve 46. The sphere 46 therefore defines the position of the electron-emitting filament 106B. The combination of sphere 46 and spacer 102A also controls the side area occupied by filament 106B. Thus, the filament 106B can provide high uniform electron emission at a controlled size by suitably adjusting the spherical size and surface density in combination with the spacer thickness.

FIG. 6 shows another later processor series using spacers in accordance with the invention of the gated field emission cathode applied to the first processor series of FIGS. 4F and 4G1 in FIG. 4A and supporting the electron-emitting device of the filament. After forming the structure of FIG. 4G (1), the additional layer 74A is removed. This becomes the structure of FIG. 6A.

A suitably etchable spacer (or coating) material is suitably deposited into the first layer 72A and the composite opening 78/80 to form the blank spacer (or coating) layer 110 as shown in FIG. 6B. do. The spacer layer 110 covers the top of the structure but does not completely fill the openings 78/80. The depression 112 is present in the unfilled portion of the opening 78/80. Each depression 112 is centered perpendicularly to the corresponding composite opening 78/80.

CVD is commonly used to precipitate spacer materials. The thickness of the spacer layer 110 along the side edges of layer 72A and layer 60B along each composite opening 78/80 is relatively uniform at any given height. The spacer material in the process series of FIG. 6 has the same properties as for the non-dielectric between the first material and the electrode as in the process series of FIG. 5.

The anisotropic etching is performed by (a) the side edge of the first layer 72A along the first opening 78 and (b) the annular portion covering the side edge of the gate layer 60B along the gate opening 80 ( To substantially remove all of the spacer layer 110 except for 110A). See Figure 6C. The depression 112 extends under the insulating layer 44 and slightly widens to correspond to the corresponding gap 112A (not shown in FIG. 6). Since the recesses 112 are vertically concentrated in the openings 78/80, each gap 112A is vertically concentrated in the corresponding openings 78/80.

By using the first layer 72A and the annular spacer portion 110A as an etching mask, the insulating layer 44 opens the non-dielectric opening 114 through the layer 44 below the low non-insulating region 42. It is anisotropically etched through the gap 112A to form. See Figure 6d. Item 44D is the remainder of insulating layer 44.

The electrically non-insulating emitter filament material is electrochemically deposited into the composite openings (or gaps) 112A / 114 for forming the precursor electron-emitting filaments that contact the non-insulating 42. The resulting structure is shown in FIG. 6E. Because of the electrochemical precipitation, the combination of the first layer 72, the spacer 110A, and the insulating layer 44D has a gate layer 60B to prevent the precursor electron-emitting device 116 from contacting the gate layer 60B. Encapsulate) (except along the sides of the structure as far as possible). Spacer 116A determines lateral voids between gate layer 60B and precursor element 116. The emitter filament material is again usually a metal such as nickel or platinum.

Electrochemical precipitation is carried out in the manner described above for the processor series of FIG. 5. The settling time is long enough to overfill the opening 112A but is typically not long enough to cause the precursor element 116 to meet the other along the top of the first layer 72A. Each precursor electron-emitting device 116 thus has a portion of the cap 116A extending in the corresponding gap 112A / 114. As in the process series of FIG. 5, excessive filling reduces the likelihood of generating electron-emitting filaments of significantly different heights due to differences in nucleation and growth of the filament material.

The first layer 72A and the spacer 110A are removed and an etchant is usually used that does not significantly penetrate the insulating layer 44D or the gate layer 60B. See Figure 6f. The outer part of the gate opening 80 is opened again for it. This portion of the gate opening 80 now separates the precursor element 116 from the gate layer 60B. When the first layer 72A and the spacer 110A are formed of the same material, etching is typically performed in one step using a wet chemical or anisotropic plasma. Two stage etching processes are commonly used when layer 72A and spacer 110A are made of different materials.

The precursor electron-emitting device 116 is processed to remove the cap portion 116A and to provide a portion of the filament that remains with the sharpened tower that extends at least partially through the gate opening 80. The electron-emitting device 116B of the filament eroded in FIG. 6G is the remainder of the precursor element 116. Electron-emitting filament 116B is made from the precursor element by an electro-gloss / sharpening technique in substantially the same manner used to produce electron-emitting filament 106B. Thus, each electron-emitting filament 116B is vertically concentrated in the corresponding gate opening 80.

Using gate layer 60B as an etch mask, insulating layer 44D having a bottom cut, typically an isotropic, method for forming corresponding dielectric dielectric space 118 around electron emitting filament 116B. Is etched through the gate opening 80. 6H shows the resulting structure. Item 44E is the remainder of insulating layer 44D. The open void 118 of the non-dielectric may extend partially or fully through the insulating layer 44E. 6H shows complete through the case.

The electroglossy / sharpening step may be performed before making the non-dielectric open void 118. The final structure is virtually identical to that shown in FIG. 6B. Instead, an open dielectric 118 of non-dielectric may be formed by anisotropic etching so that open void 118 does not cut down gate layer 60B.

Since each gate opening 80 is vertically concentrated at the position of the corresponding removed spherical body 46, the position of the spherical particles 46 defines the electron-emitting filament 116B. Similar to the process of FIG. 5, the lateral area occupied by filament 116B is controlled by sphere 46 and spacer 110.

Instead of starting the latter process series of FIG. 6 in the structure of FIG. 4G (1), the latter process series may begin in the structure of FIG. 4F. The additional layer 74A is removed. Using first layer 72A as an etch mask, gate layer 60 is anisotropically etched through first opening 78 to produce the structure of FIG. 6A.

Some of the first half of each process of FIGS. 2 and 3 may also be completed with the latter process series of FIG. 6 in accordance with the invention for producing gated field emitters having filament electron-emitting devices. Depending on the partial differences in leveling and potential differences in the thicknesses of the first and gate layers, the structure of FIG. 6A is the structure of FIG. 2D for use as a junction for the first half of the process of FIG. 2 and the latter process series of FIG. 6. Repeat.

The structure of FIG. 3E is used as a junction for the first half of the process of FIG. 2 and the latter process series of FIG. 6. 3E, the gate opening 80 is made by anisotropically etching the gate layer 60 through the first opening using the first layer 62A as the etching mask. According to the partial difference in leveling and potentially different first layer thickness, the structure of FIG. 6A is produced again.

In the alternative described in the two previous paragraphs, the position of the filament 116B is again defined by the piece 46. As such, sphere 46 and spacer 110 control the lateral area occupied by filament 116B. The spherical size and surface density may then be appropriately varied so that the filament 116B provides a high uniform electron emission at a controlled size, depending on the spacer thickness.

7A to 7J (collectively “FIG. 7”) are examples of previous processes for producing gated field-emitting cathodes in which spherical particles are used to define gate openings and utilized to make filament electron-emitting devices in accordance with the invention. To present. In the process of FIG. 7, the initial structure configuration of the substrate 40, the low non-insulating region 42, and the insulating layer 44 is formed in substantially the same manner as the process of FIG. 2. Repeated FIG. 2A shows a structure 40/42/44 for the process of FIG. 7. As such, as shown in FIG. 7B, the solid spherical piece 46 is distributed past the top of the insulating layer 44. The spherical precipitation is carried out randomly or very randomly according to the techniques described above for the process of FIG. 2.

Electrically non-insulated gate material is usually deposited in insulating layer 44 and spherical particles 46 in a direction that is substantially perpendicular to the upper surface of layer 44 using techniques such as evaporation or aimed sputtering. Gate material accumulates in the insulating layer 44 in the gaps between the pieces 46 to form electrically non-insulating gate layers 120A of uniform thickness, respectively. See FIG. 7C. A portion of the gate material 120B accumulates simultaneously in the upper half of the sphere 46. In order to avoid bridging the gate material portion 120B to the gate layer 120A, the thickness of the gate layer 120A is usually less than the average spherical radius. The gate material typically consists of a metal such as chromium, nickel, molybdenum, titanium, tungsten, or gold.

The spheres 46 are typically removed according to the techniques utilized in the process of FIG. During removal of the sphere, gate material portion 120B is removed to produce the structure of FIG. 7D. Gate opening 122 extends through gate layer 120A at each location of removed piece 46. The gate opening 122 is largely circular because the piece 46 is spherical. The diameter of each gate opening 122 is approximately equal to the diameter of the corresponding removed spherical body 46. Since the gate opening 122 is made during the deposition of the gate layer 120A without the need for gate layer etching, the gate material may be gold here.

A suitably etched spacer (or coating) material is typically gated 120A under insulating layer 44 to form a blank spacer (or coating) layer 124 as shown in FIG. 7E in a conformal method. Above and into the gate opening 122. The spacer layer 124 covers the top of the operation but does not completely fill the gate opening 122. Depression 126 is present in the unfilled portion of gate opening 122. Each depression 126 is vertically concentrated at the corresponding gate opening 122.

With the CVD used to deposit the spacer material, the thickness of the spacer layer 124 at the side edges of the gate layer 120 along each gate opening 122 is each uniform at any given height. The spacer material is selected to be able to selectively etch the non-dielectric between the gate material and the electrode. The spacer material is typically an electrical insulator, such as silicon nitride (shown in FIG. 7E) but cannot be an electrical non-insulator, for example a metal such as aluminum. When the spacer material is made of metal, the spacer material precipitation can be performed electrochemically. In this case, precipitation is typically not conformal beyond the upper surface of the structure.

Anisotropic etching is performed to remove virtually all of the spacer layer 124 except for the portion 124A that covers the side edges of the gate layer 120A along the gate opening 122. See Figure 7f. A portion of the center of the spacer layer 124 at the bottom of the gate opening 122 is removed during etching so that the depression 126 extends through the spacer layer 124 below the insulating layer 44 and becomes a gap 126A. Slightly widened (not shown in FIG. 7F).

Each spacer portion 124A is a very small one, as shown in FIG. 7F. To more clearly describe the spacer 124A, FIG. 8A presents an expanded view of a portion of the structure of FIG. 7F focused around the intended location by the left electron emitting device.

Gate layer 120A and spacer 124A are used as an etch mask, and insulating layer 44 is used to form a corresponding non-dielectric opening 128 through layer 44 under low non-insulating region 42. Anisotropically etched through the gap 126A. See Figure 7g. Item 44F is the remainder of insulating layer 44. Since the depression 126 is vertically concentrated at the gate opening 122, each composite opening 126A / 128 is vertically concentrated at the corresponding gate opening 122.

The electrically non-insulating filament material is electrochemically deposited into the composite openings (or gaps) 126A / 128 to form a precursor electron-emitting device that contacts the low non-insulating region 42. 7H shows the resulting structure. Electrochemical precipitation is again typically carried out by the method described in US Pat. No. 5,564959, cited above. As such, the emitter filament material metal is again usually a metal such as nickel or platinum.

The settling time is long enough to completely fill the non-dielectric opening 128 and enough to partially fill the gap 126A, but each precursor electron-emitting device 130 extends laterally beyond its spacer 124A. Thus, the precursor element 130 is separated laterally from the gate layer 120A by the spacer portion 124A (thickness). Since the spacer 124A is a small one illustrated in FIG. 7H, FIG. 8B shows an expanded view of a portion of the structure of FIG. 7H centered on the precursor element 130 on the left.

The spacer portion 124A is removed using an etchant that does not significantly penetrate the gate layer 120A. The gate layer 120A is used as an etching mask and the insulating layer 44F is typically isotropic undercut, which is a method for forming a corresponding non-dielectrically open spacer 132 around the precursor electron-emitting device 130. Not etched through the gate opening. Item 44G in FIG. 7I is the remainder of insulating layer 44F. The non-dielectric open spacer 132 may be partially or fully extended through the insulating layer 44G. 7i is shown in part through the case.

Electro-gloss / sharpening operation is processed to provide a precursor electron emitting device with a sharpened tip. 7J shows the resulting structure. The electron-emitting device 132A of the filament is the sharpened remainder of the precursor device 130. Electro-gloss / sharpening operation is again performed according to the kind of technique described in US Pat. No. 5,564,959.

The operations shown in FIGS. 7I and 7J can be reversed. That is, the precursor element 130 may be electropolished / sharpened to form the electron-emitting filament 130A after the non-dielectric open spacer 132 is formed around the element 130A. In addition, the open spacer 132 may be formed by anisotropic etching so that the spacer does not significantly cut down the gate layer 120A.

In some cases, with the composite openings 126A / 128 centrally concentrated at the gate opening 122, each filament electron-emitting device 130A is vertically concentrated at the corresponding gate opening 122. Since each gate opening 122 is concentrated perpendicularly to the corresponding removed spherical body 46, the spherical particles 46 define the position of the filament 130A. The side area occupied by the filament 130A is controlled by the diameter of the sphere 46 and the thickness of the spacer 124. The filaments 130B can be aligned to provide high uniform electron emission at a controlled size by appropriately adjusting spherical size and surface density along the spacer thickness.

9A to 9C (collectively "FIG. 9") illustrate an expanded set of processes in which the structure of FIG. 7G can be applied to fabricate a gated field-emitting cathode having an filament electron-emitting device according to the invention. do. In the process of FIGS. 7A-7G and 9, the spacer portion 124A is made of an electrically non-insulating material, usually a metal, which can selectively etch the emitter filament material and the gate material. For example, when (a) the gate material is chromium and (b) the filament material is nickel, the spacer material of some 124A is typically aluminum. Further, as described more fully below with respect to FIG. 14, the low non-insulating emitter region 42 in the process series of FIG. 9 consists of a lower electrically conductive layer and an electrically resistive layer thereon.

Starting with the structure of FIG. 7G, the emitter filament material is electrochemically precipitated into the composite gap 126A / 128 to form the electron-emitting device 134 of the rolled filament. During electrochemical precipitation, gate layer 120A acts as a control electrode. The non-insulating spacer 124A is used as part of the electrode in contact with the gate layer 120A. The precipitation anode is placed in the precipitation electrolyte. The low non-insulating emitter region 42 is the precipitation anode. Since the filament material precipitated into the non-dielectric opening 126A contacts the low non-insulating region 42, the filament material accumulated in the gaps 126A / 128 is used as part of the precipitation anode.

The low conductivity layer of the low non-insulating region 42 is maintained at a voltage sufficient for the emitter filament material to electrochemically accumulate in the non-dielectric opening 126A in the resistive layer above the non-insulating region 42. Gate layer 120A, on the other hand, is maintained at a voltage that is insufficient for the filament material to electrochemically accumulate in the control electrode formed with gate layer 120A and non-insulating spacer 124A.

Accumulation of the filament material in the non-dielectric opening 126A continues until the precursor electron-emitting filament 134 contacts the non-insulating spacer 124A as indicated by point 136 in FIG. 9A. When each rolled filament 134 is in contact with its non-insulated spacer 124A, the filament 134 is electrically shorted to the control electrode formed of the gate layer 120A and the non-insulated spacer 124A. The voltage of each shorted filament 134 varies from a settling anode sufficient for electrochemical settling of the filament material to a control-electrode value that is insufficient for settling the filament material. Thus, the electrochemical precipitation of filament 134 ends.

When each precursor filament 134 is electrically shorted to the control electrode, control-electrode current flows through the portion underlying the upper resistive layer in the filament 134 and the low non-insulating region 42. Each shorted filament 134 and some coupling resistance R _D underneath the upper resistive layer causes a voltage drop V _D to pass past the portion underneath the filament 134 and low resistive layer. .

For each electrically shorted filament 134, the value of the coupling resistance R _D is determined by changing the voltage drop V _D from a change in the value sufficient for electrochemical precipitation of the filament material. High enough to reach an appropriate value to prevent the precipitation-anode. Thus, the end of precipitation of one precursor filament 134 has some effect on the precipitation of another precursor filament 134. Precipitation of all of the precursor filaments 134 actually terminates when each of them independently contacts its non-insulating spacer 124A. The filament material is thus far enough to cause the rolled filament 134 to connect to the gate layer 120A and cannot inflate outside of the gap 126A.

Using a suitable etchant that does not significantly penetrate the gate layer 120A or the precursor electron emitting filaments, the spacer portion 124 is removed to produce the structure of FIG. 9B. Electro-gloss / sharpening operation is performed to convert the precursor element into the electron-emitting device 134A of the sharpened filament as shown in FIG. 9C.

Using the gate layer 120A as an etch mist, the insulating layer 44 is intended to form a corresponding non-dielectric open space 138 around the electron-emitting filament 134A, which is not cut below, typically isotropic. The method is etched through the gate opening 122. Item 44H in FIG. 9C is the remainder of insulating layer 44F. Electro-gloss / sharpening operations can be performed before and after etching to make the non-dielectric open space 138. In either case, the structure of FIG. 9C is processed according to the method described above.

Regardless of whether the non-dielectric open space 138 is made before or after the electropolished / sharpened operation, the electron-emitting device 134A of each filament is concentrated perpendicularly to the corresponding gate opening 122. Thus, the spherical body 46 defines the position of the electron-emitting filament 134A. In addition, the sphere 46 and the spacer 124A control the side area occupied by the filament 134A. The uniformity and size of the electron emission from the filament 134A is then controlled by suitably varying the spherical size and surface density in the bond depending on the spacer thickness.

The technique utilized to automatically terminate the electrochemical precipitation of the filament material in the process series of FIG. 9 can be applied to processes involving the process series of FIG. 6A through FIG. 6D. In this case, the annular spacer portion 110A is usually made of a metal, electrically non-insulating metal, which can be selectively etched against the filaments and gate material. Spacer portion 110A may also be selectively etched for the primary material. The major layer 72A is again made of an electrically non-insulating material, which is usually a metal such as aluminum that can be selectively etched against the filaments and gate material. The low non-insulating region 42 again consists of a low conductive layer and an upper resistive layer as described later with respect to FIG. 14.

Beginning with the structure of FIG. 6D, electrochemical precipitation of emitter filament material is performed with an electrochemical cell in gate layer 60B that acts like a control electrode. Since the spacer portion 110A is in contact with the gate layer 60B, the spacer 110A acts as part of the control electrode. When the precipitation anode is in the precipitation electrolyte, the low non-insulating emitter region 42 is the precipitation anode. The filament material is deposited into the non-dielectric opening 114 and used as part of the precipitation anode.

When the filament material accumulating in each non-dielectric opening 114 contacts the corresponding spacer portion 110A, a settling anode for the electron-emitting filament 116 is formed in the opening 114 electrically shorted to the control electrode. do. This ends the electrochemical precipitation of the filament material into the opening 114. A precursor electron emitting filament having a shape similar to the precursor filament in FIG. 9A is formed in the non-dielectric opening 114.

First layer 72A and spacer portion 110A are subsequently removed. The electron gloss step is performed to sharpen each electron emitting filament, and the etching is performed through the gate opening 80 to create a non-dielectric open space around the filament. As in the process series of Figures 6, 7, and 9, any of these steps may be performed first. The resulting structure is generally shown as the open aperture space of the non-dielectric shown in FIG. 6H or 7J extends completely or partially through the insulating layer 44.

In the process / process sequence of FIG. 5 to FIG. 7, spacers are made by precipitating a blank layer of spacer material and removing unnecessary portions of the blank layer. Spacers, however, may be formed by selective precipitation techniques in some circumstances. The required environment typically occurs when a gate layer is exposed along its side edges but not along its top or bottom surface.

10A to 10G (collectively " FIG. 10 ") are applied to the first half of the process series of FIG. 3F in FIG. 3A and selectively spacer precipitation in accordance with the present invention for producing a gated field-emitting cathode having a filament electron emitting device Represents a series of late processes that utilize. As illustrated in FIG. 10A, which repeats FIG. 3F, each gate opening 66 is slightly larger than the first opening 64 corresponding to the later process series in FIG. 10, so that the gate opening 66 is formed of the first layer 62A. Slightly cut down). Nevertheless, each gate opening 66 may be substantially the same diameter as the corresponding first opening 64. Regardless of whether the gate opening 66 is cut below the first layer 62A or not, only the side edges of the gate layer 60A are exposed.

An electrically non-insulating spacer (or coating) material that uses an electrochemical technique and can be appropriately etched is the gate layer 60 along the gate opening 66 for forming an annular electrically non-insulating spacer 140. Is selectively deposited on the exposed edges of See Figure 10b. The gap 142 extends through the annular spacer 140, respectively. Each gap 142 is vertically aligned with a corresponding annular spacer 140. Electrochemical precipitation is carried out for a sufficiently long time and the diameter of each gap 142 is significantly less than the diameter of the corresponding gate opening 64.

During electrochemical spacer precipitation, gate layer 60A is a precipitation cathode. Because spacers 140 contact gate layer 60A, spacers 140 form portions of the cathode as they grow along the gate edge. The precipitated anode is placed in the veteran electrolyte.

Spacer 140 may selectively etch the gate layer 62A, insulating layer 44, and backing material used to fill the electron emitting filaments. The spacer material is a material such as copper or nickel that differs from the gate material and is different from the filament material.

The gate layer 62A and the spacer 140 are used as an etching mask, and the non-insulating layer 44 forms a corresponding non-dielectric opening 144 through the insulating layer 44 under the low non-insulating region 42. In order to do so, they are etched anisotropically through the gate opening 64 and the gap 142. 10C shows the resulting structure. Item 44I is the remainder of insulating layer 44. The sidewalls of the non-dielectric openings 144 are very vertical. Because each gap 142 is smaller than the corresponding gate opening 64, the diameter of each gap 144 is approximately equal to the diameter of the opening 142 of the corresponding dielectric.

The electrically non-insulating emitter filament material is electrochemically precipitated into the non-dielectric opening 144 for forming the precursor electron-emitting filament 146 in contact with the low non-insulating region 44. Filament precipitation is effected until the precursor filament 146 contacts or nearly contacts the spacer 142. Electrochemical filament precipitation is typically performed according to the techniques generally described in US Pat. No. 5.564,959. Filament precipitation is terminated after the selected precipitation time or according to the automated technique utilized in the process series of FIG. 9.

During electrochemical filament deposition, the combination of the first layer 62A, spacer 140, and insulating layer 44I is used to prevent gate electron emission filament 146 from contacting gate layer 60A. Encapsulate (except as far as possible around the side of the structure). Spacer 140 determines the side spacing between the rolled filament 146 and the gate layer 60A. Each filament 146 is vertically concentrated at the corresponding gate opening 64 so that it is also vertically concentrated at the position of the corresponding removed spherical body 46.

The first layer 62A and spacer 140 are removed to produce the structure shown in FIG. 10E. The first layer 62A may be removed before the removing spacer 140 is removed or vice versa. Instead, when the etchant can etch the spacer and the main material, the first layer 62A and the spacer 140 can be removed at the same time. In some cases, the removal operation is performed with an etchant that does not significantly penetrate the gate layer 60A or the precursor electron-emitting filament 146. The gate opening 66 is opened again by it. Because each reopened gate opening 66 and the corresponding non-dielectric opening 146 are concentrated in the corresponding first opening 64, each filament 146 is concentrated vertically in the corresponding gate opening 66. do.

The gate layer 60A is used as the wound mask, and the insulating layer 44I uses the gate opening 66 to form a non-dielectric open space 148 around the precursor electron emission filament 146 as shown in FIG. 10F. Is etched through). Item 44J is the remainder of insulating layer 44I. Etching may be performed at an isotropic method, the position described in FIG. 10F. Instead, etching may be performed in a method that is partially or completely isotropic such that the non-dielectric open aperture space 148 cuts under the gate layer 60A. Open spacer 148 may be partially or fully extended through insulating layer 44J. 10F completely describes the situation.

Electro-gloss / sharpening operations are performed on the rolled electron-emitting filament 146 to provide a sharpened tip with them. See Figure 10g. Item 146A is the sharpened remainder of the rolled filament 146. Once again, electropolish / sharpening operation is performed according to the kind of technique described in US Pat. No. 5,564,959.

3A to 3F, and the process of FIG. 10 can be modified in various ways. The first half process series of FIG. 2D in FIG. 2A may be replaced with the first half process series of FIG. 3F in FIG. 3A. As such, the first half process series (deformation of (1) of FIG. 4G or deformation of (2) of FIG. 4G) accompanied by removal of the additional layer 74A is the process sequence of FIG. 3A to FIG. 3F. Can be replaced. Electro-gloss / sharpening operations on the precursor electron-emitting filament 146 may be performed prior to making the non-dielectric open space 148.

In the final structure, each electron-emitting filament 146A is vertically concentrated in the corresponding gate opening 66. As the removed sphere 46 defines the position of the gate opening 66, the removed sphere 46 defines the position of the filament 146A. The side area of each electron-emitting filament 146A is controlled by the diameter of the corresponding removed spherical body 46 and the side thickness of the corresponding spacer 140. By suitably adjusting the spherical size and the flake surface density in accordance with the spacer thickness, the filament 146A can provide high uniform electron emission.

In the process of FIGS. 2 and 7, the gate opening 54 and the gate opening 122 remain after removal of the spherical particles 46 as shown in the gate material. However, the gate opening 54 and the gate opening 122 are actually made in the gate layer 48A and the gate layer 120A at the same time as the gate material is deposited. A similar description applies the first opening 64 to the process of FIG. 3 and the subsequent opening 76 to the process series of FIG. 4.

11A to 11H (collectively " FIG. 11 ") are shown in FIG. 11A and before spherical body 46 is removed and in spherical particles 46 utilized to define gate openings in the manufacture of gated field emission cathodes. The process sequence in the spacer material that precipitates into the gate opening is described. The time point for the process series of FIG. 11 is the structure 40/42/44 of FIG. 7A. The sphere 46 is formed after the gate material precipitation is generally performed in a direction perpendicular to the upper surface of the layer 44 for forming the gate layer 120A and excess gate material portion 120B, as shown in FIG. 7B. It is deposited on top of the insulating layer 44. In the structure of FIG. 7C this result is repeated here as in FIG. 11A. The gate opening 122 in the gate layer 120 is clearly shown in FIG. 11F. The gate layer thickness in FIG. 11A is typically less than the gate layer thickness in the fabrication process of FIG. 7.

A properly etchable spacer material, typically an electrical insulator, is deposited on top of the structure to form a spacer (or cover) layer 150A over the gate layer 120A as shown in FIG. 11B. The spacer layer 150A is placed in the spacers between the spheres 46. Precipitation of the spacer material is performed in the same manner as the method formed in the gate opening 122 on the insulating layer 44 under the annular portion 150B fragment 46 of the spacer layer 150A. A portion 150C of the spacer material is simultaneously accumulated in a portion of the gate material 120B lying in the sphere 46. To avoid connecting a portion of excess spacer material 150C to spacer layer 150A, the overall thickness of layers 150A and 120A is usually less than the average radius of sphere 46.

Spacer material precipitation is typically performed by uniform non-targeted techniques such as untargeted sputtering or plasma-enhanced CVD (i.e., sputtering at actual diffusion to the natural angle of incidence of the colliding atoms of the sputtered material). do. During non- aiming sputtering, the pressure is usually 10 to 100 millitorr. Non-targeted spacer material precipitation can also be performed by angled rotational techniques such as angled rotary sputtering or angled rotary evaporation. In angular precipitation, the spacer material is the upper surface of the insulating layer 44 while the structure 40/42/44 is rotated relative to the source of the spacer material about an axis generally perpendicular to the upper surface of the layer 44. Precipitates in the insulating layer 44 at an angle significantly less than 90 [deg.]. Although the atoms of the colliding spacer material instantaneously form the aimed beam during the angled rotational precipitation, the angular rotation of the structure 40/42/44 relative to the spacer material source causes the overall deposition to be un aimed. Becomes

When the spacer material precipitation is carried out in a uniform, non-targeted way into the space below the piece 46, the lateral thickness of the annular spacer portion 150B-ie the spacer material 150A is perpendicular to the sphere 46. The radial distance that extends into the area blocked by can be equal to 20% to 80% of the average sphere radius and typically slightly over 50% of the average sphere radius.

Piece 46 is again removed, typically according to the technique utilized in the process of FIG. During removal of the sphere 46, excess gate material portion 120B and excess spacer material portion 150C are simultaneously removed to produce the structure of FIG. 11C. The gap 152 now extends the spacer layer 150A at the location of the removed sphere 46. In particular, the gap 152 extends through the annular spacer portion 150B placed in the gate opening 122. Since the piece 46 is very spherical, the gap 152 is mainly circular. Each gap 152 is concentrated perpendicular to the corresponding gate opening 122.

Using spacer layer 150A as an etch mask, insulating layer 44 is anisotropically etched to form a corresponding non-dielectric opening 154 through layer 44 under lower non-insulating region 42. . Item 44K in FIG. 11D is the remainder of insulating layer 44. Since the gap 152 is concentrated in the gate opening 122, each non-dielectric opening 154 is vertically concentrated in the corresponding gate opening 122.

The electrically non-insulated emitter filament material is electrochemically deposited into the composite openings (or gaps) 152/154 for forming the electron-emitting devices 156 of the precursor filaments that contact the lower non-insulated emitter region 42. do. 11E shows the resulting structure. Once again, electrochemical filament precipitation is typically performed in the manner generally described in US Pat. No. 5,564,959. As such, the emitter filament material is usually a metal such as nickel or platinum.

During electrochemical filament deposition, the combination of the spacer layer 150A and the insulating layer 44 including the spacer portion 150B is used to prevent the precursor electron-emitting filament 156 from contacting the gate layer 120A. Encapsulate (120A) (except as far along the side of the structure as possible). Spacer 150B defines side spacing between gate layer 120A and precursor filament 156.

Electrochemical precipitation is typically done for a time long enough to overfill the synthetic openings 152/154 but not long enough for the electron-emitting filament 156 to meet the other along the top of the spacer layer 158. Thus, each electron-emitting filament 156 has a cap portion 156A that protrudes outside of the composite opening 152/154. Excessive filling reduces the possibility of fabricating considerably different types of electron emitting filaments due to differences in nucleation and growth of the filament material.

The spacer layer 150A, which includes the spacer portion 150B, is removed. See Figure 11f. Spacer material removal is usually done with an etchant that does not significantly penetrate the insulating layer 44K or gate layer 120A. As a result, the outer part of the gate opening 122 is opened again. Wet chemicals, or plasmas with isotropic components, are typically used to perform spacer material etching.

Using the gate layer 120A as an etch mask and through a typically isotropic uncut bottom opening 122 which is a method for forming a corresponding non-dielectric open space 158 around the electron-emitting filament 156. Is etched. See Figure 11G. Item 44L is the remainder of insulating layer 44K. The non-dielectric open space 158 may extend partially or completely through the insulating layer 44L. 11G is fully explained through the case.

The precursor electron-emitting filament 156 provides a portion of the filament that is processed to remove the cap 156A and with a sharpened tip that at least partially extends through the gate opening 122. 11H shows the resulting structure in a sharpened electron emitting filament 156B that is the remainder of filament 156. The sharped filament 156B is typically made from the rolled filament 156 by the above-described sharpening technique to produce a sharped filament in the process series of FIG. 5. Each electron-emitting filament 156B is thus concentrated perpendicularly to the corresponding gate opening 122.

Electro-gloss / sharpening operation can be done after creating the non-dielectric open space 158. The structure of FIG. 11H is produced again. In addition, anisotropic etching may be used to form the open space 158 so that they do not significantly cut under the gate layer 120A. Instead, the formation of open space 158 can be put to sleep. The technique used in the process series of FIG. 9 to automatically terminate the electrochemical precipitation of filament material can be applied to the process of FIG. 11 in the same manner as the filament precipitation automatically terminated in the process series of FIG.

Since (a) the electron-emitting filament 156B is vertically concentrated at the gate opening 122 and (b) the opening 122 is vertically concentrated at the removed sphere 46, the position of the filament 156B is Determined by (46). The side area of the filament 156B is controlled by the diameter of the sphere 46 and the side thickness of the spacer portion 150B. Thus, the filament 156B can provide high uniform electron emission by appropriately adjusting the spherical size, the spherical surface density, and the side thickness of the spacer 150B.

The process / process series of Figs. 5 to 7, 10, and 11 for producing electron emission having the electron-emitting device of the filament all require a spacer material to settle into the gate opening. However, gated electron emitters with electron emitting filaments of average diameter significantly less than the average diameter of the spheres 46 can be made without spacer material that precipitates into the gate. 12A to 12I (collectively “FIG. 12”) provide an example of how a gated field-emitting cathode is made according to the invention.

In the process of FIG. 12, the initial structure 40/42/44 is formed in substantially the same manner as described above for the process of FIG. 2. See FIG. 12A which repeats FIG. 2A. Solid spherical particles 46 are randomly or very randomly distributed past the top of insulating layer 44 according to the technique utilized in the process of FIG. 2. 12B, which repeats FIG. 2B, illustrates the structure at this point.

The bottom (or first) cover material is deposited on top of the structure to form the bottom cover layer 160A over the insulating layer 44 as shown in FIG. 12C. Lower cover layer 160A lies in the space between pieces 44. Precipitation of cover layer 160A is performed in the same manner as the annular portion of cover layer 160A formed in the space below spherical body 46 above layer 44. A portion 160C of the lower cover material accumulates simultaneously in the upper half of the sphere 46.

Precipitation of the bottom cover material is typically performed in substantially the same manner as the spacer material precipitation of FIG. 11. The bottom cover material is typically an electrical insulator. Instead, the bottom cover material can be an electrical non-insulator, typically a metal such as chromium, nickel, molybdenum, titanium, or tungsten. In this case, the portion of the cover layer 160A later forms a portion of the gate layer.

The upper (or second) cover material is in a direction substantially perpendicular to the upper surface of the insulating layer 44 for forming the upper cover layer 162A over the lower cover layer 160A in the space between the spherical particles 46. Settles on top of the structure. Very small (essentially absent) of the top cover material accumulates in space below the spherical body 46 over the bottom cover material portion 160B. However, the portion 162B of the upper cover material accumulates simultaneously in the portion of the lower cover 160B. The overall thickness of cover layer 160A and cover layer 162A is usually less than the average radius of spherical body 46. This avoids connecting excess cover material portion 162B to cover layer 162A.

Top cover layer 162A typically forms at least a portion of the gate layer for the electron emitter. In that case, the top cover material typically consists of an electrically non-insulated gate material that is a metal such as chromium, nickel, molybdenum, titanium, tungsten, or gold. Instead, the top cover material can be an electrical insulator if the bottom cover layer 160A later becomes the gate layer.

Spherical particles 46 are now removed once again, typically according to the techniques used in the process of FIG. 2. The excess cover material portions 160C, 162B in the removed sphere 46 are simultaneously removed to produce the structure of FIG. 12E. The upper opening 164, which typically consists of a gate opening, extends through the upper cover layer 162A at the location of the removed sphere 46. The lower opening 166 similarly extends through the lower cover layer 160A, in particular through the cover portion of layer 160A, at the location of the removed sphere 46. Each lower cover opening 166 is smaller in diameter than the corresponding upper cover opening 164. Since the piece 46 is mainly spherical, the cover opening 164 and the cover opening 166 are mainly circular. Each lower opening 166 is concentrated in a corresponding upper opening 164.

Cover layer 160A and cover layer 162A are used as an etch mask, and insulating layer 44 opens corresponding non-dielectric opening 164 through layer 44 below lower non-insulating emitter region 42. Anisotropically etch through cover opening 164 and cover opening 166 to form. See Figure 12f. Item 44M is the remainder of insulating layer 44. Because each lower cover opening 166 is smaller than the corresponding cover opening 164, the diameter of each non-dielectric opening 168 is approximately equal to the diameter of the corresponding lower cover opening 166. In addition, each non-dielectric opening 168 is concentrated perpendicularly to the corresponding cover opening 164.

The electrically non-insulating emitter filament material is electrochemically deposited into composite openings (or gaps) 166/168 for forming the precursor electron emitting filaments 170 that contact the lower non-insulating emitter region 42. See Figure 12g. The settling time is long enough to completely fill the non-dielectric opening 168 but not so long to fill any of the filaments 170 in contact with the top cover layer 162A. Filament precipitation may be terminated automatically in the manner described above for the process series of FIG. 9. Once again, the filament material is usually a metal such as nickel or platinum.

Using top cover 162A as an etch mask, bottom cover layer 160A is etched through top cover opening 164 to remove annular cover portion 160B. Lower cover opening 166 is thereby widened to become lower cover opening 172 as shown in FIG. 12H. Etching is typically performed in an anisotropic manner such that the widened lower cover opening 172 does not cut under the upper cover layer 162A.

Cover layer 162A and cover layer 160A are used as an etching mask, and insulating layer 44M covers cover opening 164 to form corresponding non-dielectric open space 174 below lower non-insulating area 42. ) And cover opening 166 is anisotropically etched. Again, see Figure 12H. Item 44N is the remainder of insulating layer 44M. The non-dielectric open space 174 may extend partially or completely through the insulating layer 44N, which is shown completely through the case in FIG. 12H.

Electro-gloss / sharpening operation is performed on the rolled filament 170 to provide it with a sharpened tip that partially extends through the bottom cover opening 172. The resulting structure is shown in FIG. 12I. The electron-emitting filament 170A is a sharpened remainder of the rolled filament 170. Electroglossy / sharpening operation is typically done in the manner described above for the process of FIG. 5.

In FIG. 12I, the top cover layer 162A is usually a gate layer. Instead, the top cover layer 162A and the bottom cover layer 160D can be used together as a gate layer. As another alternative, the cover layer 160D may be a gate layer. In this case, the top cover layer 162A is typically made of or removed from an electrically insulating material.

Electro-gloss / sharpening operations may be done before making non-dielectric open space 174. Etching with isotropic components can be used to form open spaces 174 so that they cut under cover layer 160D and cover layer 162D. The formation of open space 174 may be deleted. The filament 170A which has been annealed then abuts the insulating layer 44N.

Regardless of how and when the non-dielectric open space 174 is created and whether the gate layer is formed of one or two of the cover layers 162A, 160D, each electron-emitting filament 170A has a corresponding upper cover opening 164. And is vertically concentrated in the corresponding lower cover opening 172. Since the top cover opening 164 is placed in the position of the removed sphere 46, the position of the filament 170A is determined by the sphere 46. The lateral area occupied by filament 170A is controlled by the diameter of sphere 46 and the lateral area of annular cover material portion 160B. By appropriately adjusting the sphere size, the sphere surface density, and the side thickness of the annular cover portion 160B, it is possible for the electron emitter of FIG. 12i to achieve high uniform electron emission.

In the foregoing process / process series, spherical particles 46 are utilized to directly define the openings used to define the gate openings or directly to define the gate openings. Piece 46 can however be used to first define a solid region having the necessary side shape for the gate opening. This solid region, which is usually circular, is then used to define the gate opening.

13A to 13G (collectively “FIG. 13) are examples of the first half of such a manufacturing process at a gate opening for a gated field-emitting cathode made from a solid region shaped by a spherical particle 46 in accordance with the invention. The gate openings thus made usually have steep edges, so that the first half of the process sequence of Fig. 13 is used to form an electron-emitting device that requires a spacer material to provide the gate openings, as in Figs. 7E to 7J. Particularly suitable for completion according to the later process series, the process series of Figure 13 begins with the structure 41/42/44 of Figure 2a repeated here as in Figure 13a.

An electrically insulated intermediate layer 180 serving as the bottom of the gate layer is deposited over the insulating layer 44 as shown in FIG. 13B. The intermediate non-insulating layer 180 is typically made of metals such as chromium and titanium. The pattern transfer layer 182 is formed on the intermediate layer 180. The pattern transfer layer 182 may be composed of various materials such as photoresist or inorganic dielectric material.

Particles 46 are distributed throughout the top surface of pattern transfer layer 182 using the random technique described above for the treatment of FIG. 1. Fig. 13C shows the structure at this point. A portion of the patterned layer 182 that is shaded by the particles 46, ie not covered vertically, is removed as shown in FIG. 13D. Each pedestal 182A is located below the corresponding one of the particles 46.

When the pattern transfer layer 182 is composed of photoresist, the layer 182 is formed by using a spherical particle 46 as an exposure mask so that a portion of the photoresist under the particle 46 is not chemically radiated. Are exposed to light. Exposed photoresist varies in chemical composition. A developing operation is then performed on the structure to remove the exposed photoresist, resulting in the structure shown in Fig. 13D. When layer 182 is composed of an inorganic dielectric material, particles 46 are used as an etch mask to run in a direction generally perpendicular to the top surface of insulating layer 44 relative to layer 182. The non-blocking portion of layer 182 is removed during etching to get the structure shown in FIG. 13D.

An electrically non-insulating gate material is deposited on top of the structure. Gate material deposition is preferably performed by electrochemical techniques using the non-insulating intermediate layer 180 as the deposition cathode. The deposition anode is located in the deposition electrolyte on the particles 46. During electrochemical deposition, gate material accumulates in the exposed portions of the intermediate layer 180 to form an electrically non-insulating upper gate sublayer 184 as shown in FIG. 13E.

Pedestal 182A and particles 46 are removed to form the structure of FIG. 13F. The upper gate opening 186 extends through the upper gate sublayer 184 at the location of the gathered pedestal 182A under the particle 46. For example, pedestal 182A may be removed with a suitable chemical or plasma etchant, thereby simultaneously removing particles 46. Alternatively, particles 46 may be removed, followed by pedestal 182A.

Using the upper gate sublayer 184 as an etch mask, the non-insulating intermediate layer 180 may pass the upper gate opening 186 to form a corresponding intermediate opening 188 through the intermediate layer 180 to the insulating layer 44. It is anisotropically etched away. See FIG. 13G. Each intermediate opening 188 has the same vertical center and substantially the same diameter as the upper gate opening 186 positioned thereon. Thus, gate sublayers 180A and 184 constitute a composition gate layer in which each pair of corresponding gate openings 186 and 188 form a composition gate opening.

Although the reference numerals are different, but apart from the fact that the gate layer of the structure of FIG. 13G is composed of sublayers 180A and 184, the structure of FIG. 13G is substantially the same as that of FIG. 7D. 180A / 180 and 186/188 in FIG. 13G correspond to 120A and 122 in FIG. 1D, respectively. In accordance with this difference in quotation marks, the structure of FIG. 13G can now be completed according to the spacer based end processing procedure of FIGS. 7E-7J.

Alternatively, using gate layers 180A / 184 as an etch mask, insulating layer 44 opens gate openings to form corresponding insulating open spaces through layer 44 into lower non-insulating regions 42. May be etched through (186/188). Spacer material, which is typically an electrical insulator, may be conformally deposited into the insulating open space on top of the structure to leave a depression similar to the depression 104 of FIG. 5C in the spacer material of the insulating open space. At the bottom of the insulating open space, the spacer material is removed to convert the depression into a hole extending down to the non-insulating area 42, and then a filament electron-emitting device is formed in the hole. By suitably adjusting the size of the spheres, the surface density and the thickness of the spacer material, the resulting electron-emitting device can provide very uniform electron emission.

In each electron emitter having a filament electron-emitting device such as filament 106B, 116B, 130A, 134A, 146A, 156B or 170A, the gate layer, such as gate layer 60B, 120A or 162A, is gated in the above-described process. In the same way that the layers are patterned, they may be patterned with row electrode lines continuous perpendicular to the emitter column electrodes of the lower non-insulating region 42. With proper patterning applied to the gate layer of each field emitter with electron emission filaments, the field emitter is in contact with a portion of the gate layer alternatively, and the column electrode described above for the electron emitter with electron emission cones. It can have independent row electrodes that are perpendicular to it.

The electron emitting devices 106B, 116B, 130A, 134A, 146A, 156B, 170A are filaments having a length to maximum diameter ratio of at least two, usually at least three. The ratio of length to maximum diameter is preferably 5 or more. Some of the filaments 106B, 116B, 130A, 134A, 146A, 156B, 170A below the tip are typically circular cross section cylinders. Nevertheless, the cross section is somewhat non-circular. In some cases, the ratio of maximum diameter to minimum diameter for each filament 106B, 116B, 130A, 134A, 146A, 156B, 170A is usually 2 or less.

Variants and Example Applications

FIG. 14 shows a starting point for manufacturing an implementation of a field emitter in which the lower non-insulating emitter region 42 consists of an electrically conductive layer 42A positioned below the resistive layer 42B. The conductive layer 42A is usually composed of a metal such as nickel or chromium. The resistive layer 42B is usually formed of a conductive alloy slightly doped with polycrystalline silicon or a silicon-carbon-nitrogen compound.

If the conductive layer 42A is patterned with a plurality of parallel emitter column electrodes, the resistive layer 42B can be patterned with the same number of resistance lines positioned over the corresponding column electrode. Alternatively, the resistive layer 42B may be a blanket (continuous) layer even though the conductive layer 42A is patterned in parallel lines.

15A and 15B show how the final structures of FIGS. 2G and 5G are formed, in which the lower non-insulating region 42 is composed of a conductive layer 42A and a resistive layer 42B, respectively. Lower ends of the electron-emitting devices 58A and 106B are in contact with the resistive layer 42B. The resistance between each electron-emitting element and the conductive layer 42A is at least 10 ⁶ Ω, usually 10 ⁸ Ω or more.

Figure 16 shows a typical example of the core active area of a flat panel CRT display using area field emitters made in accordance with the present invention. The substrate 40 forms the back side of the CRT display. The lower non-insulated region 42 is located along the inner surface of the back surface 40 and consists of a conductive layer 42A and a resistive layer 42B positioned thereon. The conductive layer 42A is divided into emitter-electrode lines (column electrodes) extending laterally parallel to the plane of FIG.

The group of row electrodes 190 is, for example, located on the gate layer shown here as gate layer 60B of the field emitter of FIG. 5G, one of which is shown in FIG. 16. The row electrode 190 is continuous perpendicular to the plane of FIG. 16. Row electrode openings 192 extend through the row electrodes 190 to the gate layer, one of which is similar to that shown in FIG. Each row electrode opening 192 exposes a plurality of electron emitting devices, shown herein as electron emitting filaments 106B of the field emitter of FIG. 5G.

A transparent, usually glass front face 194 is opposite the bottom face 40. The light emitting fluorescent region 196 is located on the inner surface of the front surface 194 located directly opposite the corresponding row electrode opening 192, one of which is shown in FIG. 16. An electrically conductive thin light reflecting layer 198, typically made of aluminum, is located above the fluorescent region 196 along the inner surface of the front surface 194. Electrons emitted by the electron emitting device pass through the light reflection layer 198, causing the fluorescent region 196 to emit light that produces an image that can be discerned from the outer surface of the front surface.

The core active area of the flat CRT display typically includes other components not shown in FIG. For example, a black matrix located along the inner surface of the front surface 194 typically surrounds each fluorescent region 196 to laterally separate into other fluorescent regions 196. Matching to the ridge provided on the interelectrode dielectric layer helps to control the electron trajectory. The spacer wall is used to maintain a relatively constant gap between the back face 40 and the front face 194.

When coupled to a flat panel display of the type shown in FIG. 16, a field emitter made in accordance with the present invention operates as follows. The light reflection layer 198 functions as an anode for the field emission cathode. The anode is held at a higher positive voltage than the gate and emitter lines.

a suitable voltage between (a) a selected one of the emitter column electrodes of the lower non-insulated emitter region 42 and (b) a selected one of the row electrodes formed as part of or in contact with the gate layer. When applied, the gate portion thus selected extracts electrons from the electron emitting element at the intersection of the two selected electrodes and controls the magnitude of the generated electron current. Preferred levels of electron emission are such that when the fluorescent region is high voltage fluorescence, the gate-emitter parallel plate electric field applied at a current density of 1 mA / cm 2 as measured at the fluorescence-coated front surface of the flat panel display will be 20 volts / μm or less. Occurs when. When the extracted electrons strike, the fluorescent region emits light.

Terms indicating similar directions, such as "top", "bottom", "bottom", and the like, provide a background for reference in describing the present invention so that the reader may easily understand how the various parts of the present invention fit together. It was used to In practical applications, the components of the electron-emitting device may be located in a direction different from that implied by the terminology used in the present specification. This also applies to the method by which the manufacturing step is carried out in the present invention. Since the terms indicating directions are used for ease of explanation, the present invention also includes implementations other than those in which the directions are exactly covered by the terms indicating directions used herein.

Although the present invention has been described with reference to specific examples, the description is for illustrative purposes only and is not intended to limit the scope of the invention as claimed later. For example, when the spherical particles 46 are made of glass rather than polystyrene, higher processing temperatures may be used during the steps that extend from deposition of particles 46 to removal. The distribution of particles 46 across an inter-electrode dielectric layer, gate layer or base layer can be carried out electrophorically or dielectrically, according to the techniques described in Haven et al. An electropolishing operation may be performed to smooth the edges of the gate layer at the gate opening.

One or more thin interlayers that perform various functions may be provided between the insulating layer 44 and the gate layer. This intermediate layer may provide an adhesion function, that is, the intermediate layer adheres well to both the inter-electrode dielectric 44 and the gate layer when the gate material itself does not adhere well to the inter-electrode dielectric material. The intermediate layer then undergoes a processing step similar to that applied to the gate layer, including forming an intermediate opening corresponding to the gate opening.

A transparent electrically non-insulating layer, located between the front surface 194 and the fluorescent light 196, for example composed of indium-tin oxide, can be used as the anode instead of the light reflection layer 198. The substrate 40 may be removed if the underlying non-insulating region 42 is a continuous layer having a thickness sufficient to support the structure. The insulating substrate 40 may be replaced with a compound substrate on which a thin insulating layer is placed on a relatively thick non-insulating layer having a structural support.

In manufacturing a large area electron emitter with a gate, the substrate 40 may be in the form of a rectangular plate that is cut into one or more rectangular plates after formation of the electron emitting device rather than a circular wafer. The electron-emitting device may have other forms than cones and filaments.

After the gate opening forms a structure extending downward through the gate layer to the insulating layer 44 above the underlying non-insulating emitter region 42, the thickness of the gate layer is more selective to the electrically non-insulating gate material over the gate layer. Can be increased by deposition. Additional gate material deposition can be performed by electrochemical techniques. In general, additional gate material deposition may be performed before or after removing the particles 46.

The deposition termination technique described in connection with FIG. 9 can be used to automatically terminate electrochemical deposition of electron-emitting filaments in a region electron emitter defined by a mechanism where the filament location does not include a sphere 46. For example, the automatic termination technique of FIG. 9 can be applied to openings formed by photolithographic etching techniques or filaments deposited in openings defined by charge particle tracks, as in McCullrey et al., US Pat. No. 5,462,467.

Area electron emitters produced in accordance with the manufacturing process of the present invention can be used to construct flat devices in addition to flat CRT displays. In particular, this electron emitter can be used in a normal vacuum environment requiring an electron source with a gate. Accordingly, various modifications and applications can be made by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims.

Claims (38)

Spraying a plurality of particles onto the structure; Using particles to define corresponding locations for a plurality of gate openings extending through an electrically non-insulating gate layer provided over the electrically insulating layer in the structure; Providing a spacer material in the gate opening to generally cover its side ends, but leave a corresponding gap extending through the spacer material under the insulating layer; Etching the insulating layer through the gap to form a corresponding dielectric opening, usually through the insulating layer, below the lower electrically non-insulating layer provided below the insulating layer; And Injecting an electrically non-insulating emitter material into the dielectric opening to form a corresponding electron-emitting device over the lower non-insulating region. The method of claim 1, Providing the spacer material includes: Depositing a blanket layer of spacer material over the gate layer; And Removing unwanted material of the blanket layer such that the remainder of the blanket layer consists of a plurality of spacer portions each extending a gap in the spacer material. The method of claim 1, Providing the spacer material comprises selectively depositing spacer material into the gate opening. The method of claim 1, And subsequent to the emitter material implantation, etching the insulating layer through the gate opening to form a corresponding dielectric opening space around the electron emitting filament. The method of claim 1, The emitter material implantation step is generally terminated for each dielectric opening when the electron-emitting device formed in the dielectric opening contacts the spacer material located along the side end of the gate opening for the dielectric opening. Way. The method of claim 1, And the spraying step involves spraying the particles directly over one of the insulating layer and the gate layer. The method of claim 1, The spraying step involves spraying particles over the insulating layer, The use step includes providing an electrically non-insulated gate material over an insulating layer in at least the space between the particles; And Removing the particles and any material generally superimposed on the particles to form a gate layer with the gate openings through which the remaining gate material extends. The method of claim 1, The spraying step involves spraying particles across the gate layer, The use step includes providing additional material over the gate layer in at least the space between the particles; Removing the particles and any material that generally overlaps the particles such that the corresponding gap extends through the remaining additional material at the location of the removed particles; And Etching the gate layer through the gap to form a corresponding gate opening through the gate layer. The method of claim 1, The spraying step involves spraying particles over the insulating layer, wherein the using step and providing the spacer material are: Depositing an electrically non-insulated gate material over the insulating layer in the spaces between the particles to form a gate layer with the gate opening at the location of the particles; Providing a spacer material in the gate opening below the particles above the insulating layer; And Removing the particles and generally any material superimposed on the particles. The method of claim 1, Prior to the spraying step, the method includes providing a pattern moving layer over the insulating layer in the structure, wherein the spraying step involves spraying particles over the pattern moving layer, The use step includes the steps of creating a corresponding pedestal from the pattern moving layer by removing material of the pattern moving layer that is not blocked by the particles; Depositing an electrically non-insulated gate material over the insulating layer in at least the space between the pedestals; And Removing the pedestal and usually any material comprising particles, wherein the residual gate material overlaps the pedestal to form a gate layer. Spraying a plurality of particles onto the structure; Using particles to define corresponding locations for a plurality of gate openings extending through an electrically non-insulating gate layer provided over the electrically insulating layer in the structure; Etching the insulating layer through the gate opening to form a corresponding dielectric opening, usually through the insulating layer, below the lower non-insulating layer provided below the insulating layer; Providing a spacer material in the dielectric opening to generally cover its side ends, but to leave a corresponding gap extending through the spacer material under the non-insulated region; And Injecting an electrically non-insulating emitter material into the gap to form a corresponding electron-emitting device over the lower non-insulating region. The method of claim 11, And following the emitter-material implanting step, removing the spacer material along the side ends of the dielectric openings. The method of claim 11, Prior to the spraying step, the method includes providing a pattern moving layer over the insulating layer in the structure, wherein the spraying step involves spraying particles over the pattern moving layer, The use step includes the steps of creating a corresponding pedestal from the pattern moving layer by removing material of the pattern moving layer that is not blocked by the particles; Depositing an electrically non-insulated gate material over the insulating layer in at least the space between the pedestals; And Removing the pedestal and usually any material comprising particles, wherein the residual gate material overlaps the pedestal to form a gate layer. The method according to claim 1 or 11, wherein Said use step comprises providing a first layer formed over the gate layer with a plurality of first openings corresponding to the gate openings such that each gate opening is aligned perpendicular to the corresponding first openings. Way. The method of claim 14, And the spraying step comprises spraying particles over one of the insulating layer, the gate layer, and the first layer. The method of claim 14, The spraying step involves spraying particles over the insulating layer, The use step includes providing an electrically non-insulated gate material over the insulating layer in at least the space between the particles; Providing a first material over the gate layer in at least the space between the particles; And Any material and particles usually superimposed on the particles are formed so that the first layer forms a first layer with the first opening extending therein and the gate material with the gate opening extending therein. And removing the same. The method of claim 14, The spraying step involves spraying particles across the gate layer, The use step includes providing a first material over the gate layer in at least the space between the particles; Removing any material and particles generally superimposed on the particles to form a first layer with the first opening that extends the remaining first material therefrom; And Etching the gate layer through the first opening to form a gate opening. The method of claim 14, The spraying step involves spraying particles over the first layer, The use step includes providing additional material over the first layer in at least the space between the particles; Removing any material and particles that generally overlap the particles such that the gap at the location of the removed particles extends through the remaining additional material; Etching the first layer through the gap to form a first opening; And Etching the gate layer through the first opening to form a gate opening. The method according to any one of claims 1 to 13, The electron-emitting device is characterized in that it is generally formed in the shape of filament. Spraying a plurality of particles onto the structure; The lower cover material covers the space between the particles and generally extends into the space below the particle above the insulating layer to form a lower cover layer with lower openings each corresponding to the particle, each having a lower opening positioned at the position of the corresponding particle. Providing a bottom cover material over; The upper cover material over the lower cover layer in the space between the particles to form an upper cover layer, each corresponding to the particles, each having an upper opening having a diameter larger than the corresponding lower opening and positioned at the corresponding particle's opening; Providing a; Removing any material and particles that generally overlap the particles; Etching the insulating layer through the upper and lower openings to form a corresponding dielectric opening through the insulating layer under the lower electrically non-insulating region provided below the insulating layer; And Injecting an electrically non-insulating emitter material into the dielectric opening to form a corresponding electron-emitting device over the lower non-insulating region. The method of claim 20, At least one of said cover layers comprises an electrically non-insulated gate material forming a gate layer. Spraying a plurality of particles onto the structure; A plurality of first openings extending through a first layer provided over an electrically non-insulating gate layer formed over the electrically insulating layer in the structure and each guiding extending through the gate layer such that the gate openings are aligned perpendicular to the corresponding first openings. Using particles to define corresponding locations for a plurality of corresponding gate openings; Etching the insulating layer through the first opening and the gate opening to form a corresponding dielectric opening through the insulating layer, generally under the lower electrically non-insulating region provided below the insulating layer; Depositing an electrically non-insulating emitter material over the first layer through the first and gate openings and into the dielectric opening to form a corresponding electro-emitting device over the lower non-insulating region; And Removing the first layer to remove any emitter material accumulated over the first layer. The method of claim 22, Wherein said spraying involves depositing particles directly over one of an insulating layer, a gate layer, and a first layer. The method of claim 22, The spraying step involves spraying particles over the insulating layer, The use step includes providing an electrically non-insulated gate material over the insulating layer in at least the space between the particles; Providing a first material over the gate material in at least the space between the particles; And Any material and particles usually superimposed on the particles are formed so that the first layer forms a first layer with the first opening extending therein and the gate material with the gate opening extending therein. And removing the same. The method of claim 22, The spraying step involves spraying particles across the gate layer, The use step includes providing a first material over the gate layer in at least the space between the particles; Removing any material and particles generally superimposed on the particles to form a first layer with the first opening therewith, the remaining first material extending therefrom; And Etching the gate layer through the first opening to form a gate opening. The method of claim 22, The spraying step involves spraying particles over the first layer, The use step includes providing additional material over the first layer in at least the space between the particles; Removing any material and particles generally overlapping the particles such that the additional openings extend through the remaining additional material at the location of the removed particles; Etching the first layer through the additional opening to form a first opening; And Etching the gate layer through the first opening to form a gate opening. Spraying a plurality of particles over the electrically insulating layer; Providing an electrically non-insulated gate material over the insulating layer in at least the space between the particles; Providing a first material over the gate material in at least the space between the particles; A gate layer in which the remaining first material extends at a location of the particles from which the plurality of first openings have been removed, and in which the residual gate material extends at a location where the plurality of gate openings are each aligned perpendicularly to the first opening; Removing any material and particles generally superimposed on the particles to be made of; Etching the insulating layer through the gate opening to form a corresponding dielectric opening generally through the insulating layer underneath the underlying electrically non-insulating region; And Forming a plurality of electron-emitting devices over the lower non-insulated region such that each electron-emitting device is at least partially positioned in a corresponding one of the dielectric openings. Providing a structure in which the electrically non-insulating gate layer lays an electrically insulating layer over the lower electrically non-insulating region; Spraying a plurality of particles over the gate layer; Providing a first material over the gate layer in at least the space between the particles; Removing any material and particles generally overlapping the particles such that the remaining first material consists of a first layer extending at the location of the particles from which the plurality of first openings have been removed; Etching the gate layer through the first opening to form a corresponding gate opening through the gate layer; Etching the insulating layer through the gate opening to form a corresponding dielectric opening generally through the insulating layer; Depositing an electrically non-insulating emitter material over the first layer and into the dielectric opening to form a corresponding electron-emitting device over the lower non-insulating region; And Removing the first layer to generally remove any emitter material accumulated over the first layer. Spraying a plurality of particles over the first layer; Providing additional material over the first layer in at least the space between the particles; Removing any material and particles generally overlapping the particles such that the gap extends through the remaining additional material at the removed particle location; Etching the first layer through the gap to form a corresponding first opening through the first layer below the underlying electrically non-insulated gate layer; Etching the gate layer through the first opening to form a corresponding gate opening through the gate layer underneath the underlying electrically insulating layer; Etching the insulating layer through the gate opening to form a corresponding dielectric opening, usually through the insulating layer underneath the underlying electrically non-insulating region; And Forming a plurality of electron-emitting devices over the lower non-insulated region such that each electron-emitting device is at least partially positioned in a corresponding one of the dielectric openings. The method according to any one of claims 22 to 29, And the first layer is made of an inorganic dielectric material. The method according to any one of claims 22 to 29, And the gate material is made of a metal that is difficult to accurately etch the small openings. The method according to any one of claims 22 to 29, The electron-emitting device is generally characterized in that it is formed in a conical shape. The method according to any one of claims 27 to 29, The electron-emitting device is characterized in that it is generally formed in a filament shape. The method according to any one of claims 1 to 13 and 22 to 29, The particles are large spherical. The method according to any one of claims 1 to 13 and 22 to 29, And the electron-emitting device has substantially the same size. The method according to any one of claims 1 to 13 and 22 to 29, And wherein the electron-emitting device operates in field emission mode. The method according to any one of claims 1 to 13 and 22 to 29, Providing anode means on and away from the electron-emitting device to collect electrons emitted by the electron-emitting device. The method of claim 37, And said anode means are provided as part of a light emitting structure having a light emitting element for emitting light when hit by electrons emitted from the electron emitting element.