JPH0541152A - Manufacture of electric field emission cathode - Google Patents
Manufacture of electric field emission cathodeInfo
- Publication number
- JPH0541152A JPH0541152A JP19768591A JP19768591A JPH0541152A JP H0541152 A JPH0541152 A JP H0541152A JP 19768591 A JP19768591 A JP 19768591A JP 19768591 A JP19768591 A JP 19768591A JP H0541152 A JPH0541152 A JP H0541152A
- Authority
- JP
- Japan
- Prior art keywords
- field emission
- emission cathode
- substrate
- etching
- electric field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明はマイクロ真空デバイス
における電界放出陰極の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field emission cathode in a micro vacuum device.
【０００２】[0002]
【従来の技術】微小な電界放出陰極を利用し、超高速の
真空ＩＣや、高精細のフラットパネルＣＲＴを形成しよ
うという試みが始まっている。これらの真空デバイス
は、半導体の微細加工技術を用いて形成され、素子の高
機能化と高集積化を目指すものである。2. Description of the Related Art Attempts have been made to form ultra-high-speed vacuum ICs and high-definition flat panel CRTs by using minute field emission cathodes. These vacuum devices are formed by using a fine processing technology for semiconductors, and aim at high functionality and high integration of elements.
【０００３】電界放出陰極はマイクロ真空デバイスの主
要構成要素であり、その形状から錐型と楔型の２種類に
分けることができる。錐型の電界放出陰極は基板と垂直
の方向に電子を放出し、楔型は水平方向に放出する。錐
型の電界放出陰極はその形成方法で、蒸着型とエッチン
グ型の２種類に分けることができる。蒸着型は陰極を金
属の蒸着により形成され、エッチング型はシリコンの異
方性エッチングにより形成される。楔型は金属の蒸着と
そのエッチングによって形成される。A field emission cathode is a main constituent element of a micro vacuum device, and can be classified into two types, a cone type and a wedge type, depending on its shape. The cone-shaped field emission cathode emits electrons in a direction perpendicular to the substrate, and the wedge-shaped field emission cathode emits electrons in a horizontal direction. The conical field emission cathode can be divided into two types, a vapor deposition type and an etching type, depending on the forming method. The vapor deposition type is formed by depositing a metal on the cathode, and the etching type is formed by anisotropic etching of silicon. The wedge shape is formed by vapor deposition of metal and its etching.
【０００４】これらの電界放出陰極を適用したデバイス
として、フラットパネルＣＲＴがある。フラットパネル
ＣＲＴは電界放出陰極の高集積度を最大限に利用しよう
とするものである。A flat panel CRT is a device to which these field emission cathodes are applied. Flat panel CRTs seek to maximize the high integration of field emission cathodes.
【０００５】次に錐型電界放出陰極の形状およびその形
成方法について説明する。図６に錐型の陰極の構造図を
示す。図において、５１は基板、５２はゲート膜、５３
は絶縁膜、５４は電界放出陰極である。Next, the shape of the conical field emission cathode and the method for forming the same will be described. FIG. 6 shows the structure of a conical cathode. In the figure, 51 is a substrate, 52 is a gate film, and 53.
Is an insulating film and 54 is a field emission cathode.
【０００６】Ｓｉ基板５１上に円錐状あるいは角錐状の
電界放出陰極５４が形成されている。ゲート膜５２はＳ
ｉＯ2 の絶縁膜５３上に形成されている。電界放出陰極
（エミッタコーン）とアノード（図示しない）間に電圧
をかけ、かつ、エミッタとゲート間に電圧を印加するこ
とにより、エミッタ先端から電子が引き出される。先端
の曲率半径は数百Åである。A conical or pyramidal field emission cathode 54 is formed on a Si substrate 51. The gate film 52 is S
It is formed on the insulating film 53 of iO 2 . Electrons are extracted from the tip of the emitter by applying a voltage between the field emission cathode (emitter cone) and the anode (not shown) and applying a voltage between the emitter and the gate. The radius of curvature of the tip is several hundred Å.
【０００７】蒸着型、エッチング型の形成方法をそれぞ
れ図７、図８に示す。図７に示すのが蒸着型である。図
において、６１はＳｉウェハー基板、６２はＳｉＯ2 絶
縁膜、６３はＭｏ膜、６４はＡｌ犠牲層、６５はＭｏ蒸
着膜、６６は電界放出陰極である。The vapor deposition type and etching type forming methods are shown in FIGS. 7 and 8, respectively. FIG. 7 shows a vapor deposition type. In the figure, 61 is a Si wafer substrate, 62 is a SiO 2 insulating film, 63 is a Mo film, 64 is an Al sacrificial layer, 65 is a Mo vapor deposition film, and 66 is a field emission cathode.
【０００８】次に上述した蒸着型の製造工程について説
明する。表面ドープを施し導電性を良くしたＳｉウェハ
ー基板６１上に、ＳｉＯ2 絶縁膜６２を１〜１．５μｍ
成膜し、Ｍｏ膜６３を電子ビーム蒸着する。この上から
直径１μｍの円状にＭｏ膜６３とＳｉＯ2 絶縁膜６２を
エッチングで抜く。次にフッ酸でＳｉＯ2 絶縁膜６２を
やや溶かしだし、その後Ａｌ犠牲層６４を斜め方向から
蒸着する（図７Ａ）。次にＭｏ膜６３を上方より真空蒸
着する。Ｍｏ膜６３はＡｌ−Ｍｏ−ＳｉＯ2 の穴を通し
てＳｉウェハー基板６１上に堆積するが、Ｍｏ膜６３の
穴の縁にも堆積するため、次第に穴の径が小さくなり、
最終的には穴は閉じてしまう。そのためＭｏ膜６３はコ
ーン状になってＳｉウェハー基板６１上に堆積する（図
７Ｂ）。最後にＡｌ犠牲層６４を溶解除去する（図７
Ｃ）。Next, the manufacturing process of the above-mentioned vapor deposition type will be described. A SiO 2 insulating film 62 of 1 to 1.5 μm is formed on a Si wafer substrate 61 that has been surface-doped to improve conductivity.
The Mo film 63 is formed by electron beam evaporation. From above, the Mo film 63 and the SiO 2 insulating film 62 are removed by etching into a circular shape having a diameter of 1 μm. Next, the SiO 2 insulating film 62 is slightly melted with hydrofluoric acid, and then the Al sacrifice layer 64 is obliquely deposited (FIG. 7A). Next, the Mo film 63 is vacuum-deposited from above. The Mo film 63 is deposited on the Si wafer substrate 61 through the Al-Mo-SiO 2 hole, but since it is also deposited on the edge of the Mo film 63, the diameter of the hole is gradually reduced,
Eventually the hole closes. Therefore, the Mo film 63 has a cone shape and is deposited on the Si wafer substrate 61 (FIG. 7B). Finally, the Al sacrificial layer 64 is dissolved and removed (FIG. 7).
C).
【０００９】図８に示すのがエッチング型である。図に
おいて、７１はＳｉウェハー基板、７２はエッチングマ
スク、７３は絶縁膜、７４はゲート電極、７５は電界放
出陰極である。The etching type is shown in FIG. In the figure, 71 is a Si wafer substrate, 72 is an etching mask, 73 is an insulating film, 74 is a gate electrode, and 75 is a field emission cathode.
【００１０】次にエッチング型の製造工程について説明
する。導電性を上げるため、予めSiウェハー基板７１の
面にリンをドープし、Ｎ型Ｓｉウェハーにしておく。そ
の上に、Ｓi3Ｎ4 やＳｉＯ2 のエッチングマスク７２を
所望の大きさ（１〜２μの円形）に形成する（図８
Ａ）。次にＫＯＨなどの溶液でＳｉウェハー基板７１を
異方性エッチングするとＳｉウェハーはピラミッド状に
加工される。このピラミッドの先端曲率半径は１０００
Å以下である（図８Ｂ）。そして陰極７５の周囲にＳｉ
Ｏ2 の絶縁膜７３（１〜２μｍ、ＣＶＤ）とＷ，Ｍｏ，
Ｔａなどのゲート用の電極７４（0.５μｍ、ＥＢ蒸着）
を成膜する（図８Ｃ）。Next, an etching type manufacturing process will be described. In order to increase the conductivity, the surface of the Si wafer substrate 71 is previously doped with phosphorus to form an N-type Si wafer. On top of that, an etching mask 72 of Si 3 N 4 or SiO 2 is formed in a desired size (circle of 1 to 2 μ) (FIG. 8).
A). Next, when the Si wafer substrate 71 is anisotropically etched with a solution such as KOH, the Si wafer is processed into a pyramid shape. The radius of curvature of the tip of this pyramid is 1000
Å or less (Fig. 8B). And Si around the cathode 75
O 2 insulating film 73 (1-2 μm, CVD) and W, Mo,
Gate electrode 74 such as Ta (0.5 μm, EB vapor deposition)
Is formed (FIG. 8C).
【００１１】[0011]
【発明が解決しようとする課題】蒸着型は電界放出陰極
が金属でできているため高い電流密度が期待できるとい
う長所があるが、ミクロンオーダーの小さい開口部を通
して金属を蒸着するので、開口部の径により電界放出陰
極の径と高さが異なり、その制御が困難という問題点が
ある。一方、エッチング型はＳｉウェハーの異方性エッ
チングを利用して電界放出陰極を形成するので、形状の
制御が比較的容易であるが、電流密度が小さいことや不
規則な電流−電圧特性が問題点となる。The vapor deposition type has an advantage that a high current density can be expected because the field emission cathode is made of metal, but since the metal is vapor-deposited through a small opening of micron order, the opening portion of The diameter and height of the field emission cathode differ depending on the diameter, and there is a problem that its control is difficult. On the other hand, the etching type is relatively easy to control the shape because the field emission cathode is formed by using anisotropic etching of a Si wafer, but the current density is small and the irregular current-voltage characteristic is a problem. It becomes a point.
【００１２】この発明は上記のような問題点を解消する
ためになされたもので、金属でできた電界放出陰極を用
いることで高い電流密度を得、かつ錐型の形状を得るた
めに比較的容易な形状制御方法により形成することによ
り、性能、信頼性が高く、製造コストの安い電界放出陰
極の製造方法を得ることを目的とする。The present invention has been made in order to solve the above problems, and it is relatively possible to obtain a high current density and a pyramidal shape by using a field emission cathode made of metal. It is an object of the present invention to obtain a method for manufacturing a field emission cathode having high performance and reliability and low manufacturing cost by forming by a simple shape control method.
【００１３】[0013]
【課題を解決するための手段】この発明に係る電界放出
陰極の製造方法は、錐型の電界放出電極を持つマイクロ
真空デバイスにおいて、基板に錐型の凹みを形成し、こ
の凹みの上に電極材料を形成し、その後基板を除去する
ことにより錐型の電界放出電極を得るものである。According to the method of manufacturing a field emission cathode according to the present invention, in a micro vacuum device having a conical field emission electrode, a conical recess is formed on a substrate and an electrode is formed on the concavity. By forming a material and then removing the substrate, a conical field emission electrode is obtained.
【００１４】[0014]
【作用】この発明は、錐型の電界放出電極を持つマイク
ロ真空デバイスにおいて、基板に錐型の凹みを形成し、
その上に電界放出陰極の電極材料を形成し、その後基板
を除去することによって、電界放出電極の材料に金属を
用いることができ、高い電流密度を得ることができる。
またエッチングにより基板上に錐型の凹みを作るため、
形状の制御が比較的容易となる。そのため、性能、信頼
性が高く、製造コストの安い電界放出陰極を得ることが
できる。According to the present invention, in a micro vacuum device having a conical field emission electrode, a conical recess is formed on a substrate,
By forming the electrode material of the field emission cathode on it and then removing the substrate, a metal can be used as the material of the field emission electrode and a high current density can be obtained.
Also, because a conical recess is made on the substrate by etching,
Shape control becomes relatively easy. Therefore, a field emission cathode having high performance and reliability and low manufacturing cost can be obtained.
【００１５】[0015]
【実施例】以下、この発明による実施例を図について説
明する。図１はこの発明の製造方法の工程図を示す断面
図である。図において、１１はＳｉ基板、１２は基板エ
ッチング用のマスク材である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a process chart of the manufacturing method of the present invention. In the figure, 11 is a Si substrate, and 12 is a mask material for etching the substrate.
【００１６】この実施例の製造方法は、Ｓｉ基板１1(0.
５mm厚程度、結晶方位）上にエッチングマスク材１２と
してＳｉＯ2 膜を３０００Åスパッタ形成する（図１
Ａ）。このＳｉＯ2 膜は熱酸化膜あるいはＳi3Ｎ4 膜等
でもよい。その上に写真製版を施し、Ｓｉ基板１１に錐
型の凹みを設ける部分以外をレジストで覆う。次にフッ
化水素酸、フッ化アンモニウム水溶液を用いてＳｉＯ2
マスクを溶解除去する（図１Ｂ）。さらにＫＯＨ水溶液
に基板を浸漬し、異方性エッチングにより角錐状の凹み
１１ａをＳｉ基板１１表面に形成する（図１Ｃ）。マス
クであるＳｉＯ2 膜をフッ酸等でエッチング除去し、Ｓ
ｉ基板に角錐状の凹み１１ａが形成できる（図１Ｄ）。In the manufacturing method of this embodiment, the Si substrate 11 (0.
A SiO 2 film of 3000 Å is formed as an etching mask material 12 on a crystal orientation of about 5 mm (FIG. 1).
A). This SiO 2 film may be a thermal oxide film or a Si 3 N 4 film. Photolithography is performed thereon, and the Si substrate 11 is covered with a resist except the portion where the conical recess is provided. Next, using hydrofluoric acid and an ammonium fluoride aqueous solution, SiO 2
The mask is dissolved and removed (FIG. 1B). Further, the substrate is dipped in a KOH aqueous solution and anisotropically etched to form pyramidal depressions 11a on the surface of the Si substrate 11 (FIG. 1C). The SiO 2 film that is the mask is removed by etching with hydrofluoric acid or the like,
A pyramidal depression 11a can be formed on the i substrate (FIG. 1D).
【００１７】Ｓｉエッチング液には、フッ酸硝酸系以外
にアルカリエッチ液があり、苛性カリあるいは有機アル
カリ水溶液を加熱すれば、かなりのエッチング速度に達
する。そしてこの種のエッチング液は結晶方位依存性が
大きく、図２に示すように（１００）方向のエッチング
速度は早く、これに反して（１１１）方向のエッチング
速度は最も遅い。As the Si etching liquid, there are alkaline etching liquids other than the hydrofluoric acid / nitric acid type, and when a caustic potash or an organic alkaline aqueous solution is heated, a considerable etching rate is reached. This type of etching solution has a large crystal orientation dependency, and as shown in FIG. 2, the etching rate in the (100) direction is fast, whereas the etching rate in the (111) direction is the slowest.
【００１８】そこで（１００）面のウェハーを用い、パ
ターンの線を（１１１）方向にすれば、この線を含む
（１１１）面が現れる。そしてこの方向にはエッチング
がほとんど進行しないので、エッチング形状は図２に示
したようになる。If a (100) plane wafer is used and the pattern line is oriented in the (111) direction, the (111) plane containing this line appears. Since etching hardly progresses in this direction, the etching shape is as shown in FIG.
【００１９】以下この発明による他の実施例を図につい
て説明する。図３は本発明の製造方法の工程図を示す断
面図である。図において、２１はＳｉ基板、２２は基板
エッチング用のマスク材であるフォトレジストである。Another embodiment according to the present invention will be described below with reference to the drawings. FIG. 3 is a cross-sectional view showing a process drawing of the manufacturing method of the present invention. In the figure, 21 is a Si substrate, and 22 is a photoresist which is a mask material for etching the substrate.
【００２０】この実施例の製造方法は、Ｓｉ基板２１
（0.５mm厚程度）上にフォトレジスト２２を塗布する
（図３Ａ）。次に、写真製版を施し、Ｓｉ基板２１に錐
型の凹みを設ける部分のレジストを除去する（図３
Ｂ）。次にＳｉ基板２１をイオンビームエッチング（Ｉ
ＢＥ）装置内に載置する。ＩＢＥ層によりアルゴンのイ
オンビームを照射して、円錐状の凹み２１ａをＳｉ基板
表面に形成する（図３Ｃ）。最後にアッシャー等を用い
てフォトレジスト２２を除去する（図３Ｄ）。In the manufacturing method of this embodiment, the Si substrate 21
A photoresist 22 is applied on (about 0.5 mm thickness) (FIG. 3A). Next, photoengraving is performed to remove the resist in the portion where the conical recess is formed in the Si substrate 21 (FIG. 3).
B). Next, the Si substrate 21 is subjected to ion beam etching (I
BE) Place in the device. The IBE layer is irradiated with an argon ion beam to form a conical depression 21a on the surface of the Si substrate (FIG. 3C). Finally, the photoresist 22 is removed using an asher or the like (FIG. 3D).
【００２１】このときＳｉ基板２１は、アルゴンのイオ
ンビームによってエッチングされるが、イオンビームの
直進性がよいため異方性が良くエッチングされる。この
ときイオンビームの方向に対して基板２１を傾けると、
イオンビームの影になる部分ができ、斜めにエッチング
することができる。At this time, the Si substrate 21 is etched by an ion beam of argon, but since the ion beam has a good linearity, it has good anisotropy. At this time, if the substrate 21 is tilted with respect to the direction of the ion beam,
There is a shadow of the ion beam, which can be etched diagonally.
【００２２】上記２つの実施例についてウェットエッチ
ングあるいはＩＢＥによるエッチングによりＳｉ表面に
形成する凹みは、それぞれ角錐状、円錐状となる。この
形状の違いはエッチングの方法によって変わるので、電
界放出陰極を用いるデバイスの目的仕様によって選べば
よい。The recesses formed on the Si surface by wet etching or IBE etching in the above two embodiments have a pyramid shape and a cone shape, respectively. Since this difference in shape varies depending on the etching method, it may be selected according to the target specifications of the device using the field emission cathode.
【００２３】以下この発明による電界放出陰極の製造方
法を図４について説明する。図において、３１はＳｉ基
板、３２は電界放出陰極材料、３３は接着剤層、３４は
電界放出陰極支持基板である。A method of manufacturing a field emission cathode according to the present invention will be described below with reference to FIG. In the figure, 31 is a Si substrate, 32 is a field emission cathode material, 33 is an adhesive layer, and 34 is a field emission cathode support substrate.
【００２４】上述した電界放出陰極の製造方法について
説明する。表面に錐型の凹み３１ａをもったＳｉ基板３
１（図４Ａ）をスパッタ装置内に載置し、その表面にタ
ングステン（Ｗ）の電界放出陰極材料３２を２ミクロン
の厚さにスパッタ形成する（図４Ｂ）。さらにその上に
電界放出陰極の支持基板としてガラスなどの基板３４を
接着剤層３３あるいは陽極接合法などによって接合する
（図４Ｃ）。接合の終わったＳｉ基板３１をＫＯＨ水溶
液の中に浸漬し、Ｓｉ基板を溶解除去することで電界放
出陰極３５ができる（図４Ｄ）。A method of manufacturing the above-mentioned field emission cathode will be described. Si substrate 3 having a conical recess 31a on the surface
1 (FIG. 4A) is placed in a sputtering apparatus, and a field emission cathode material 32 of tungsten (W) is formed on the surface thereof by sputtering to a thickness of 2 μm (FIG. 4B). Further, a substrate 34 such as glass as a supporting substrate for the field emission cathode is bonded thereon by an adhesive layer 33 or an anodic bonding method (FIG. 4C). The Si substrate 31 after the joining is immersed in a KOH aqueous solution, and the Si substrate is dissolved and removed to form the field emission cathode 35 (FIG. 4D).
【００２５】次にこの発明によるその他の実施例を図に
ついて説明する。図５はこの発明の製造方法の工程図を
示す断面図である。図において、４１はＳｉ基板、４２
は電界放出陰極表面材料、４３は電界放出陰極材料、４
４は接着剤層、４５は電界放出陰極支持基板である。Next, another embodiment according to the present invention will be described with reference to the drawings. FIG. 5 is a sectional view showing a process drawing of the manufacturing method of the present invention. In the figure, 41 is a Si substrate, 42
Is a field emission cathode surface material, 43 is a field emission cathode material, 4
4 is an adhesive layer, and 45 is a field emission cathode supporting substrate.
【００２６】上述した製造方法では、表面に錐型の凹み
４１ａをもったＳｉ基板４１（0.５mm厚）（図５Ａ）を
スパッタ装置内に載置し、その表面にタングステン
（Ｗ）の電界放出陰極表面材料４２を２０００Åの厚さ
にスパッタ形成する。その上にメッキによりニッケルの
電界放出陰極材料４３を２ミクロンの厚さに形成する
（図５Ｂ）。電界放出陰極の支持基板としてガラスなど
の基板４５を接着剤層４４あるいは陽極接合法などによ
って接合する（図５Ｃ）。接合の終わった基板をＫＯＨ
水溶液の中に浸漬し、Ｓｉ基板を溶解除去することで電
界放出陰極４６ができる（図５Ｄ）。In the manufacturing method described above, the Si substrate 41 (0.5 mm thick) (FIG. 5A) having the conical recess 41a on the surface is placed in the sputtering apparatus, and the electric field of tungsten (W) is applied to the surface. The emission cathode surface material 42 is sputtered to a thickness of 2000Å. A nickel field emission cathode material 43 having a thickness of 2 μm is formed thereon by plating (FIG. 5B). A substrate 45 made of glass or the like as a support substrate for the field emission cathode is bonded by the adhesive layer 44 or the anodic bonding method (FIG. 5C). KOH the bonded substrate
The field emission cathode 46 is formed by immersing in the aqueous solution and removing the Si substrate by dissolution (FIG. 5D).
【００２７】[0027]
【発明の効果】この発明は、錐型の電界放出電極を持つ
マイクロ真空デバイスにおいて、基板に錐型の凹みを形
成し、その上に電界放出陰極の電極材料を形成し、その
後基板を除去することによって、電界放出電極の材料に
金属を用いることができ、高い電流密度を得ることがで
きる。またエッチングにより基板上に錐型の凹みを作る
ため、形状の制御が比較的容易となる。そのため、性
能、信頼性が高く、製造コストの安い電界放出陰極を得
ることができる。According to the present invention, in a micro vacuum device having a cone-shaped field emission electrode, a cone-shaped recess is formed on a substrate, an electrode material for a field emission cathode is formed thereon, and then the substrate is removed. As a result, a metal can be used as the material of the field emission electrode, and a high current density can be obtained. Further, since the conical recess is formed on the substrate by etching, the shape can be controlled relatively easily. Therefore, a field emission cathode having high performance and reliability and low manufacturing cost can be obtained.
【図１】この発明の一実施例による電界放出陰極の製造
方法の工程図を示す断面図である。FIG. 1 is a cross-sectional view showing a step in a method for manufacturing a field emission cathode according to an embodiment of the present invention.
【図２】この発明の一実施例を示すエッチングにより現
れる結晶面の方向を示す説明図である。FIG. 2 is an explanatory view showing directions of crystal planes which appear by etching showing an embodiment of the present invention.
【図３】この発明の他の実施例による電界放出陰極の製
造方法の工程図を示す断面図である。FIG. 3 is a cross-sectional view showing a step in a method of manufacturing a field emission cathode according to another embodiment of the present invention.
【図４】この発明の別の実施例による電界放出陰極の製
造方法の工程図を示す断面図である。FIG. 4 is a cross-sectional view showing a step in a method of manufacturing a field emission cathode according to another embodiment of the present invention.
【図５】この発明のさらに別の実施例による電界放出陰
極の製造方法の工程図を示す断面図である。FIG. 5 is a cross-sectional view showing a step in a method of manufacturing a field emission cathode according to still another embodiment of the present invention.
【図６】従来の電界放出陰極の構成図である。FIG. 6 is a configuration diagram of a conventional field emission cathode.
【図７】従来の電界放出陰極の製造方法を示す工程図の
断面図である。FIG. 7 is a cross-sectional view of a step diagram showing a conventional method for manufacturing a field emission cathode.
【図８】従来の電界放出陰極の他の製造方法を示す工程
図の断面図である。FIG. 8 is a cross-sectional view of a process showing another method for manufacturing a conventional field emission cathode.
１１ Ｓｉ基板 １２ マスク材 ２１ Ｓｉ基板 ２２ マスク材 ３１ Ｓｉ基板 ３１ａ 凹み ３２ 電界放出陰極材料 ３３ 接着剤層 ３４ 電界放出陰極支持基板 ３５ 電界放出陰極 ４１ Ｓｉ基板 ４１ａ 凹み ４２ 電界放出陰極表面材料 ４３ 電界放出陰極材料 ４４ 接着剤層 ４５ 電界放出陰極支持基板 ４６ 電界放出陰極 11 Si Substrate 12 Mask Material 21 Si Substrate 22 Mask Material 31 Si Substrate 31a Recess 32 Field Emission Cathode Material 33 Adhesive Layer 34 Field Emission Cathode Support Substrate 35 Field Emission Cathode 41 Si Substrate 41a Recess 42 Field Emission Cathode Surface Material 43 Field Emission Cathode material 44 Adhesive layer 45 Field emission cathode support substrate 46 Field emission cathode
Claims (1)
デバイスにおいて、基板に錐型の凹みを形成し、この凹
みの上に電極材料を形成し、その後基板を除去すること
によって錐型の電界放出電極を得ることを特徴とする電
界放出陰極の製造方法。1. In a micro-vacuum device having a cone-shaped field emission electrode, a cone-shaped electric field is formed by forming a cone-shaped recess on a substrate, forming an electrode material on the recess, and then removing the substrate. A method for manufacturing a field emission cathode, characterized in that an emission electrode is obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19768591A JPH0541152A (en) | 1991-08-07 | 1991-08-07 | Manufacture of electric field emission cathode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19768591A JPH0541152A (en) | 1991-08-07 | 1991-08-07 | Manufacture of electric field emission cathode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0541152A true JPH0541152A (en) | 1993-02-19 |
Family
ID=16378647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19768591A Pending JPH0541152A (en) | 1991-08-07 | 1991-08-07 | Manufacture of electric field emission cathode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0541152A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5509843A (en) * | 1993-05-19 | 1996-04-23 | Kabushiki Kaisha Toshiba | Method and apparatus for manufacturing needle shaped materials and method for manufacturing a microemitter |
| US5679960A (en) * | 1994-01-28 | 1997-10-21 | Kabushiki Kaisha Toshiba | Compact display device |
| US5903092A (en) * | 1994-05-18 | 1999-05-11 | Kabushiki Kaisha Toshiba | Device for emitting electrons |
-
1991
- 1991-08-07 JP JP19768591A patent/JPH0541152A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5509843A (en) * | 1993-05-19 | 1996-04-23 | Kabushiki Kaisha Toshiba | Method and apparatus for manufacturing needle shaped materials and method for manufacturing a microemitter |
| US5679960A (en) * | 1994-01-28 | 1997-10-21 | Kabushiki Kaisha Toshiba | Compact display device |
| US5903092A (en) * | 1994-05-18 | 1999-05-11 | Kabushiki Kaisha Toshiba | Device for emitting electrons |
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