JPH11188153A - Image display device for game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To program various display images without considering the loads of an arithmetic unit. SOLUTION: Image processings such as the rotation and reduction, etc., of images read from a CG memory 21 are performed by using a display working engine 25. An image changeover limiting circuit 30 continuously outputs changeover inhibition signals for stopping the output of switching signals to switches 32a and 32b for switching frame buffers 32c and 32d until the display working engine 25 ends the processing of the image of highest priority. At the rising timing of next vertical synchronizing signals after the processing is ended and the changeover inhibition signals are switched to H, the switches 32a and 32b are switched. Thus, even at the time of displaying the images for taking time for the processing, the disturbance of the images is eliminated, the degree of freedom of the program of the images is raised and complicated images can be displayed as well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and more particularly to an image display device suitable for use in displaying a game machine such as a pachinko machine or a game machine.

[0002]

2. Description of the Related Art In recent years, gaming machines such as pachinko machines which use a liquid crystal display device or a CRT display device in a so-called accessory portion arranged at the center of a pachinko machine in order to improve game characteristics have become mainstream. ing. Competition among companies is how to change the image displayed on the liquid crystal display device or the CRT display device to make the game more interesting. Therefore, in recent gaming machines, it is required to increase the number of images to be displayed on a liquid crystal display device or a CRT display device and to realize movement of images (characters) in finer units.

Conventionally, in game machines and the like, in order to move a character in finer units, an image of each character is decomposed into 8 × 8 dot units or 16 × 16 dot units and stored in a CG memory. Have been used in accordance with the display priority, and written out on a display memory or directly output to a display device.

Further, in order to enhance the game characteristics, a program which requires a high processing speed, such as creating a polygon for performing a three-dimensional display of an image and pasting the image to each surface, is often incorporated. I have.

[0005]

However, a liquid crystal display device or a CRT display device mounted on a pachinko machine normally rewrites a screen every 1/60 second, so that the display image generating circuit can process one screen. Has to be completed within 1/60 second. However, in practice, the load on the arithmetic unit in the display image generation circuit differs depending on the content of the processing, and if all of them are to be kept within 1/60 second, the diversity of the display image programming must be sacrificed. There was a problem that said no. That is, in actual drawing, several images (defined as windows) are overwritten to form one image, but the time required for drawing each window depends on the complexity and size of the image and the like. Because of this difference, the number of windows that can be processed may be reduced within 1/60 second when display processing is performed on an image that includes a window that takes a long time to process.
When the number of images (windows) to be superimposed is reduced, the expression of the displayed image is limited.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image display device for a game machine which can program various display images without concern for a load on an arithmetic unit in a display image generation circuit.

[0007]

In order to achieve the above object, an image display device of a gaming machine according to the present invention comprises: an image processing means for generating a display image; and first and second frames for storing image signals. A buffer, a display device for displaying an image in frame units, first switch means connected to the first and second frame buffers and the display device, and selectively connecting one of the frame buffers to the display device; A first switch means connected to the second frame buffer and the image processing means for selectively connecting one of the frame buffers to the image processing means; a first switch means for the first and second switch means; A switching signal supply means for supplying a complementary switching signal which causes one of the second frame buffers to read when the other frame buffer is rewritten; First and provided with a switching prohibiting means for supplying to the second switch means.

In order to achieve the above object, an image display apparatus for a gaming machine according to the present invention stores a main CPU for instructing a change of a display image based on winning information, and stores various unit images based on an instruction from the main CPU. An image generation unit that reads a unit image from a CG memory to generate and output a display image, first and second frame buffers that store the display image, and switches the display image for each frame to generate first and second images. A write switch for supplying the frame buffer, a read switch for switching and outputting a display image from the first and second frame buffers for each frame, and a first and a second switch connected to the read switch;
A display means for displaying a display image supplied from the frame buffer of the image generation unit, and a switching prohibition means for prohibiting the switching between the write changeover switch means and the readout changeover switch means until the rewriting of one frame of image in the image generation unit is completed. Prepare.

The display means repeatedly reproduces the image of the same frame when the switching is prohibited by the switching prohibiting means, so that the image is not disturbed. In order to achieve the above object, an image display device for a gaming machine according to the present invention comprises a main CPU for instructing a change of a display image based on winning information.
An image generation unit that reads a unit image from a CG memory that stores various unit images based on an instruction from the main CPU, generates and outputs a display image, first and second frame buffers that store the display image, A write switch switch for alternately switching the display image at each predetermined timing and supplying it to one of the first and second frame buffers; and alternately switching the display image from the first and second frame buffers at a predetermined timing. A read-out switch for outputting, a display connected to the read-out switch for displaying a display image supplied from the first and second frame buffers, and a switching timing of the write-in switch and the read-out switch. The timing register to be set, and the switching of the write switch switch and the read switch switch It comprises switching inhibiting means for inhibiting the up period set in the timing register.

Here, there is provided a table storing a plurality of switching timings of the write switch switch and the read switch switch, and the switch prohibiting unit reads the corresponding switch timing from the table based on the value set in the timing register. It is desirable to prohibit switching until the readout period.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a configuration of an image display device according to an embodiment of the present invention. FIG. 2 is a front view of the pachinko machine to which the image display device of FIG. 1 is attached. FIG.
, The pachinko machine is provided with an outer frame 1 for installation on an island of a pachinko parlor, a front frame 2 is attached to the front of the outer frame 1 so as to be openable and closable, and a metal frame 3 is fixed to an inner peripheral edge of the front frame 2. A glass frame 4 is mounted in the metal frame 3 so as to be openable and closable by a hinge (not shown).
The upper plate set 6 is attached to the lower edge of the glass frame 4.

A handle grip 8 and a lower plate set 9 of a hitting ball firing device are assembled to the lower edge of the front frame 2, and a game board 40 is mounted inside the front frame 2 so as to face the glass 5. You. An image display device 50 having a liquid crystal color panel or a CRT is attached to the center of the game board 40, and a band 41, a game nail 42, a lamp windmill 43, and a windmill are provided at a portion of the game board 40 located around the image display device 50. 44, starting winning opening 45, 46, winning opening 47, opening and closing body 4
A variable winning ball device (attacker) 49 having an 8 and an out port 60 are provided. Therefore, in this pachinko machine, when a game ball (not shown) is placed in the upper plate set 6 and the handle grip 8 is rotated in one direction, the firing device (not shown) causes the ball to be transferred from the upper plate set 6 to the band 41 one by one. Fire in. The fired game ball is guided along the band 41 above the game area in the band 41, and the upward thrust of the game ball becomes smaller than the gravity of the game ball, so that the game ball moves down the game area. The game nail 42, the ramp windmill 43, or the windmill 4
4 or the like, and enters the starting winning openings 45 and 46 to move the image display device 50 to a starting ball.
Or a constant supply ball for supplying a constant number of game balls to the upper plate set 6 and supplying them as balls, or starting winning holes 45 and 46
A game ball that does not enter the winning opening or 47 enters the out opening 60 and becomes an out ball. Also, when the image display device 50 displays the big hit by the combination of the stop symbols after the variable display operation, the opening and closing plate 48 of the variable winning ball device 49 opens and closes, and the hit ball against the game ball hit into the game area is opened. Probability increases. The opening / closing operation of this variable winning prize ball device 49, the constant supply operation by winning the winning opening 47, the blinking of the lamp windmill 43, and the like are controlled by the game control device 28 shown in FIG.

Referring to FIG. 1, the game control device 28 and the image display device 50 will be described in detail. This game control device 2
8 is configured by a microcomputer that operates according to a preset program,
Various game information such as scroll information, reach information, jackpot information, and probability variation information are output to the image display device 50.

The rotation of the handle grip 8 is detected by the sensor 3.
1a, which is used as a game start detection signal. When the game control device 28 receives the game start detection signal, a series of operations is started. The sensor 31b detects that the game ball hit by the player has won the starting winning openings 45 and 46,
When the game control device 28 receives the winning detection signal, the game control device 28 instructs to display images of, for example, three rotating slots on the image display device 50 according to a program, and the game control device 28 has a built-in image. Each slot is sequentially stopped by the stop symbol combination determining means using the random numbers. At this time, when the symbols of the two slots are aligned, a reach state is established, and the reach state is controlled. Subsequently, the remaining one slot is rotated, and when three symbols are aligned, a big hit (bingo) process is performed. Further, when the three patterns are not finally aligned, a detachment process is performed.
The jackpot processing is performed at a predetermined time in the opening and closing plate 48 of the variable winning opening 49.
Is kept open and a jackpot is displayed. In the losing process, a losing display is performed with the open / close plate 48 of the variable winning opening 49 closed. The jackpot display and the loss display are processes for displaying an image prepared in advance using the display screen of the image display device 50 that has displayed images of three rotating slots.

The CPU 29 in the image display device 50 is a CPU
The display image setting value is written to the priority register 23a and the attribute register 23b every time the image is rewritten via the interface 22. The unit image number is written in the priority register 23a at a position corresponding to the display priority. Priority 0 is the image which has the lowest display priority and is displayed first. Display attributes such as sprite images and groups described later are written in the attribute register 23b.

The image display device 50 has a program memory 10 storing a program in addition to the CPU 29, and all operations are performed in accordance with the program read from the program memory 10. Although a circuit for changing a pallet, a color mode, and the like is not shown in FIG. 1 for simplicity of description, an actual circuit further includes many circuits other than those shown in the figure. Needless to say, The image display device 50 includes an image display control unit 20 and a display device 33 using a liquid crystal or the like. An image from an image buffer memory 32 described later is displayed on the display device 33.

Next, the image display control unit 20, which is a main component of the image display device 50, will be described. In FIG.
The image display control unit 20 includes a CG memory 21, a CPU interface 22, a register 23, an address generation unit 24, a display processing engine 25, a synchronization signal generation unit 27, an image data output unit 26, a CPU 29, a program memory 10, and an image buffer memory 32. The register 23 has a priority register 23a and an attribute register 23b. The image buffer memory 32 has a frame memory A (32c) and a frame memory B (32d) each having a storage capacity for one frame, and a frame memory A (32c) and a frame memory B (32d).
Is provided with a pair of switches 32a and 32b, which are complementarily switched so that one of them is written and the other is read.

The image data output unit 26 sequentially displays the display attributes of the image in accordance with the display priority specified in the priority register 23a, starting from the image with the lower display priority, that is, the image overwritten by the image drawn later. From the attribute register 23b, the address of the corresponding image is generated from the address generation unit 24, and the corresponding image data is read from the CG memory 21. The image data output unit 26 performs image processing such as rotation and reduction of the read image using the display processing engine 25 according to the display attribute. Specifically, the display processing engine 25 issues an address generation instruction for performing processes such as image rotation, enlargement, and reduction based on the display attributes read from the attribute register 23b.
4 and the address generation unit 24 generates a read address to the CG memory 21 to read image data. The enlargement can be realized by continuously generating the same address a plurality of times according to the enlargement ratio. In the case of reduction, it can be realized by thinning out addresses. In the case of rotation, it can be realized by performing processing of converting addresses in the X direction and the Y direction at a predetermined rate according to the rotation angle.

In such processing as well, for example, if the enlargement ratio is large, the time for continuously outputting the same address becomes long, so that the processing takes time. Further, even when the number of characters performing rotation or the like is large, more time is required for processing. In the case where there is a large amount of work that has a heavy processing load, the number of windows whose work is completed within 1/60 second is limited, and the work may not be completed within 1/60 second in the last window. Therefore, the image data output unit 26 continues to output the switching prohibition signal 26a until the processing of the image with the highest priority in the priority register 23a ends.

The horizontal synchronizing signal H is output from the synchronizing signal generator 27.
sync, a vertical synchronization signal Vsync, and a dot clock Dot clk for the liquid crystal display device. The switches 32a and 32b of the image buffer memory 32 complementarily switch between writing and reading every 60 lines in synchronization with the vertical synchronization signal Vsync. The vertical synchronization signal V output from the synchronization signal generator 27
sync is supplied to the D-type flip-flop 3 via the AND circuit 35.
4 is output. The D flip-flop 34 inverts the output state each time a pulse is input to the clock terminal, and maintains that state until the next pulse is input. Therefore, when the vertical synchronization signal Vsync shown in FIG. 4A is directly input, the output is inverted in the order of the frame memory A and the frame memory B every one vertical synchronization period as shown in FIG. During the period, the output from the same frame memory is maintained.

The output of the D-type flip-flop 34 is supplied to switches 32a and 32b and also to write enable / read enable terminals of image buffer memories 32c and 32d.
Write and read permission are given in synchronization with the switching of b. Here, the vertical synchronizing signal Vsync from the synchronizing signal generator 27 is output to the D-type flip-flop 34 via the AND circuit 35, and the other input terminal of the AND circuit 35 is prohibited from switching from the image data output unit. Signal 2
6a (shown in FIG. 4 (3)) has been input.
As shown in (4), the switching prohibition signal 26a is "L".
During this period, the switches 32a and 32b are maintained as they are, no matter how high the vertical synchronization signal Vsync rises.
Therefore, the switch between the write side and the read side of the switches 32a and 32b switches at the timing when the next vertical synchronizing signal Vsync rises after the switching prohibition signal 26a changes to "H". Therefore, the switching prohibition signal 26
The same frame memory A (32c) or frame memory B (3) continues for several frames until a changes to "H".
The image from 2d) is displayed on the liquid crystal display device 32.

Therefore, the image from the same frame memory is continuously output until the processing of the image with the highest priority in the priority register 23a is completed. . Next, an image display control unit 20 according to a second embodiment of the present invention will be described. FIG. 3 is a block diagram illustrating an image display control unit 20 according to the second embodiment of this invention.
In the image display control unit 20 according to the first embodiment, the switching prohibition signal 26a is configured to switch from “L” to “H” when the processing by the display processing engine 25 is completed. , 32b are actually switched at the rising timing of the next vertical synchronizing signal. In other words, it suffices to determine the processing time in the display processing engine 25 in units of one frame.

In the present embodiment, the display processing engine 25
The display program sets in advance the processing time required in the setting rate register 23c of the register 23 as one of the display attributes for each display image by the display program as to how many frames of time are required. As shown in Table 1 of FIG. 5, this set rate can be set in eight steps from 000 indicating switching every 1/60 second to 111 indicating switching every 1 second.

In FIG. 3, an AND circuit 39 is a circuit for rewriting the register 23 in synchronization with the vertical synchronization signal Vsync. In FIG. 3, the image display control unit 20
Are a CG memory 21, a CPU interface 22, a register 23, an address generation unit 24, a display processing engine 2
5. Synchronous signal generator 27, image data output unit 26, CP
U29, program memory 10, image buffer memory 3
2, a switching limiting circuit 30, a decoder 37, and a counter 36, and the register 23 includes a priority register 23a, an attribute register 23b, and a setting rate register 2
3c. The image buffer memory 32 has a frame memory A (32c) having a storage capacity of one frame.
And frame memory B (32d) and frame memory A
(32c) and a pair of switches 32a, 32b that are complementarily switched so that one of the frame memory B (32d) and the other is read when writing. Furthermore,
A down counter 36 for outputting a trigger pulse having a variable period to the clock terminal of the D-type flip-flop 34, a decoder 37 for setting an initial value of the down counter 36, and
An AND circuit 38 for limiting rewriting of the set rate register 23c is provided.

The image data output unit 26 displays the display attributes of the images in order from the image with the lower display priority, that is, the image overwritten by the image drawn later, according to the display priority specified in the priority register 23a. From the attribute register 23b, the address of the corresponding image is generated from the address generation unit, and the corresponding image data is read from the CG memory 21. The image data output unit 26 performs image processing such as rotation and reduction of the read image using the display processing engine 25 according to the display attribute.

Codes from 000 to 111 shown in Table 1 are set in the set rate register 23c according to the image to be displayed. This code is selected so that the switching timing of the display image on the liquid crystal display device 32 is a time necessary and sufficient for performing the processing in the display processing engine 25. Codes from 000 to 111 shown in Table 1 are supplied from the setting rate register 23c to the decoder 37, and the initial value of the counter 36 corresponding to the code is set in the counter 36.

For example, when the code is 010, the counter 35 sets an initial value 3 and outputs a clock to the clock terminal of the D-type flip-flop 34 every time the vertical synchronization signal Vsync is input three times. Therefore, in this case, the display processing engine 25 only needs to finish the processing within 1/20 ms. Similarly, when the maximum code 111 is set, the same image is displayed while counting 60 frames, and the process may be completed within 1000 ms = 1 second.

If the set rate register 23c of the register 23 is rewritten before the AND circuit 38 finishes counting the initial value set in the counter 36, the screen is switched before the processing in the display processing engine 25 is completed. Since the screen may not be switched after a long time if it is performed or rewritten frequently, when the initial value is set once, the set value is counted and a clock is output to the clock terminal of the D-type flip-flop 34. Until rewriting is prohibited. Since one input of the AND circuit 38 is an inverted output of the down counter 36, C
The data of the set rate from the PU interface circuit 22 is when the down counter 36 finishes counting and outputs a pulse.

This embodiment has an advantage that display switching can be set in advance by a program creator. On the other hand, in the first embodiment, since the switching is not performed until the processing is actually completed, the abnormal display is not performed even if the display processing takes longer than originally planned for some reason.

[0030]

As described above, according to the present invention, an image display for a game machine capable of programming various display images and complicated images without worrying about the load on the arithmetic unit in the display image generation circuit. An apparatus can be provided. As a result, the number of window characters to be displayed can be increased, so that a complicated image can be displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image display device according to a first embodiment of the present invention.

FIG. 2 is a front view of a pachinko machine to which the image display device of FIG. 1 is attached.

FIG. 3 is a block diagram illustrating a configuration of an image display device according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram illustrating an operation of the image display device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing Table 1.

[Explanation of symbols]

 Reference Signs List 21 CG memory 22 CPU interface 23a Priority register 23b Attribute register 23c Setting rate register 24 Address generation unit 26 Image data output unit 27 Synchronization signal generation unit 28 Game machine control device 30 Image switching restriction circuit 32 Image buffer memory 32a, 32b switch 33 Display apparatus

Claims (6)

[Claims] 1. An image processing means for generating a display image, first and second frame buffers for storing image signals, a display device for displaying an image in frame units, and the first and second frames A first switch unit connected to a buffer and the display device to selectively connect one frame buffer to the display device; and one frame connected to the first and second frame buffers and the image processing unit. Second switch means for selectively connecting a buffer to the image processing means; and one of the first and second frame buffers being the other when the first and second frame buffers are rewritten to the first and second switch means. Switching signal supply means for supplying a complementary switching signal to be read by the frame buffer, and the first and second switching means by masking the rewrite timing signal. An image display device comprising switching prohibition means for supplying to a stage. 2. The image processing device according to claim 1, wherein the image processing unit reads a unit image from the CG memory based on display image information from an external device and generates a display image. , The second
An image display device, comprising: an image generation unit that outputs the image to a switch unit, and outputs a switching prohibition signal to the switching prohibition unit until the image generation unit finishes generating a display image for one screen. 3. A main CPU for instructing a change of a display image based on winning information, and reading out the unit image from a CG memory for storing various unit images based on an instruction from the main CPU to generate and output a display image. An image generation unit; first and second frame buffers for storing the display image, and write switching switch means for switching the display image for each frame and supplying the display image to the first and second frame buffers; Read-out switch means for switching and outputting the display image from the second frame buffer for each frame, and connected to the read-out switch means;
Display means for displaying a display image supplied from a second frame buffer, wherein switching of the write switch switch and the read switch switch is inhibited until image rewriting for one frame in the image generator is completed. An image display device for a gaming machine, comprising a switching prohibiting means. 4. An image display device for a game machine according to claim 3, wherein said display means repeatedly reproduces an image of the same frame when the switching is prohibited by said switching prohibiting means. 5. A main CPU for instructing a change of a display image based on winning information, and reading out the unit image from a CG memory storing various unit images based on an instruction from the main CPU to generate and output a display image. An image generation unit; a write switch switch unit for alternately switching between the first and second frame buffers for storing the display image and the display image at predetermined timings and supplying the display image to one of the first and second frame buffers. Read-out switch means for alternately switching and outputting the display image from the first and second frame buffers at predetermined timings; and a read-out switch means connected to the read-out switch means;
Display means for displaying a display image supplied from the second frame buffer; a timing register for setting switching timing of the write changeover switch means and readout changeover switch means; switching between the write changeover switch means and the readout changeover switch means A switching prohibition unit for prohibiting the operation until a period set in the timing register. 6. A switching device according to claim 5, further comprising a table storing a plurality of switching timings of said write switch switch and read switch switch, wherein said switch prohibiting unit responds from said table based on a value set in said timing register. An image display device for a gaming machine, wherein a switching timing to be read is read and switching is prohibited until the read period.