JPH1117720A - Transmission equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide equipment, which can prevent overflow from occurring on the side of reception equipment, by variably controlling transmission frequency while switching the validity/invalidity of a read signal from a FIFO type memory when transmitting a frame at every prescribed time while using the FIFO type memory. SOLUTION: A CPU 110 has a function as a variable transmission frequency control means and controls transmitting operation while being connected to a gate 113 and a FIFO memory 100. The FIFO memory 100 is a first-in first-out type memory and is connected to the CPU 110, gates 114 and 113 and flip-flop 92. The flip-flop 92 inverts a control signal IFLG1 and is connected to the FIFO memory 100 and the gate 113. The gate 113 is an OR gate and controls a signal RD showing data transmission while being connected to the CPU 110 and the FIFO memory 100. The gate 114 is a NOT gate and inverts the level of output data while being connected to the FIFO memory 100.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitting apparatus which is used, for example, when a master station and a plurality of slave stations are connected in a ring and communication is performed between the master station and the slave stations.

[0002]

2. Description of the Related Art For example, one master station 1 as shown in FIG.
In a communication system in which the base station 171 and a plurality of slave stations 172 are connected in a ring and communicate with each other, one frame, which is a unit of communication from the master station 171 to one slave station 172, includes synchronization information and identifies the slave station. It consists of address information and data of a predetermined length.

In this communication system, the master station 171
Transmits the frame for each slave station 172 to the next slave station 172 in order. On the other hand, the slave station 172 receives the frame addressed to itself, based on the address information, captures the data of this frame, inserts the data addressed to the master station into this frame as necessary, and The data is transmitted to the station 172, and finally, the master station 171 receives the data of the frame from each slave station 172.

[0004] Therefore, in the conventional communication system, even when there is no new data for a certain slave station 172 (that is, when it has not been updated), the master station 171 transmits the data before update. Until the data is updated, the same frame is transmitted redundantly, which is inconvenient in transmitting a series of data such as character information.

More specifically, for example, one character data or the like
Long data that cannot be transmitted in a frame must be transmitted over a plurality of frames, and if the frames overlap as described above, there is a problem that accurate data transmission cannot be performed.

In order to solve this problem, for example, if data indicating transmission over a plurality of frames or data indicating the order of frames is added, the transmission efficiency is reduced.

[0007] For this reason, the present applicant has disclosed in
No. 0758, a communication method capable of accurately transmitting long data that needs to be transmitted over a plurality of frames, and a transmission method capable of improving transmission efficiency as compared with a conventional communication system. An apparatus and a receiving apparatus are disclosed.

Hereinafter, the communication method, the transmitting device and the receiving device will be described in detail with reference to the drawings. This is 1
The present invention is applied to a communication system in which one master station and a plurality of slave stations are connected in a ring to perform communication.

In this communication system, for example, as shown in FIG. 2, one master station 10 and N slave stations 20 _i (i = 1,
2... N) are connected in a ring shape by an optical cable, for example.

[0010] Then, the master station 10, data for one slave station 20 _i is, for example, one of a predetermined length of data such as control commands, or for example by determining long or series of data of character information or the like, a series Is divided for each predetermined length.
Next, the master station 10 identifies a first flag for identifying that the same frame is transmitted redundantly and whether the data for one slave station 20 _i is a series of data or one predetermined length of data. A second flag is added to each of the divided data to form a frame.

The value of the first flag is set to a value different from the value of the first flag of the previous frame when the same data as that of the previously transmitted frame (hereinafter, referred to as the previous frame) is not transmitted repeatedly. When the same data as the data of the previous frame is transmitted redundantly, the same value as the value of the first flag of the previous frame is used.

[0012] Further, the master station 10, respectively adds synchronization information to the frame for each slave station 20 _i, collecting frame for all slave station 20 _i, adds a header information at a predetermined position, a series of frames formed, and transmits to the slave station 20 ₁ the series of frames as communication data. Furthermore, the master station 10 receives the communication data consisting of a series of frames from the slave station 20 _N, is adapted to receive data from the slave station 20 _i.

On the other hand, the slave station 20 _i detects header information from the received communication data, counts the number of pieces of synchronization information from the header information, and detects a frame for the own station.
Then, the slave station 20 _i determines, based on the second flag, whether the data of the received frame is a series of data or one predetermined length of data. When the data of the received frame is a series of data, The change of the first flag is detected for each frame, and the first flag of the current frame is set to the first flag of the previous frame.
When the flag is the same as that of the current frame, the data of the current frame is invalidated. When the first flag of the current frame is different from the first flag of the previous frame, the data of the current frame is validated.

The slave station 20 _i is connected to the master station 1 if necessary.
The communication data in which the data addressed to 0 is inserted into the frame addressed to the own station is transmitted to the next slave station 20 _{i + 1} .

[0015] Specifically, the master station 10 communicates with the above-mentioned FIG.
As shown, a random access memory (hereinafter, RAM hereinafter) for storing data from the data and all slave station 20 _i for all slave station 20 _i and 11, sequentially reads the data for the RAM11 slave station 20 _i, A transmission / reception circuit 1 for sequentially forming frames for each slave station 20 _i by adding the first and second flags to form communication data
2, electronic transducer for transmitting communication data formed by said transmission reception circuit 12 to the slave station 20 ₁ as an optical signal (hereinafter, E /
O / E converter) 13, a photoelectric converter (hereinafter referred to as an O / E converter) 14 which receives an optical signal from the slave station 20 _N and supplies communication data to the transmission / reception circuit 12, and a CPU.
15 is provided.

The RAM 11 is composed of, for example, a two-port RAM capable of simultaneously performing writing and reading, and the CPU 15 writes data for the slave station 20 _i to the RAM 11 asynchronously with the transmission path.

The transceiver circuit 12 reads the data for all slave station 20 _i stored in the RAM 11, for example, slave station 20 _1, the order of the child station 20 ₂ ..., the first and second flags and synchronization information forming a frame for each slave station 20 _i and the like added to.

[0018] The transmitting and receiving circuit 12, as well as collect frames for all slave station 20 _i, adds a header information at a predetermined position, to form a series of frames, E / O converts this series of frames as communication data To the vessel 13.

The E / O converter 13 converts communication data supplied from the transmission / reception circuit 12 into an optical signal, and converts the communication data into an optical signal.
To send to 0 _1.

Here, the format of communication data transmitted from master station 10 will be described. This communication data,
That is, a series of frames 33 is composed of frames 32 _i for all slave stations 20 _i , for example, as shown in FIG.
The frame 32 _i is composed of data 30 _i to which the first and second flags and the like are added and a start bit 31 which is synchronization information.
It is composed of

Further, as shown in FIG. 4A, for example, the frame 32 _i includes 2-bit control codes CNT0 and CNT.
T1 (second flag) and a 2-bit control flag FLG
0, FLG1 (first flag) and 8-bit data D
O, a 1-bit clear bit CLR, and a 1-bit response bit TAK, and an interval (space) SPC is provided between adjacent frames.

The start bit 31 has a value of 1, for example. Meanwhile, as the header information of a sequence of frames 33 described above, the value of the clear bit CLR of the last frame 32 _N of a series of frames 33 are set to 1,
The value of the clear bit CLR of the other frame 32 _i (i ≠ N) is set to 0.

The data DO, control codes CNT0 and CNT1, control flags FLG0 and FLG1, and the like are set by the CPU 15. That is, in the RAM 11, for example, as shown in FIG.
0 and an area (hereinafter referred to as a DI area) 60 for storing received data and the like are provided.
0 is a 2-byte area 5 for each slave station 20 _i .
1 when the CPU 15 transmits data to the slave station 20 _i , the CPU 15 writes the data in the area 51 corresponding to the slave station 20 _i , and controls the control flags FLG 0, FLG
1, values of control codes CNT0, CNT1, etc. are set.

[0024] Then, CPU 15, when transmitting one of a predetermined length of data as the data for the slave station 20 _i is a control code CNT0 1, a control code CNT1 0
And When transmitting a series of data as data to the slave station 20 _i , the CPU 15 uses the control code C
NT0 and CNT1 are both set to 1.

The transmitting / receiving circuit 12 is connected to the slave station 20 _i
Even if the data for has not been updated, the data for all the slave stations _20i are read at a predetermined cycle, and the communication data is formed and transmitted as described above. Therefore, the same data may be transmitted redundantly. Therefore, when updating the data in the area 51, the CPU 15 inverts the value of the control flag FLG0.

On the other hand, the O / E converter 14 receives an optical signal from the slave station 20 _N and supplies communication data to the transmission / reception circuit 12. The transmission / reception circuit 12 includes the O / E converter 1
The frame from each slave station 20 _i is extracted from the communication data supplied from the communication station 4 and stored in the RAM 11. More specifically, for example, as shown in FIG. 5 described above, the DI area 60 of the RAM11 are all slave stations 20 _i
Are allocated a 2-byte area 61,
When receiving the communication data, the transmission / reception circuit 12
_In the area 61 corresponding to _i , data from the slave station 20 _i , control flags FLG0, FLG1, control codes CNT0, CN
T1 and the like are written. And CPU1
5 reads data or the like from the area 61 that corresponds to the child station 20 _i, receives the data from the slave station 20 _i.

On the other hand, as shown in FIG. 2, the slave station 20 _i extracts an O / E converter 21 for receiving an optical signal and outputting communication data, and extracts a frame addressed to the own station. A transmission / reception circuit 22 that inserts data for the master station 10 into this frame to form communication data, and an E / O converter 23 that converts the communication data formed by the transmission / reception circuit 22 into an optical signal and transmits it. And a CPU 24.

The O / E converter 21 receives the optical signal and supplies communication data to the transmission / reception circuit 22. The transmission / reception circuit 22 detects a frame in which the value of the clear bit CLR is 1 from the communication data supplied from the O / E converter 21, counts the number of start bits 31 from this frame, and counts the frame addressed to the own station. Is detected, and the data addressed to the own station is
Supply to PU24.

That is, the address information of the slave station 20 _i required in the conventional communication system can be deleted.
Transmission efficiency can be improved.

More specifically, the transmission / reception circuit 22 determines whether the data of the received frame is a series of data or one predetermined length of data based on the values of the control codes CNT0 and CNT1, and determines the series of data. At this time, the control flag FL of the current frame is set based on the value of the control flag FLG0.
When G0 is the same as the control flag FLG0 of the previous frame, the data of the current frame is invalidated. When the control flag FLG0 of the current frame is different from the control flag FLG0 of the previous frame, the data of the current frame is valid. The data is supplied to the CPU 24.

The CPU 24 also operates the master station 1 as necessary.
The data for 0 is supplied to the transmission / reception circuit 22. The transmission / reception circuit 22 adds a control flag FL to the data from the CPU 24.
G1 and the like are added to form a frame, and this frame is inserted into communication data and supplied to the E / O converter 23. Then, the E / O converter 23 converts the communication data from the transmission / reception circuit 22 into an optical signal and transmits the optical signal to the next slave station 20 _{i + 1} .

Similarly, the slave stations 20 _{i + 2} and 20
_{i + 3} ... insert a frame for the master station 10 into the communication data as necessary and transmit it to the next slave station 20. Thus, communication data from the slave station 20 _N is supplied to the master station 10.

Here, the format of communication data received by master station 10 will be described.

The communication data, that is, a series of frames 43 is composed of frames 42 _i for all the slave stations 20 _{i as} shown in FIG.
_i is composed of data 40 _i to which a control flag or the like is added and a start bit 41.

Furthermore, the frame 42 _i, for example, as shown in B of FIG. 4, the 2-bit control code CNT0, CN
T1, a 2-bit control flag FLG0, FLG1,
8-bit data DI and 1-bit clear bit CL
A space SPC is provided between R and an adjacent frame.

The transmission / reception circuit 22 sets the value of the control flag FLG1 to a value different from the value of the control flag FLG1 of the previous frame when the same data as the data of the previous frame transmitted last time is not transmitted repeatedly. When the same data as that of the data is transmitted redundantly, the control flag F
The value of LG1 is set to the same value as the value of the control flag FLG1 of the previous frame.

Next, a specific protocol in the communication system configured as described above will be described.

First, the master station 10 sends the slave station 20 _i
For example, an operation of transmitting the above-described series of data will be described.

As shown in FIG. 6A, for example, the CPU 15 divides a series of data to be transmitted to the slave station 20 _i into 8 bits and writes the data into the area 51 corresponding to the slave station 20 _i. Then, the value of the control flag FLG0 is inverted, for example, from 0 to 1, and the control codes CNT0, CNT1
Is 1 representing a series of data.

[0040] The transceiver circuit 12, together forming a frame are read in the order the data for all slave station 20 _i as described above, and a low level control signal EFLG0 that notifies of the transmission data is read to the CPU15 I do.

Then, the CPU 15 outputs the control signal EFLG
When 0 becomes low level, the next divided 8 bits are written into the area 51, and the value of the control flag FLG0 is inverted, and the CPU 15 and the transmission / reception circuit 12 repeat the above operation. Thus, CPU 15 sequentially divides the series of data to the slave station 20 _i, and transmits.

The slave station 20 _i transmits the control flag F
The communication data in which the values of LG0 and control code CNT1 are controlled is received. Then, the transmission / reception circuit 22 determines whether the received data is a series of data or one predetermined length of data based on the value of the control code CNT1, and in this case, since the control code CNT1 is 1, the series of data is Determine that it was received.

The transmission / reception circuit 22 is provided, for example, in FIG.
As shown in the figure, a change in the control flag FLG0 is detected for each frame to generate a flag signal OFLG0 representing the value of the control flag FLG0, and the flag signal OFLG for the current frame is generated.
When 0 is different from the flag signal OFLG0 of the previous frame, the data of the current frame is validated and supplied to the CPU 24,
When the flag signal OFLG0 of the current frame is the same as the flag signal OFLG0 of the previous frame, the data of the current frame is invalidated and is not supplied to the CPU 24.

Then, the transmission / reception circuit 22 repeats the above operation. Thus, the CPU 24 can accurately receive a series of data.

Next, the operation in which the master station 10 transmits data of one predetermined length, for example, 8 bits, to the slave station 20 _i will be described.

The CPU 15 of the master station 10 writes 8-bit data into the area 51, and sets the value of the control code CNT0 to 1 and the value of CNT1 to 0. And the slave station 20 _i
The transmission / reception circuit 22 of the control unit 22 transmits the received data to the CP regardless of the value of the control flag FLG0 because the value of the control code CNT1 is 1 based on the value of the control code CNT1
Supply to U24.

Thus, in this communication system, a series of data and one data of a predetermined length can be accurately communicated.

Next, a case where the slave station 20 _i transmits data to the master station 10 will be described.

The CPU 24 of the slave station 20 _i supplies data to be transmitted to the master station 10 to the transmission / reception circuit 22 as shown in FIG. 7B, for example. When data is supplied from the CPU 24, the transmission / reception circuit 22 sets the value of the control flag FLG1 to a value different from the value of the control flag FLG1 of the previous frame. Specifically, for example, the transmission / reception circuit 22 controls the control signal IFLG
1 and sets the value of the frame control flag FLG1 to the master station 10 based on the control signal IFLG1 to transmit data, and supplies the CPU 24 with a signal RD indicating that the data has been transmitted.

Then, the transmission / reception circuit 22 and the CPU 24
Data is transmitted by repeating the above operation.

Meanwhile, the transmission and reception circuit 12 of the master station 10, for example, as shown in C in FIG. 7, to extract the frame from the slave station 20 _i, supplied to the RAM 11.

At this time, the transmission / reception circuit 12 sets the control flag FLG1 of the current frame to the control flag FLG of the previous frame.
When the control flag FLG1 is equal to 1, a signal (hereinafter, referred to as a flag change signal) EFLG1 indicating a change in the control flag FLG1 is set to a low level. The flag change signal EFLG1 is set to a high level, and the flag change signal EFLG1 is
To supply.

Further, the CPU 15 outputs the flag change signal E
Based on FLG1, when the flag change signal EFLG1 is at low level, the data stored in the area 61 is read out and taken in.

[0054] Thus, the master station 10, the change of the control flag FLG1 from the slave station 20 _i detected for each frame, when the control flag FLG1 of the current frame is the same as in the previous frame as invalid data of the current frame, when the control flag FLG1 of the current frame is different from the previous frame to receive data from the slave station 20 _i as valid data of the current frame.

Here, a specific configuration of the receiving section of the transmitting / receiving circuit 22 will be described.

[0056] slave station 20 _i of the transmitting and receiving circuit 22, for example, as shown in FIG. 8, the FIFO memory 70 for storing the received data, a flip-flop 71 for storing a flag signal OFLG0 of the previous frame, the flip-flop 71
An exclusive OR gate 72 for calculating an exclusive OR of the flag signal OFLG0 of the previous frame and the flag signal OFLG0 of the current frame stored in the exclusive OR gate 7 and the exclusive OR gate 7
And a gate 73 for controlling the writing to the FIFO memory 70 based on the output of the second memory 2.

The flip-flop 71 sequentially stores the flag signal OFLG0 representing the value of the control flag FLG0 of the received frame addressed to the own station. The exclusive OR gate 72 calculates the exclusive OR of the flag signal OFLG0 of the previous frame stored in the flip-flop 71 and the flag signal OFLG0 of the current frame, and obtains the flag signal OFLG0 of the previous frame and the flag signal OFLG of the current frame.
When 0 is different, a low-level signal (hereinafter simply referred to as "0") is supplied to the gate 73, and when the flag signal OFLG0 of the previous frame and the current frame are the same, "1" is supplied to the gate 73. Supply.

When a frame addressed to the own station is received,
The gate 73 is supplied with the write request signal WR as “0”, and when the write request signal WR becomes “0”, when the output of the exclusive OR gate 72 is “0”,
The write enable signal WE, which is an output, is set to “0”. On the other hand, when the write request signal WR is “0” and the output of the exclusive OR gate 72 is “1”, the gate 73 sets the write enable signal WE to “1”.

The FIFO memory 70 stores data supplied via the buffer gate 75 when the write enable signal WE is "0". That is, data is stored in the FIFO memory 70 when the control flag FLG0 is different from the control flag FLG0 of the previous frame.

When data is stored, the FIFO memory 70 supplies the output ready signal ORDY to the CPU 24 as, for example, "1". And CPU2
4 is a FIFO memory 70 based on the output ready signal ORDY when the output ready signal ORDY is "1".
Read data from. Thus, the slave station 20 _i can correctly receive a series of data such as character information even if data is repeatedly sent from the master station 10.

By the way, the transmission / reception circuit 22 is
Flip-flop 7 for inhibiting writing to O memory 70
4 is provided. The FIFO memory 70 sets the input ready signal IRDY to “0” when, for example, data cannot be written.

The flip-flop 74 latches the input ready signal IRDY in synchronization with the start bit 31 and supplies it to the gate 73. When the inverted output of the flip-flop 74 is "1", the gate 73 The writing of the memory 70 is prohibited to prevent the overflow of the FIFO memory 70.

Further, another specific configuration of the receiving section of the transmitting / receiving circuit 22 will be described. Note that the same components as those in the circuit shown in FIG. 8 described above are denoted by the same reference numerals, and description thereof will be omitted.

Although the receiving section of the transmitting / receiving circuit 22 shown in FIG. 8 has the FIFO memory 70, the CPU 24 reads data at a sufficiently high speed compared to the frame receiving cycle, and loses the received data. When there is no fear, for example, as shown in FIG. 9, a buffer 80 for holding the received data and a flag signal OFLG0 of the previous frame are provided.
And the flag signal OFLG0 of the previous frame stored in the flip-flop 71
An exclusive OR gate 72 for comparing the flag with the flag signal OFLG0 of the current frame may be provided, and a flip-flop 83 for notifying the CPU 24 of data reception based on the output of the exclusive OR gate 72.

Then, the CPU 24 sets the control flag FLG
When the value of 0 is different from the value of the control flag FLG0 of the previous frame, the buffer 80 is opened in synchronization with the reception ready signal RxRDY supplied from the flip-flop 83 as "1", and data is taken in.
Is reset to set the reception ready signal RxRDY to “0”.

As a result, the receiving section 22 of the transmitting / receiving circuit outputs the flag signal OFLG0 as in the specific example shown in FIG.
Is detected for each frame, and when the flag signal OFLG0 of the current frame is the same as the flag signal OFLG0 of the previous frame, the data of the current frame is invalidated, and the flag signal OFLG0 of the current frame becomes the flag signal OFL of the previous frame.
When it is different from G0, the data of the current frame is validated,
Receive data.

Next, a specific configuration of the transmission section of the transmission / reception circuit 22 will be described.

The transmission unit of the transmission / reception circuit 22 is, for example, as shown in FIG.
, A register 90 for holding data from the CPU 24 to the master station 10, and a flip-flop 91 preset by a write signal WR from the CPU 24.
And a flip-flop 92 for inverting the control signal IFLG1 when transmitting data updated based on the output of the flip-flop 91.

When there is data for master station 10, CPU 24 supplies the data and write signal WR to register 90, and register 90 stores and outputs the data. Further, the CPU 24 supplies the write signal WR as a preset signal to the flip-flop 91, presets the flip-flop 91, and sets the output to “1”.

Further, when a read request signal RD is supplied when data is read from the register 90 to form a frame, the flip-flop 92 outputs the output of the flip-flop 91 using the read request signal RD as a clock. Is "1", the control signal IFLG1, which is its output, is inverted.

At this time, the flip-flop 91
Is reset by the read request signal RD, and supplies the transmission ready signal TxRDY to the CPU 24 as "1".

Thus, the transmitting section of the transmitting / receiving circuit 22 controls the control flag FLG when updating and transmitting the data.
The value of 1 is inverted, and the value of the control flag FLG1 is not inverted when transmitting data redundantly.

Here, another specific configuration of the transmitting section of the transmitting / receiving circuit 22 will be described.

The same components as those in the circuit shown in FIG. 10 are denoted by the same reference numerals, and description thereof is omitted. For example, as shown in FIG. 11, the transmission unit of the transmission / reception circuit 22 uses a FIFO instead of the register 90 shown in FIG.
The configuration uses the O memory 100. That is,
The CPU 24 can output data at high speed.

Specifically, the transmitting section of the transmitting / receiving circuit 22
FIFO memory 10 for storing data from CPU 24
0 and the output ready signal ORD of the FIFO memory 100
Flip-flop 9 for inverting output based on Y signal
2 is provided.

Then, the CPU 24 writes the data for the master station 10 into the FIFO memory 100. When the data is stored, the FIFO memory 100 sets the output ready signal ORDY signal to "1" and sets the flip-flop 9
Feed to 2. Further, when the read request signal RD is supplied when data is read from the FIFO memory 100, the flip-flop 92 outputs the control signal IFLG1 which is the output thereof if the output ready signal ORDY from the FIFO memory 100 is "1". Invert the value of. As a result, the transmission unit of the transmission / reception circuit 22 inverts the value of the control flag FLG1 when updating and transmitting data in the same manner as in the specific example shown in FIG. The value of the control flag FLG1 is not inverted.

[0077]

By the way, in the above configuration, the FI of the transmitting section of the transmitting / receiving circuit 22 shown in FIG.
The FO memory 100 is connected to the CPU 24 and stores data, and the flip-flop 92 is connected to the FIFO memory 10.
It is connected to 0 and stores a flag.
In this configuration, when a frame is sent periodically, the read signal RD of the FIFO memory 100 is supplied each time the frame is transmitted. FI
When data exists in the FO memory 100, every time the read signal RD is supplied, the FIFO memory 10
New data is read from 0 and transmitted.

In this configuration, since there is no mechanism for suppressing transmission, it is impossible to suppress transmission according to the state of the receiving apparatus. Therefore, it is impossible to prevent the receiving apparatus from overflowing.

Therefore, the present invention has been made in view of such a situation, and has as its object to provide a transmitting apparatus capable of preventing occurrence of overflow on the receiving apparatus side.

[0080]

The transmitting apparatus according to the present invention comprises:
A series of data for one slave station is divided into predetermined lengths, and a first flag is added to each of the divided data to form a frame. When the flag is set to the same value as the first flag of the previous frame, and when transmission is not repeated, the first flag is controlled to have a different value from the first flag of the previous frame. When transmitting frames at regular time intervals using the memory means and the first-in first-out memory, the validity / invalidity of the read signal of the first-in first-out memory is switched and the transmission frequency is variably controlled, whereby To solve the problems.

That is, according to the present invention, in a communication system using a transmission flag, when a transmission device using a FIFO memory is configured, a mechanism for controlling transmission is provided to prevent transmission data from overflowing on the receiving station side. Making it possible.

[0082]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic circuit configuration of a transmitting section of the present embodiment applied as a main section of the transmitting apparatus. The configuration shown in FIG. 1 is applied to, for example, the transmission unit of the transmission / reception circuit 22 shown in FIG. 2, and among the instruction numbers in the figure, the same instruction numbers as those in FIGS. Represents the same function.

In FIG. 1, CPU 110 has a function as transmission frequency variable control means of the present embodiment, and is connected to gate 113 and FIFO memory 100 to control the transmission operation.

The FIFO memory 100 is a first-in first-out type memory, and includes the CPU 110 and the gate 11
4, 113 and the flip-flop 92.

The flip-flop 92 controls the control signal I
FLG1 is inverted and connected to FIFO memory 100 and gate 113.

The gate 113 is a logical sum (AND) gate, and is connected to the CPU 110 and the FIFO memory 100, and controls a signal RD indicating that the data has been transmitted.

The gate 114 is a NOT gate and is connected to the FIFO memory 100 and inverts the level of output data.

In such a configuration, the CPU 11
0 writes data to the FIFO memory 100,
When data is stored, the O memory 100 supplies the output ready signal ORDY signal to the flip-flop 92 as "1". Further, from the FIFO memory 100,
When data is read, a read request signal RD ′
Is supplied, the flip-flop 92 inverts the value of the output control signal IFLG1 if the output ready signal ORDY from the FIFO memory 100 is “1”.

When transmitting a frame, a read request signal RD is supplied. At this time, when the next data is actually transmitted, a transmission permission signal S
END is supplied to the gate 113.

As a result, the control signal I in the flip-flop 92 is set only when actually transmitting new data.
Inversion of FLG1 occurs, and transmission can be controlled.

As described above, according to the configuration of the present embodiment, the flow control can be performed by adding a simple circuit to limit the amount of data to be transmitted.

That is, by controlling the execution speed of the communication, the overflow of the communication data is prevented, and the communication with higher reliability becomes possible.

[0094]

As is apparent from the above description, the present invention sets the flag to the same value when transmitting the same frame repeatedly, and sets the flag of the previous frame to a different value when not transmitting the same frame repeatedly. A transmitting apparatus for transmitting a frame at regular time intervals using a first-in first-out memory, by switching between valid / invalid of a read signal of the first-in first-out memory and variably controlling a transmission frequency. Thus, it is possible to prevent the occurrence of overflow on the receiving device side.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a specific configuration of a transmission unit applied to a transmission / reception circuit in a communication system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a communication system.

FIG. 3 is a diagram showing a specific format of communication data.

FIG. 4 is a diagram showing a specific format of a frame constituting the communication data.

FIG. 5 is a diagram showing specific contents of a RAM constituting a master station to which the present invention is applied.

FIG. 6 is a diagram for explaining a specific protocol of communication from a master station to a slave station.

FIG. 7 is a diagram for explaining a specific protocol of communication from a slave station to a master station.

FIG. 8 is a circuit diagram showing a specific configuration of a receiving unit of a transmitting / receiving circuit forming a slave station to which the present invention is applied.

FIG. 9 is a circuit diagram showing another specific configuration of the receiving unit of the transmitting / receiving circuit forming the slave station.

FIG. 10 is a circuit diagram showing a specific configuration of a transmission unit of a transmission / reception circuit forming a slave station to which the present invention is applied.

FIG. 11 is a circuit diagram showing another specific configuration of the transmission section of the transmission / reception circuit forming the slave station.

FIG. 12 is a diagram showing a configuration of a conventional communication system.

[Explanation of symbols]

10 master station, 11 RAM, 12, 22 transmission / reception circuit, 13, 23 E / O converter, 14, 21 O /
E converter, 20 slave stations, 110 CPU, 100
FIFO memory, 92 flip-flops, 11
3,114 gate

Claims (1)

[Claims] 1. A series of data for one slave station of a plurality of slave stations connected to one master station in a ring shape is divided for each predetermined length, and a first data is divided for each of the divided data.
Frame forming means for forming a frame by adding a flag, and transmitting means for transmitting a frame formed by the frame forming means. When transmitting the same frame repeatedly, the flag is the same as the flag of the previous frame. And a control means for controlling the frame composing means so as to set the flag to a value different from the flag of the previous frame when the transmission is not repeated, a first-in first-out memory means, A transmission frequency variable control means for variably controlling a transmission frequency by switching between valid / invalid of a read signal of the first-in first-out memory when transmitting a frame at regular intervals using a first-in first-out memory; A transmission device characterized by the above-mentioned.