JPH1117536A - Frequency synthesizer - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a frequency synthesizer capable of preventing occurrence of glitch and malfunction. Kind Code: A1 A VCO and a frequency divider circuit that divides an output signal of the VCO and outputs a pulse signal using a frequency division value of K or (K + 1) as a frequency division value in response to a count signal.
And a main counter 13 that counts down the count data value Np to 0 based on the output pulse signal of the frequency dividing circuit 12a and outputs the result, and counts the count data value A (<Np) based on the output pulse signal of the frequency dividing circuit 12a. A swallow counter 14a that counts down to 1, a flip-flop 19 that latches the output of the swallow counter based on the output pulse signal of the frequency divider 12a and outputs a count signal S19, and a count data value A that is input to the swallow counter 14a. Are provided, and an AND gate 20 for setting the flip-flop 19 when it is 0 data and a phase comparison circuit 15 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a PLL (Phase Loc
ked Loop) circuit.

[0002]

2. Description of the Related Art A pulse swallow method is known as one of the methods of a PLL frequency synthesizer.

FIG. 3 is a block diagram showing a configuration example of a frequency synthesizer employing a pulse swallow method. As shown in FIG. 3, the frequency synthesizer 10
1, (K, K + 1) frequency dividing circuit 12, main counter 1
3. Swallow counter 14, phase comparison circuit (P / C) 1
5, a low-pass filter (LPF) 16, a two-input AND gate 17, and an inverter 18.

In the frequency synthesizer 10, when the count signal S14, which is the output signal of the swallow counter 14, is input at a low level in the frequency divider 12, the output signal S11 of the VCO 11 is frequency-divided by the frequency division value K + 1. When the count signal S14 is input at a high level, the output signal S11 of the VCO 11 is frequency-divided by the frequency division value K, and the pulse signal S12 is output.

In the main counter 13, a count data value Np (N
p> 2) is counted down (counts Np pulses) based on the output signal S12 (clock signal CLK) of the frequency divider circuit 12, and when the count value becomes "1", the signal S13 is sent to the phase comparator circuit 15. Is output.

In the swallow counter 14, the frequency dividing circuit 12
Receiving the output signal S17 of the AND gate 17 which takes the logical product of the output signal S12 of the inverter 18 and the output signal S18 of the inverter 18, the count data value A (A <Np), which is an externally provided dividing constant, S17 (clock signal CL
K) is counted down (A pulses are counted), and a low-level count signal S14 is output to the frequency dividing circuit 12 and the inverter 18 when the count value becomes "0" and when the count value becomes "0". Is done.

That is, in the swallow counter 14, before the main counter 13 counts Np pulses, A pulses are counted, and the frequency dividing circuit 12 outputs A ×
A low-level pulse having a width of (pulse width of signal S12) is output. As a result, the frequency dividing circuit 12 outputs the count signal S
When 14 is at a high level, the frequency division value becomes K, so that the frequency dividing circuit 12, the main counter 13 and the swallow counter 1
4 is set to a value represented by the following equation.

[0008]

D = A (k + 1) + K (Np−A) = K · Np + A

The signal S13 is output from the main counter 1
3 and the swallow counter 14 are input as a preset enable signal PE. When the preset enable signal PE is input, the count value is preset in the main counter 13 and the swallow counter 14, and the countdown is performed from the externally supplied count data values Np and A.

The phase comparator 15 compares the phase of the output signal S13 of the main counter 13 with the phase of the reference signal Sref. As a result of the comparison, a control signal S15 indicating whether the phase of the output signal S13 of the main counter 13 is ahead or behind the phase of the reference signal Sref is fed back to the VCO 11 via the low-pass filter 16. Then, the output signal S13 of the main counter 13
When the phase difference between the reference signal and the reference signal Sref becomes zero, the locked state is established and the above-described feedback loop is stabilized.

[0011]

By the way, in the frequency synthesizer adopting the pulse swallow method, the swallow counter is programmed to divide 1 to 2 ⁿ . Therefore, normally, "0" is detected and the count signal S14 is output. Since the swallow counter in the frequency synthesizer is configured by connecting flip-flops in multiple stages, there is a latent internal delay, and as shown in FIG. 4, a glitch may occur in the "0" decode output. As a result, a malfunction is likely to occur. Since the main counter does not detect “0”, there is no possibility of malfunction due to glitch.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a frequency synthesizer that can prevent glitches from occurring and prevent malfunction.

[0013]

In order to achieve the above object, the present invention provides an oscillating means which oscillates at a frequency corresponding to the input level of a control signal and a value K when the count signal is at a first logical level. When the count signal is at the second logic level, a frequency dividing means for dividing the output signal of the oscillating means to output a pulse signal by using the value (K + 1) as the dividing ratio, Count value N
a first counter that counts down p in response to the pulse signal and outputs a detection result when 1 is detected;
A first latch circuit for holding an output signal of the first counter in response to the pulse signal; a count value A externally supplied being counted down in response to the pulse signal; , A second latch circuit for holding an output signal of the second counter in response to the pulse signal, and a second latch circuit for holding the output signal when the count value A is 0. A first control circuit for fixing an output, a second control circuit for controlling an input of the pulse signal to the second counter in accordance with an output signal of the second latch circuit; Phase comparing means for comparing the phase difference between the output signal of the latch circuit and the reference signal and outputting the result of the comparison as the control signal to the oscillating means.

Preferably, the count value A is smaller than the count value Np.

Further, the first and second counters are reset by an output signal of the first latch circuit,
The output signal of the second latch circuit is the count signal.

According to the frequency synthesizer of the present invention, in the frequency dividing means, when the output count signal of the second latch circuit is at the first logical level, the output signal of the oscillating means is frequency-divided by the frequency dividing value K, When the count signal is at the second logic level, the output signal of the oscillating means is frequency-divided with the frequency division value (K + 1) and output as pulse signals to the first counter and the second counter. In the first counter, an externally applied count data value Np is counted down based on the output pulse signal of the frequency dividing means, and a signal indicating that the count value has become 1 is output to the first latch circuit. In the first latch circuit, a signal output from the first counter is output to the phase comparing means in response to an output pulse signal of the frequency dividing means.

In the second counter, upon receiving the output pulse signal of the frequency dividing means, the count data value A (A <Np) given from the outside is counted down based on the output pulse signal, and the count value becomes 1. Is output to the second latch circuit. In the second latch circuit, the signal output from the second counter is output to the frequency dividing means in response to the output pulse signal of the frequency dividing means. When the count data value A is equal to or greater than "1", the second counter outputs a signal indicating that the count value has become 1 to the second latch circuit, and the signal is output to the frequency divider output pulse signal. The response is output to the frequency dividing means. On the other hand, when the count data value A is given as “0”, the output of the second latch circuit is fixed by the second control circuit. Therefore, at this time, a glitch based on a delay or the like in the counter does not occur. The frequency division value of the frequency dividing means changes to K or (K + 1) according to the output signal of the second latch circuit. As a result, the frequency dividing means, the first and second counters, and the first and second counters Is set to (K · Np + A). The phase comparing means compares the phase of the output signal of the first latch circuit with the phase of the reference signal, and outputs a control signal corresponding to the comparison result to the oscillating means. Then, when the phase difference between the output signal of the first latch circuit and the reference signal becomes zero, a locked state is established, and the above-mentioned feedback loop is stabilized.

[0018]

FIG. 1 is a block diagram showing an embodiment of a frequency synthesizer according to the present invention, and the same components as those in FIG. 3 showing a conventional example are denoted by the same reference numerals.

That is, the frequency synthesizer 10a
Are a VCO 11 as an oscillating means, a (K, K + 1) dividing circuit 12a as a dividing means, a main counter 13,
Swallow counter 14a, phase comparison circuit (P / C) 1
5, a low-pass filter (LPF) 16, a two-input AND gate 17, an inverter 18, a flip-flop 19, and an AND gate 20 as reset means having five negative inputs.

The frequency dividing circuit 12a includes a flip-flop 19
When the output count signal S19 is input at a low level, the output signal S11 of the VCO 11 is divided by the divided value (K +
1), and when the count signal S19 is input at a high level, the output signal S11 of the VCO 11 is divided by the divided value K, and the main counter 13, the AND gate 17, and the flip-flop 19 are used as the pulse signal S12a. Output to

The main counter 13 counts a count data value Np (Np>
2) is counted down (counts Np pulses) based on the output pulse signal S12a (clock signal CLK) of the frequency dividing circuit 12a, and when the count value becomes "0", the signal S13 is sent to the phase comparison circuit 15. Output. In addition,
The main counter 13 is constituted by a plurality of flip-flops, and the last-stage flip-flop FF2 as a latch circuit latches the count value 1 and the output timing thereof becomes the count 0.

The swallow counter 14 includes a frequency dividing circuit 12a.
And the output signal S of the AND gate 17 which takes the logical product of the output pulse signal S12a of the
In response to the signal 17, the count data value A (A <Np) as a frequency dividing constant provided from the outside is counted down based on the signal S17 (clock signal CLK) (A pulses are counted), and the count result is flip-flopped. Output to the loop 19.

In this frequency synthesizer 10a, a swallow counter 14a which is a program counter
Is supplied as 5-bit data. The output terminal of the swallow counter 14a is connected to the input terminal D of the flip-flop 19, and the input line of 5-bit data A to the swallow counter 14a is connected to each inverting input terminal of the AND gate 20. The output terminal of the gate 20 is a flip-flop 1
9 is connected to the set terminal S. That is, when the 5-bit data A is all given as "0", the flip-flop 19 is held in the set state (1) by the AND gate 20. When the 5-bit data value A is other than "0", the swallow counter 14a outputs "1" to the flip-flop 19 at the timing of counting "1".

Next, the operation of the above configuration will be described. In the frequency dividing circuit 12a, when the output count signal S19 of the flip-flop 19 is input at a low level, VC
When the output signal S11 of O11 is divided by the division value (K + 1) and the count signal S19 is input at a high level, the output signal S11 of the VCO 11 is divided by the division value K, and the main counter is used as the pulse signal S12a. 1
3, and output to the clock input of AND gate 17 and flip-flop 19.

In the main counter 13, the count data value Np (Np> 2) supplied from the outside is counted down based on the output signal 12a (clock signal CLK) of the frequency dividing circuit 12 (Np pulses are counted). , A signal S13 indicating that the count value has become 0 is output to the phase comparison circuit 15.

In the swallow counter 14a, the frequency dividing circuit 1
Receiving the output pulse signal S17 of the AND gate 17, which takes the logical product of the output pulse signal S12a of FIG. Counted down based on When the count value becomes 1, a signal of “1” is output to the flip-flop 19. At this time, the constant data A to the swallow counter 14a is 5
Although given as bit data, it is input to the AND gate 20 in parallel with the input to the swallow counter 14a. When the 5-bit data A is all "0", the output of the AND gate 20 goes high, and the flip-flop 19 is set. That is, when the 5-bit data A is not “0”, “1” is input to the input D of the flip-flop 19 at the timing when the swallow counter 14a counts “1”, and when the 5-bit data A is “0”, The flip-flop 19 is in the set state and always outputs "1". Therefore, at this time, a glitch based on a delay or the like in the counter does not occur.

That is, in the swallow counter 14a and the flip-flop 19, the main counter 13
Before counting the pulses, A pulses are counted, and a low-level pulse having a width of A × (pulse width of the signal S12a) is output to the frequency dividing circuit 12a. As a result, when the count signal S19 is at a high level, the frequency division value of the frequency division circuit 12a becomes K. Therefore, the frequency division circuit 12a, the main counter 13, and the swallow counter 14a determine that the entire frequency division ratio D is (KNp + A). ).

The signal S13 is input to the main counter 13 and the swallow counter 14a as a preset enable signal PE. Preset enable signal P
When E is input, the count value is preset in the main counter 13 and the swallow counter 14a, and the count data value N as an externally provided dividing constant is provided.
Countdown is performed from p and A.

The phase comparator 15 compares the phase of the output signal S13 of the main counter 13 with the phase of the reference signal Vref. As a result of the comparison, a control signal S15 indicating whether the phase of the output signal S13 of the main counter 13 is ahead or behind the phase of the reference signal Vref is fed back to the VCO 11 via the low-pass filter 16. Then, the output signal S13 of the main counter 13
When the phase difference between the reference signal Vref and the reference signal Vref becomes zero, the locked state is established, and the above-described feedback loop is stabilized.

As described above, according to the present embodiment, Vs oscillating at a frequency corresponding to the input level of the control signal
The output signal of the VCO 11 is frequency-divided with the value of (K + 1) when the count signal of CO11 and the low-level count signal are input, and the value K when the count signal of the high level is input, and a pulse signal is output. A frequency dividing circuit 12a, a counter section for counting down an externally supplied count data value Np to 1 based on an output pulse signal of the frequency dividing circuit 12a, and an output signal of the counter section based on an output pulse signal of the frequency dividing circuit 12a. A main counter 13 including a flip-flop FF2 to be latched;
The swallow counter 14a counts down the count data value A smaller than the externally applied count data value Np to 1 based on the output pulse signal of 1 and the output of the swallow counter 14a is latched based on the output pulse signal of the frequency dividing circuit 12a. Flip-flop 19 and count data value A input to swallow counter 14a
And compares the phase difference between the output signal of the main counter 13 and the reference signal with the AND gate 20 that sets the flip-flop 19 when the count data value A is 0 data. LPF16 as
And the phase comparison circuit 15 that outputs the signal to the VCO 11 via the VCO 11. Therefore, the occurrence of glitches can be reliably prevented, the occurrence of malfunctions can be prevented, and a highly accurate frequency synthesizer can be realized.

[0031]

As described above, according to the frequency synthesizer of the present invention, the occurrence of glitch can be prevented, and the malfunction can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a pulse swallow frequency synthesizer according to the present invention.

FIG. 2 is a diagram for explaining a frequency dividing operation of the circuit of FIG. 1;

FIG. 3 is a block diagram showing a configuration example of a conventional pulse swallow frequency synthesizer.

FIG. 4 is a diagram for explaining a frequency dividing operation of the circuit of FIG. 3;

[Explanation of symbols]

 10a: Pulse swallow frequency synthesizer 11: VCO 12a: Divider 13: Main counter 14a: Swallow counter 15: Phase comparator (P / C) 16: Low-pass filter (LPF) 17: 2-input AND gate 18: Inverter 19 ... Flip-flop 20 ... And gate

Claims (3)

[Claims] An oscillating means for oscillating at a frequency corresponding to an input level of a control signal; a value K as a dividing ratio when the count signal is at a first logic level; In some cases, frequency dividing means for dividing the output signal of the oscillating means to output a pulse signal with the value (K + 1) as a dividing ratio, and counting down an externally applied count value Np in response to the pulse signal, A first counter that outputs a detection result when 1 is detected; a first latch circuit that holds an output signal of the first counter in response to the pulse signal; A second counter that counts down in response to the pulse signal and outputs a detection result when 1 is detected; and an output signal of the second counter in response to the pulse signal. A second latch circuit, a first control circuit for fixing an output of the second latch circuit when the count value A is 0, and a pulse according to an output of the second latch circuit. A second control circuit for controlling an input of a signal to the second counter, a phase difference between an output signal of the first latch circuit and a reference signal, and a comparison result as the control signal; Frequency synthesizer having a phase comparison means for outputting to the means. 2. The counter value A is equal to the count value Np.
The frequency synthesizer according to claim 1, wherein the frequency synthesizer has a value smaller than the frequency synthesizer. 3. The method according to claim 1, wherein the first and second counters are reset by an output signal of the first latch circuit, and an output signal of the second latch circuit is the count signal. Frequency synthesizer.