JPH1116701A - Multiple chip resistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decide the inside and outside of a resistor without fail by a method, wherein a multiple chip resistor is composed of a black color base inside and outside deciding insulating layer provided between a plurality of resistance layers, as well as a transmittable protective layer provided covering at least the resistance layers and the inside and outside deciding insulating layer. SOLUTION: A recess 12 and a projection 13 are provided on the opposite sides of a white color base insulating substrate 11 so as to form electrode layers 14. These electrode layers 14 are composed of three layers, i.e., an upper side electrode layer made of a mixed material, e.g. silver and glass, a nickel-plating layer 14b covering the upper side electrode layers 14a and a solder-plated layer 14c covering the nickel-plated layer 14b. A black color base resistance layers 15 partly and convolutionally connected to the upper side electrode layer 14a are formed, so as to form the other black color base inside and outside deciding insulating layer 16 between the resistance layers 15. Finally, a transmittable protective layer 17 covering the resistance layers 15 and the inside and outside deciding insulating layer 16 is formed, and then side electrodes 18 are formed on the sides of the insulating substrate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple chip resistor used for a high-density wiring circuit, for correcting a circuit operation by correcting a resistance value by laser trimming after mounting on the circuit, and for correcting a function. It is about a vessel.

[0002]

2. Description of the Related Art A conventional multiple chip resistor will be described below with reference to the drawings.

FIG. 6 is a perspective view of a conventional multiple chip resistor seen from above, and FIG. 7 is a sectional view taken along line XX of FIG.

In FIG. 1, reference numeral 1 denotes an insulating substrate made of 96% alumina or the like. Reference numeral 2 denotes a concave portion provided on the opposite side of the insulating substrate 1. Reference numeral 3 denotes a protrusion provided on the opposite side of the insulating substrate 1. Reference numeral 4 denotes an electrode layer provided on the projection 3. The electrode layer 4 is composed of three layers (not shown). The lowermost layer is an electrode layer made of a mixed material of silver and glass, the intermediate layer is a nickel plating layer, and the uppermost layer is a solder plating layer. Reference numeral 5 denotes a resistance layer formed of a mixed material of ruthenium oxide and glass or the like provided so as to be electrically connected to the opposing electrode layer 4. Reference numeral 6 denotes a permeable protective layer made of lead borosilicate glass or the like provided so as to cover at least the resistance layer 5.

[0005]

However, in the case of taping a multiple chip resistor, the conventional multiple chip resistor has a structure of two in spite of the fact that the front and back sensors are used to determine the front surface and the back surface and the package is used. Since only the transparent protective layer 6 is formed between the resistive layers 5 and that portion looks like the color (white) of the insulating substrate in appearance, when taping this multiple chip resistor, the front and back sensors are used. Had the problem of misidentifying the front and back.

In the structure of the conventional multiple chip resistor, only the protective layer 6 is formed between the two resistive layers 5 as shown in the sectional view of FIG. There is a problem that unevenness occurs in a portion where the protective layer 6 is formed thereon, and an adsorption error occurs when mounting a multiple chip resistor.

An object of the present invention is to solve the above-mentioned conventional problems by providing a multiple chip resistor in which the front and back surfaces of a resistor can be reliably determined by a front and back sensor and suction errors during mounting are less likely to occur. It is intended for.

[0008]

In order to achieve the above object, the present invention provides a black-based front / back determination insulating layer provided between a plurality of resistance layers, and at least the resistance layer and the front / back determination insulating layer. And a transmissive protective layer provided so as to cover it.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is provided with a plurality of electrode layers provided on a side portion of an insulating substrate so as to face each other, and provided so as to be electrically connected to the plurality of electrode layers. A plurality of resistance layers, a black-based front / back determination insulating layer provided between the plurality of resistance layers, and a transmissive protective layer provided so as to cover at least the resistance layer and the front / back determination insulating layer. It consists of

[0010] The invention described in claim 2 is the same as the claim 1.
The resistance layer described above and the insulating layer for front and back determination determine the front and back surfaces of the resistor.

[0011] The invention according to claim 3 is based on claim 1.
The described resistance layer and the insulating layer for front / back determination are of the same color system.

The invention described in claim 4 is the first invention.
The described resistance layer and the insulating layer for front / back determination have the same thickness.

According to this configuration, the front and back sensors of the resistor can be reliably determined by the front and back sensors, and the suction error at the time of mounting is eliminated.

(Embodiment 1) Hereinafter, a multiple chip resistor according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a perspective view of a multiple chip resistor according to a first embodiment of the present invention viewed from above, and FIG.
FIG. 3 is a cross-sectional view of FIG.

In FIG. 1, reference numeral 11 denotes a white insulating substrate made of 96% alumina, glass ceramic or the like. 12
Is a concave portion provided on the opposite side of the insulating substrate 11. Reference numeral 13 denotes a protrusion provided on the opposite side of the insulating substrate 11. Reference numeral 14 denotes an electrode layer provided on the projection 13.
The electrode layer 14 is composed of three layers, 14a is an upper electrode layer made of a mixed material of silver and glass or the like, 14b
Is a nickel plating layer provided to cover the upper electrode layer 14a, and 14c is a solder plating layer provided to cover the nickel plating layer 14b. 15 is an upper electrode layer 14a
And a black-based resistance layer made of a mixed material of ruthenium oxide and glass, which is provided so as to be partially overlapped with and electrically connected thereto. Reference numeral 16 denotes a black type front-back determination insulating layer made of a lead borosilicate glass or the like provided between the resistance layers 15. Reference numeral 17 denotes a permeable protection layer made of a lead borosilicate glass or the like provided so as to cover at least the resistance layer 15 and the insulating layer 16 for front / back determination. Reference numeral 18 denotes a side electrode layer made of a mixed material of silver and glass or the like provided on the side surface of the insulating substrate 11 so as to be electrically connected to at least the upper electrode layer 14a.

A method of manufacturing the multiple chip resistor having the above-described configuration will be described below with reference to the drawings.

FIGS. 4 and 5 are process diagrams showing a method for manufacturing a multiple chip resistor according to the first embodiment of the present invention.

First, as shown in FIG. 4A, 96% alumina having through holes 21 and vertical and horizontal dividing grooves 22 is formed.
White sheet-like substrate 23 made of glass ceramic or the like
Screen-printed and dried a mixed paste material of silver and glass so as to straddle the dividing groove 22 of the above, and fired at a temperature of about 850 ° C. in a belt-type continuous firing furnace at a temperature of about 850 ° C. for a profile of about 45 minutes. To form

Next, as shown in FIG. 4B, a mixed paste material of ruthenium oxide and glass is superposed on a part of the upper electrode layer 24 so as to electrically connect the upper electrode layers 24. Screen-printed and dried on the upper surface of the sheet-like substrate 23, and fired at a temperature of about 850 ° C. in a belt-type continuous firing furnace at a temperature of about 850 ° C. with a profile of about 45 minutes, and dried for about 1 hour.
A black resistive layer 25 having a thickness of 0 μm is formed.

Next, as shown in FIG.
In order to eliminate the white portion between 5 and to make the surface flat, a lead borosilicate glass paste containing a black pigment such as manganese oxide is screen-printed and dried, and is heated to about 600 ° C. by a belt-type continuous firing furnace. At a temperature of about 45 minutes with a profile of about 45 minutes,
A black-based front / back determination insulating layer 26 of the same color as 5 is formed.

Next, as shown in FIG. 5A, a lead borosilicate glass paste is screen-printed and dried so as to cover at least the upper surfaces of the resistance layer 25 and the insulating layer 26 for determining the front and back sides, and is subjected to belt-type continuous firing. Firing in a furnace at a temperature of about 600 ° C. with a profile of about 45 minutes to form a permeable protective layer 27. Here, since the resistance layer 25 and the front / back determination insulating layer 26 have the same thickness, the protective layer 27
Has a flat state without irregularities.

Next, as shown in FIG. 5B, division grooves (not shown in FIG. 5) of the sheet-like substrate (not shown in FIG. 5) so that the upper electrode layer 24 is exposed from the side surfaces. ) To form a strip-shaped substrate 28.

Next, as shown in FIG. 5C, a mixed paste material of silver and glass is roller-transfer-printed and dried so as to be electrically connected to the upper electrode layer 24, and the belt-type continuous firing furnace is used. At a temperature of about 600 ° C. with a profile of about 45 minutes to form the side electrode layer 29.

Next, as shown in FIG. 5D, the strip-shaped substrate 28 is divided along the division grooves 22 to form individual substrates 30.

Finally, the upper electrode layer 24 and the side electrode layer 29
A first plating layer (not shown) made of nickel plating or the like is formed so as to cover the first plating layer, and a second plating layer made of an alloy plating of tin and lead or the like is formed so as to cover the first plating layer. (Not shown)) to manufacture a multiple chip resistor.

The characteristics of the multiple chip resistor constructed and manufactured as described above will be described below in comparison with those of a conventional multiple chip resistor.

(Experimental Method 1) The front and back sensors of the automatic taping machine are used to judge the front and back of each of the multiple chip resistors, the multiple chip resistors of the present embodiment, and the conventional multiple chip resistors, and package them. .

(Pass / Fail Judgment 1) A multiple chip resistor packaged upside down is regarded as defective.

(Experimental Results 1) (Table 1) shows experimental results of the number of defective packaging of the multiple chip resistor according to the conventional and the present embodiment.

[0031]

[Table 1]

As is clear from Table 1, since the multiple chip resistor of the present invention is provided with an insulating layer for determining the front and back sides between the resistance layers, the front and back surfaces of the multiple chip resistor are surely detected by the front and back sensors. It can be confirmed that the judgment has been made.

(Experimental Method 2) The surface of each of the multiple chip resistors, the multiple chip resistors of the present embodiment, and the conventional multiple chip resistors of 10,000 is adsorbed by an automatic mounting machine.

(Mounting failure 2) A chip in which a suction error has occurred in a multiple chip resistor is determined to be defective.

(Experimental Results 2) Table 2 shows the experimental results of the number of defective mountings of the multiple chip resistor according to the prior art and the present invention.

[0036]

[Table 2]

As is clear from Table 2, since the multiple chip resistor of the present invention is provided with an insulating layer for determining the front and back sides between the resistance layers, the surface is flat and no suction error occurs during mounting. Can be confirmed.

Although the convex electrode type is used in the first embodiment, this does not limit the shape of the electrode.
The same effect can be obtained by using the concave electrode type.

Further, in the first embodiment, the two-element type is used, but this does not limit the number of elements.
Similar effects can be obtained by using an element type or more.

[0040]

As described above, according to the present invention, since the black-type front / back determination insulating layer is provided between the resistance layers, the front / back sensor of the multiple chip resistor can be reliably determined by the front / back sensor. Since the thickness of the insulating layer for determining the front and back sides is the same, the surface of the protective layer becomes flat, so that a multiple chip resistor excellent in mountability can be provided.

[Brief description of the drawings]

FIG. 1 is a perspective view of a multiple chip resistor according to a first embodiment of the present invention as seen from above.

FIG. 2 is a sectional view taken along line XX of FIG.

FIG. 3 is a sectional view taken along the line YY of FIG.

FIG. 4 is a process chart showing the manufacturing method.

FIG. 5 is a process chart showing the manufacturing method.

FIG. 6 is a perspective view of the conventional multiple chip resistor seen from above.

FIG. 7 is a sectional view taken along line XX of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Insulating substrate 14 Electrode layer 15 Resistance layer 16 Insulating layer for front / back determination 17 Protective layer

Claims (4)

[Claims] A plurality of electrode layers provided on a side of the insulating substrate so as to face each other; a plurality of resistance layers provided so as to be electrically connected to the plurality of electrode layers; and a plurality of resistance layers provided between the plurality of resistance layers. A multi-chip resistor comprising: a black-based front / back determination insulating layer; and a transparent protective layer provided so as to cover at least the resistance layer and the front / back determination insulating layer. 2. The multiple chip resistor according to claim 1, wherein the front and back surfaces of the multiple chip resistor are determined by the resistance layer and the front / back determination insulating layer. 3. The multiple chip resistor according to claim 1, wherein the resistance layer and the front / back determination insulating layer are of the same color system. 4. The multiple chip resistor according to claim 1, wherein the resistance layer and the front / back determination insulating layer have the same thickness.