JPH05226108A - Rectangular chip resistor and its manufacture - Google Patents

Rectangular chip resistor and its manufacture

Info

Publication number
JPH05226108A
JPH05226108A JP4199374A JP19937492A JPH05226108A JP H05226108 A JPH05226108 A JP H05226108A JP 4199374 A JP4199374 A JP 4199374A JP 19937492 A JP19937492 A JP 19937492A JP H05226108 A JPH05226108 A JP H05226108A
Authority
JP
Japan
Prior art keywords
layer
chip resistor
surface electrode
electrode layers
electrode layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4199374A
Other languages
Japanese (ja)
Other versions
JP3116579B2 (en
Inventor
Masato Hashimoto
正人 橋本
Takaaki Shirai
卓見 白井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP04199374A priority Critical patent/JP3116579B2/en
Publication of JPH05226108A publication Critical patent/JPH05226108A/en
Application granted granted Critical
Publication of JP3116579B2 publication Critical patent/JP3116579B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Non-Adjustable Resistors (AREA)

Abstract

PURPOSE:To contrive to surely mount a chip resistor on a printed board by suppressing the inclination of the resistor in longitudinal and transverse directions through providing parts, in which the height of an electrode is made higher than a protective layer, in four corners of the top-face part of the chip resistor. CONSTITUTION:After top-face electrode layers 2 are formed on the surface of 96 alumina substrate 1 by the use of a thick-film silver paste, a thick-film resistive paste mainly composed of RuO2 is used in the manner of overlapping with a part of the top-face electrode layer 2 so that a resistive layer 4 is formed. Then, after an overcoat glass layer 6 is formed in the manner of completely covering the resistive layer 4, the thick-film silver paste is used in the manner of overlapping with a part of the top-face electrode layer 2 so that two pairs of top-face electrode layers 5 are formed. Subsequently, the alumina substrate 1 is divided into strips and the thick-film silver paste is used in the manner of overlapping with parts of the top-face electrode layers 2, 5 so that end-face electrode layers 3 are formed in the side of the strip-shaped alumina substrate. After that, the secondary-substrate division of the strip-shaped alumina substrate is performed so that Ni plating layer and Sn-Pb plating layer are formed in the electrode layers 2, 3, 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高密度配線回路に用いら
れる角形チップ抵抗器およびその製造方法に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rectangular chip resistor used in a high density wiring circuit and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年、電子機器の軽薄短小化に対する要
求がますます増大していく中、回路基板の配線密度を高
めるため、抵抗素子には非常に小型な抵抗器が多く用い
られるようになってきた。また、近年の高密度実装にお
いて従来からの、ワンバイワンの実装機に加え更に実装
速度の速い一括実装機も多く用いられるようになってき
ている。
2. Description of the Related Art In recent years, with the ever-increasing demand for smaller, lighter, smaller electronic devices, in order to increase the wiring density of circuit boards, very small resistors have become widely used as resistive elements. Came. In addition, in recent years, in addition to the conventional one-by-one mounting machine, a collective mounting machine having a higher mounting speed has been widely used in high-density mounting.

【0003】従来の厚膜タイプの角形チップ抵抗器の構
造の一例を、図3(a),(b),(c)に示す。図3
(a)は上視図、(b)は図3(a)のA−A′間の断
面図、(c)は図3(a)のB−B′間の断面図であ
る。
An example of the structure of a conventional thick film type rectangular chip resistor is shown in FIGS. 3 (a), 3 (b) and 3 (c). Figure 3
3A is a top view, FIG. 3B is a sectional view taken along the line AA ′ in FIG. 3A, and FIG. 3C is a sectional view taken along the line BB ′ in FIG.

【0004】従来の角形チップ抵抗器は96アルミナ基
板10上に形成された一対の厚膜電極による上面電極層
11と前記上面電極層11と接続するように形成された
ルテニウム系厚膜抵抗による抵抗層12と、抵抗層を覆
うガラス層14、上面電極層の一部と重なる端面電極層
13とからなっている。なお、露出電極面には半田付け
性を確保するためにNiめっき層と半田めっき層を電解
メッキにより形成している。しかし、この角形チップ抵
抗器は上面電極層とガラス層の段差が約50μm程度あ
る。
The conventional rectangular chip resistor is a resistor formed by a pair of thick film electrodes formed on a 96 alumina substrate 10 and a ruthenium-based thick film resistor formed so as to be connected to the upper electrode layer 11. It comprises a layer 12, a glass layer 14 covering the resistance layer, and an end face electrode layer 13 overlapping a part of the upper face electrode layer. A Ni plating layer and a solder plating layer are formed on the exposed electrode surface by electrolytic plating to ensure solderability. However, this prismatic chip resistor has a step difference of about 50 μm between the upper electrode layer and the glass layer.

【0005】[0005]

【発明が解決しようとする課題】また、このチップ抵抗
器を一括実装機にてプリント基板に自動実装した場合に
チップ抵抗器の表面側(ガラス面側)がプリント基板に
接するように実装される場合も50%程度の確率で発生
するが、この時ランドパターンとチップ抵抗器にズレが
発生した場合、図4(a),(b)に示す如く、縦方向
および横方向にチップ抵抗器が傾き、最悪の場合片側端
子のみしか半田付けされない場合も生じるといった課題
を有していた。
Further, when this chip resistor is automatically mounted on a printed circuit board by a collective mounting machine, the chip resistor is mounted so that the front surface side (glass surface side) of the chip resistor is in contact with the printed circuit board. In this case, the probability of occurrence is about 50%. However, if the land pattern and the chip resistor are misaligned at this time, the chip resistor is vertically and horizontally displaced as shown in FIGS. 4 (a) and 4 (b). There is a problem that the tilt occurs, and in the worst case, only one terminal is soldered.

【0006】本発明は、このような課題を解決するもの
で、チップ抵抗器が裏向きに実装されたときにでもチッ
プ抵抗器の傾きを抑え、確実にプリント基板に実装させ
ることを目的とする。
The present invention solves such a problem, and an object of the present invention is to suppress the inclination of the chip resistor even when the chip resistor is mounted face down, and to surely mount the chip resistor on the printed circuit board. ..

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、絶縁性の基板上に形成された1対の第1上面電極層
と、この第1上面電極層の一部に重なる抵抗層と、前記
第1上面電極層に接続する基板端面に形成された1対の
端面電極層と、抵抗層を完全に覆う保護層とを備え、前
記第1上面電極層の一部に重なるように形成された2対
の第2上面電極層はその上面が保護層の上面よりも突出
していることを特徴とするものである。
In order to achieve the above object, a pair of first upper surface electrode layers formed on an insulative substrate, and a resistance layer overlapping a part of the first upper surface electrode layers. A pair of end face electrode layers formed on the end faces of the substrate connected to the first top face electrode layer, and a protective layer that completely covers the resistance layer, and formed so as to partially overlap the first top face electrode layer. The two pairs of second upper surface electrode layers thus formed are characterized in that the upper surfaces thereof project beyond the upper surface of the protective layer.

【0008】[0008]

【作用】本発明によれば、チップ抵抗器の上面部分に電
極の高さを保護層より高くした部分を四隅に設けること
により、チップ抵抗器が裏向きに実装された場合でも縦
方向・横方向のチップ抵抗器の傾きを抑えることにより
確実にプリント基板に実装されるものである。
According to the present invention, by providing the upper portion of the chip resistor with the electrode height higher than that of the protective layer at the four corners, even when the chip resistor is mounted face down, By suppressing the inclination of the chip resistor in the direction, the chip resistor is surely mounted on the printed circuit board.

【0009】[0009]

【実施例】以下、本発明の一実施例の角形チップ抵抗器
およびその製造方法について、図面を用いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A rectangular chip resistor according to an embodiment of the present invention and a method of manufacturing the same will be described below with reference to the drawings.

【0010】図1(a)は本発明の実施例を示す上視図
であり、図1(b)は図1(a)のA−A′間断面図、
図1(c)は図1(a)のB−B′間断面図である。
FIG. 1A is a top view showing an embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA 'in FIG.
FIG. 1C is a cross-sectional view taken along the line BB ′ of FIG.

【0011】図1(a),(b),(c)において、本
発明の角形チップ抵抗器は、96アルミナ基板1と、前
記96アルミナ基板1上の銀系厚膜の1対の第1上面電
極層2と、前記第1上面電極層2の一部に重なるルテニ
ウム系厚膜の抵抗層4と、前記抵抗層4を完全に覆うガ
ラス層6と、前記第1上面電極層2上に形成され、角形
チップ抵抗器の四隅に配置された2対の第2上面電極層
5、前記第1上面電極層2および前記第2上面電極層5
の一部に重なる銀系厚膜の端面電極層3より構成され
る。なお、露出電極面には半田付け性を向上させるため
に、Niめっき層とSn−Pbめっき層を電解めっきに
より施している。ここで上面電極部分の高さはガラス部
分の高さより高くなるように構成され、チップ抵抗器が
裏向きに実装された場合でも縦方向・横方向のチップ抵
抗器の傾きを抑えることができる。
1 (a), 1 (b) and 1 (c), a rectangular chip resistor according to the present invention comprises a 96 alumina substrate 1 and a pair of first silver-based thick films on the 96 alumina substrate 1. A top surface electrode layer 2, a ruthenium-based thick film resistance layer 4 overlapping a portion of the first top surface electrode layer 2, a glass layer 6 that completely covers the resistance layer 4, and a top surface of the first top surface electrode layer 2. Two pairs of the second upper surface electrode layer 5, the first upper surface electrode layer 2, and the second upper surface electrode layer 5 that are formed and are arranged at the four corners of the rectangular chip resistor.
Of the end face electrode layer 3 made of a silver-based thick film that partially overlaps with. The exposed electrode surface is electrolytically plated with a Ni plating layer and a Sn-Pb plating layer in order to improve solderability. Here, the height of the upper surface electrode portion is configured to be higher than the height of the glass portion, and even when the chip resistor is mounted face down, inclination of the chip resistor in the vertical and horizontal directions can be suppressed.

【0012】次に、図1に示した本発明の実施例1の製
造方法について説明する。まず、耐熱性および絶縁性に
優れた96アルミナ基板1を受け入れる。このアルミナ
基板1には短冊状、および個片状に分割するために、分
割するための溝(グリーンシート時に金型成形)が形成
されている。次に、前記96アルミナ基板1の表面に厚
膜銀ペーストをスクリーン印刷・乾燥し、ベルト式連続
焼成炉によって850℃の温度で、ピーク時間6分,I
N−OUT45分のプロファイルによって焼成し第1上
面電極層2を形成した。次に、第1上面電極層2の一部
に重なるように、RuO2を主成分とする厚膜抵抗ペー
ストをスクリーン印刷し、ベルト式連続焼成炉により8
50℃の温度でピーク時間6分,IN−OUT45分の
プロファイルによって焼成し、抵抗層4を形成した。次
に、前記第1上面電極層2間の前記抵抗層4の抵抗値を
揃えるために、レーザー光によって、前記抵抗層4の一
部を破壊し抵抗値修正(Lカット,100mm/秒,12
KHZ,5W)を行った。続いて、前記抵抗層4を完全に
覆うように、ホウケイ酸鉛系ガラスペーストをスクリー
ン印刷し、ベルト式連続焼成炉によって590℃の温度
で、ピーク時間6分、IN−OUT50分の焼成プロフ
ァイルによって焼成し、オーバーコートガラス層6を形
成した。次に、前記上面電極層2の一部に重なるように
厚膜銀ペーストをスクリーン印刷・乾燥し、ベルト式連
続焼成炉によって600℃の温度で、ピーク時間6分,
IN−OUT45分のプロファイルによって焼成し2対
の第2上面電極層5を形成した。次に、端面電極を形成
するための準備工程として、端面電極を露出させるため
に、アルミナ基板1を短冊状に分割し、短冊状アルミナ
基板を得た。前記短冊状アルミナ基板の側面に、前記第
1上面電極層2および第2上面電極層5の一部に重なる
ように厚膜銀ペーストをローラーによって塗布し、ベル
ト式連続焼成炉によって600℃の温度で、ピーク時間
6分,IN−OUT45分の焼成プロファイルによって
焼成し端面電極層3を形成した。次に、電極メッキの準
備工程として、前記端面電極層3を形成済みの短冊状ア
ルミナ基板を個片状に分割する二次基板分割を行い、個
片状アルミナ基板を得た。そして最後に、露出している
第1上面電極層2と第2上面電極層5と端面電極層3の
半田付け時の電極喰われの防止および半田付けの信頼性
の確保のため、電解めっきによってNiめっき層とSn
−Pbのめっき層を形成した。
Next, a manufacturing method of the first embodiment of the present invention shown in FIG. 1 will be described. First, the 96 alumina substrate 1 having excellent heat resistance and insulating properties is received. In order to divide the alumina substrate 1 into strips and individual pieces, grooves for division (molding at the time of green sheet) are formed. Next, a thick film silver paste was screen-printed on the surface of the 96 alumina substrate 1 and dried, and a belt type continuous firing furnace was used at a temperature of 850 ° C. for a peak time of 6 minutes, I.
The first upper surface electrode layer 2 was formed by firing according to the profile of N-OUT 45 minutes. Next, a thick film resistance paste containing RuO 2 as a main component is screen-printed so as to overlap a part of the first upper surface electrode layer 2, and the thick film resistance paste is formed by a belt-type continuous firing furnace.
The resistance layer 4 was formed by firing at a temperature of 50 ° C. according to a profile with a peak time of 6 minutes and IN-OUT 45 minutes. Next, in order to make the resistance value of the resistance layer 4 between the first upper surface electrode layers 2 uniform, a part of the resistance layer 4 is destroyed by laser light to correct the resistance value (L cut, 100 mm / sec, 12
KHZ, 5W). Subsequently, a lead borosilicate glass paste was screen-printed so as to completely cover the resistance layer 4, and a belt-type continuous firing furnace was used to perform a firing profile at a temperature of 590 ° C. for a peak time of 6 minutes and IN-OUT 50 minutes. Firing was performed to form the overcoat glass layer 6. Next, a thick film silver paste is screen-printed and dried so as to overlap a part of the upper electrode layer 2, and the temperature is set to 600 ° C. in a belt-type continuous firing furnace for a peak time of 6 minutes.
Two pairs of second upper surface electrode layers 5 were formed by firing according to the profile of IN-OUT 45 minutes. Next, as a preparatory step for forming the end face electrodes, the alumina substrate 1 was divided into strips to expose the end face electrodes to obtain strip-shaped alumina substrates. A thick film silver paste is applied to the side surface of the strip-shaped alumina substrate by a roller so as to partially overlap the first upper surface electrode layer 2 and the second upper surface electrode layer 5, and the temperature is set to 600 ° C. by a belt-type continuous firing furnace. Then, the end face electrode layer 3 was formed by firing according to a firing profile with a peak time of 6 minutes and IN-OUT 45 minutes. Next, as a preparatory step for electrode plating, the strip-shaped alumina substrate on which the end face electrode layer 3 had been formed was divided into individual secondary substrates to obtain individual alumina substrates. Finally, in order to prevent electrode erosion during soldering of the exposed first upper surface electrode layer 2, second upper surface electrode layer 5, and end surface electrode layer 3 and to secure reliability of soldering, electrolytic plating is performed. Ni plating layer and Sn
-Pb plating layer was formed.

【0013】以上の工程により、本発明の実施例による
角形チップ抵抗器を試作した。この本発明の実施例によ
る角形チップ抵抗器をランドパターン上に裏向きに実装
した状態を図2(a),(b)に示す。チップ抵抗器の
傾きが小さく確実にプリント基板に半田付けされてお
り、本発明の効果が表れていることが分かる。
Through the above steps, a rectangular chip resistor according to an embodiment of the present invention was prototyped. 2 (a) and 2 (b) show a state in which the rectangular chip resistor according to the embodiment of the present invention is mounted on the land pattern in a face down manner. It can be seen that the chip resistor has a small inclination and is reliably soldered to the printed circuit board, and the effect of the present invention is exhibited.

【0014】また、更に、第2上面電極層5の一方の対
と他方の対の間隔を実装機の吸着ノズル7の外径より小
さくすることにより、図2(c)に示すように、実装機
の吸着ノズル7が直接オーバーコートガラス層6に当た
ることが無くなり、実装時のガラスカケ不良も大幅に軽
減できる。
Further, by making the distance between one pair and the other pair of the second upper surface electrode layers 5 smaller than the outer diameter of the suction nozzle 7 of the mounting machine, as shown in FIG. The suction nozzle 7 of the machine does not directly hit the overcoat glass layer 6, and defective glass chips during mounting can be greatly reduced.

【0015】なお、実施例において第2上面電極層5は
ガラス層6形成後に、600℃の温度で焼成し形成した
が、これは580℃〜640℃の範囲の温度で焼成して
もよい(580℃以下では電極強度が劣化し、640℃
以上では抵抗特性が劣化する)。
In the embodiment, the second upper electrode layer 5 is formed by firing at a temperature of 600 ° C. after forming the glass layer 6, but it may be fired at a temperature in the range of 580 ° C. to 640 ° C. ( The electrode strength deteriorates at 580 ° C or lower to 640 ° C.
With the above, the resistance characteristics deteriorate).

【0016】[0016]

【発明の効果】以上の説明より明らかなように、本発明
の角形チップ抵抗器によれば、チップ抵抗器の上面部分
の四隅に電極の高さを保護層より高くした第2上面電極
層を設けることにより、チップ抵抗器が裏向きに実装さ
れた場合でも縦方向・横方向のチップ抵抗器の傾きを抑
えることにより確実にプリント基板に実装されるという
効果が得られる。
As is apparent from the above description, according to the rectangular chip resistor of the present invention, the second upper surface electrode layer in which the height of the electrode is higher than that of the protective layer is provided at the four corners of the upper surface portion of the chip resistor. By providing the chip resistor, even if the chip resistor is mounted face down, it is possible to obtain the effect that the chip resistor can be reliably mounted on the printed circuit board by suppressing the inclination of the chip resistor in the vertical and horizontal directions.

【0017】また、更に、上面電極層の一方の対と他方
の対の間隔を実装機の吸着ノズルの外径より小さくする
ことにより、実装機の吸着ノズルが直接オーバーコート
ガラス層に当たることが無くなり、実装時のガラスカケ
不良も大幅に軽減できる。
Further, by making the distance between one pair and the other pair of the upper surface electrode layers smaller than the outer diameter of the suction nozzle of the mounting machine, the suction nozzle of the mounting machine does not directly contact the overcoat glass layer. , Glass chip defects during mounting can be greatly reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)は本発明の一実施例の角形チップ抵抗器
の構造を示す上面図 (b)は同断面図 (c)は同断面図
1A is a top view showing the structure of a rectangular chip resistor according to an embodiment of the present invention, FIG. 1B is the same sectional view, and FIG. 1C is the same sectional view.

【図2】(a)は同角形チップ抵抗器がランドパターン
に裏向きに実装された状態を示す横方向からみた説明図 (b)は同角形チップ抵抗器がランドパターンに裏向き
に実装された状態を示す縦方向からみた説明図 (c)は同角形チップ抵抗器が実装機の吸着ノズルに吸
着された状態を示す説明図
FIG. 2 (a) is a side view showing a state where the equilateral chip resistors are mounted on the land pattern face down, and FIG. 2 (b) is a side view showing the equilateral chip resistors mounted on the land pattern face down. (C) is an explanatory view showing a state in which the equilateral rectangular chip resistor is adsorbed by the adsorption nozzle of the mounting machine.

【図3】(a)は従来の角形チップ抵抗器の構造を示す
上面図 (b)は同断面図 (c)は同断面図
3A is a top view showing the structure of a conventional rectangular chip resistor, FIG. 3B is the same sectional view, and FIG. 3C is the same sectional view.

【図4】(a)は従来の角形チップ抵抗器がランドパタ
ーンに裏向きに実装された状態を示す横方向からみた説
明図 (b)は従来の角形チップ抵抗器がランドパターンに裏
向きに実装された状態を示す縦方向からみた説明図
FIG. 4 (a) is a lateral view showing a state where a conventional rectangular chip resistor is mounted on a land pattern face down. FIG. 4 (b) is a conventional rectangular chip resistor faced on the land pattern face down. Explanatory view seen from the vertical direction showing the mounted state

【符号の説明】[Explanation of symbols]

1 96アルミナ基板 2 第1上面電極層 3 端面電極層 4 抵抗層 5 第2上面電極層 6 オーバーコートガラス層 7 吸着ノズル 1 96 Alumina substrate 2 1st upper surface electrode layer 3 end surface electrode layer 4 resistance layer 5 2nd upper surface electrode layer 6 overcoat glass layer 7 adsorption nozzle

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】絶縁性の基板上に形成された1対の第1上
面電極層と、この第1上面電極層の一部に重なる抵抗層
と、前記第1上面電極層に接続する基板端面に形成され
た1対の端面電極層と、抵抗層を完全に覆う保護層とを
備え、前記第1上面電極層の一部に重なるように形成さ
れた2対の第2上面電極層はその上面が保護層の上面よ
りも突出していることを特徴とする角形チップ抵抗器。
1. A pair of first upper surface electrode layers formed on an insulative substrate, a resistance layer overlapping a part of the first upper surface electrode layer, and a substrate end surface connected to the first upper surface electrode layer. The pair of end surface electrode layers formed on the first surface electrode layer and the protective layer that completely covers the resistance layer, and the pair of second upper surface electrode layers formed so as to partially overlap the first upper surface electrode layer are A rectangular chip resistor having an upper surface protruding more than the upper surface of the protective layer.
【請求項2】第2上面電極層はガラス層形成後に、58
0℃〜640℃の焼成温度で形成することを特徴とする
請求項1記載の角形チップ抵抗器の製造方法。
2. The second upper surface electrode layer is formed of a glass layer 58 after formation of the glass layer.
The method for manufacturing a rectangular chip resistor according to claim 1, wherein the film is formed at a firing temperature of 0 ° C to 640 ° C.
【請求項3】第2上面電極層の一方の対と他方の対の間
隔は実装機の吸着ノズルの外径より小さいことを特徴と
する請求項1記載の角形チップ抵抗器。
3. The rectangular chip resistor according to claim 1, wherein a distance between one pair and the other pair of the second upper surface electrode layers is smaller than an outer diameter of the suction nozzle of the mounting machine.
JP04199374A 1991-07-29 1992-07-27 Square chip resistor and method of manufacturing the same Expired - Fee Related JP3116579B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04199374A JP3116579B2 (en) 1991-07-29 1992-07-27 Square chip resistor and method of manufacturing the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3-188622 1991-07-29
JP18862291 1991-07-29
JP04199374A JP3116579B2 (en) 1991-07-29 1992-07-27 Square chip resistor and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH05226108A true JPH05226108A (en) 1993-09-03
JP3116579B2 JP3116579B2 (en) 2000-12-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0795878A3 (en) * 1996-03-13 1998-05-27 Kamaya Electric Co., Ltd. Chip resistor
CN112309660A (en) * 2020-09-25 2021-02-02 华东光电集成器件研究所 Preparation method of thick film hybrid circuit substrate side resistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0795878A3 (en) * 1996-03-13 1998-05-27 Kamaya Electric Co., Ltd. Chip resistor
CN112309660A (en) * 2020-09-25 2021-02-02 华东光电集成器件研究所 Preparation method of thick film hybrid circuit substrate side resistor

Also Published As

Publication number Publication date
JP3116579B2 (en) 2000-12-11

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