JPH11162969A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH11162969A
JPH11162969A JP32808097A JP32808097A JPH11162969A JP H11162969 A JPH11162969 A JP H11162969A JP 32808097 A JP32808097 A JP 32808097A JP 32808097 A JP32808097 A JP 32808097A JP H11162969 A JPH11162969 A JP H11162969A
Authority
JP
Japan
Prior art keywords
sog
film
gas
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP32808097A
Other languages
Japanese (ja)
Inventor
Masanori Yasuhara
正典 安原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP32808097A priority Critical patent/JPH11162969A/en
Publication of JPH11162969A publication Critical patent/JPH11162969A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Formation Of Insulating Films (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve adhesiveness between lower SOG and upper SOG in a process for applying multiple SOG film layers. SOLUTION: A wiring film is sputtered and patterned and wiring layers 103 and formed on a semiconductor substrate. Then, a CVD oxide film layer 102 whose film thickness is about 5000 Å is formed on the whole face. Then, an SOG film 104 of the lower layer is formed and a surface is prcessed by plasma 106 using Ar gas as inert gas which does not positively react to Si-OR and Si-H in the SOG film. Then, the SOG film 105 of the upper layer is formed. Consequently, danger of deterioration of the SOG film owing to crack (micro crack) of the SOG film and peeling-off is eliminated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置のSO
G塗布工程と、SOG層が露出した状態での表面処理方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SO
The present invention relates to a G application step and a surface treatment method in a state where an SOG layer is exposed.

【0002】[0002]

【従来の技術】従来の技術では、半導体装置の微細化及
び高集積化に伴い、種種の平坦化技術が行われている。
その一つとして、SOGを塗布する平坦化方法が挙げら
れる。この様な平坦化法は一般的に以下に示すような工
程により実施されている。
2. Description of the Related Art In the prior art, various flattening techniques have been used in accordance with miniaturization and high integration of semiconductor devices.
As one of them, there is a flattening method of applying SOG. Such a flattening method is generally performed by the following steps.

【0003】まず、所望の半導体装置基板上に下層配線
を形成した後に、第1のCVD酸化膜層を形成する。次
にSOGを1から複数回にわたって塗布をする事で所望
の平坦化膜層を形成した後、第2のCVD酸化膜層の形
成を行い、下層配線上に平坦化された層間絶縁膜を形成
している。その場合、下層SOG塗布層と上層SOG塗
布層の密着性を上げるために下層SOG塗布(SOGの
塗布と塗布直後のベークが連続して行う)と上層SOG
塗布の間に表面処理としてOプラズマ処理、O処理
若しくは、350℃以上のアニール処理等を実施してい
た。しかしOプラズマや、O処理の場合、SOG表
面にある有機成分だけでなくSOG膜中に残留している
有機成分(Si−OR、Si−H,Si−CH等)と
、Oが反応して昇華される為にSOG膜が分解さ
れ膜質の劣化を引き起こす。また、アニール処理の場合
は、未反応な、Si−OR、Si−CH等が表面に残
留し易く、上層SOG塗布層や、第2のCVD酸化膜層
との密着性不良の原因となっていた。
First, after a lower wiring is formed on a desired semiconductor device substrate, a first CVD oxide film layer is formed. Next, a desired planarizing film layer is formed by applying SOG one or more times, and then a second CVD oxide film layer is formed to form a planarized interlayer insulating film on the lower wiring. doing. In this case, in order to increase the adhesion between the lower SOG coating layer and the upper SOG coating layer, the lower SOG coating (the application of SOG and the baking immediately after the coating are continuously performed) and the upper SOG coating are performed.
O 2 plasma treatment, O 3 treatment, annealing at 350 ° C. or more, or the like was performed as a surface treatment during coating. However, in the case of O 2 plasma or O 3 treatment, not only the organic components on the SOG surface but also the organic components (Si—OR, Si—H, Si—CH 3, etc.) remaining in the SOG film and O 2 , O 3 is the SOG film to be sublimated by reaction causing deterioration of the film quality is degraded. In the case of annealing, unreacted, Si-OR, easily remaining Si-CH 3 and the like surface, turned and upper SOG applied layer, causing poor adhesion to the second CVD oxide film layer I was

【0004】さらに、この様な状態のまま形成された多
層構造の層間絶縁膜は、後の配線層形成時の膜ストレス
や、半導体基板の保護膜層形成による膜ストレスで、下
層SOG膜層と上層SOG膜層の間での剥がれやSOG
層と第2のCVD酸化膜層との密着不良による、マイク
ロクラックを発生させるという問題があった。
Further, the interlayer insulating film having a multi-layer structure formed in such a state is not affected by the film stress at the time of forming a wiring layer later or the film stress due to the formation of a protective film layer of a semiconductor substrate. Peeling or SOG between upper SOG film layers
There was a problem that microcracks were generated due to poor adhesion between the layer and the second CVD oxide film layer.

【0005】[0005]

【発明が解決しようとする課題】本発明は、この様な課
題を解決するために、下層のSOG膜層の膜質劣化を与
える事の無い表面処理を行うことで、SOGを複数回塗
布可能な、下層のSOG膜層と上層のSOG膜層及び、
SOGによる平坦化層形成後に形成する絶縁膜層との密
着性を向上することが可能な半導体装置の製造方法を提
供することを目的とする。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is capable of applying SOG a plurality of times by performing a surface treatment without deteriorating the film quality of an underlying SOG film layer. A lower SOG film layer and an upper SOG film layer,
It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of improving adhesion to an insulating film layer formed after formation of a planarization layer by SOG.

【0006】[0006]

【課題を解決するための手段】本発明は、前述の従来技
術に於ける下層SOG膜層を劣化させる事無くSOGを
複数回塗布するために、下層SOG塗布と上層SOG塗
布の間にプラズマ照射による表面処理を行う事を特徴と
する半導体装置の製造方法を提供するものである。
SUMMARY OF THE INVENTION The present invention provides a method of applying a plasma between a lower SOG coating and an upper SOG coating in order to apply SOG a plurality of times without deteriorating the lower SOG film layer in the prior art. And a method for manufacturing a semiconductor device characterized by performing a surface treatment by the method.

【0007】また、請求項2の記載の発明は、アルゴン
ガス、クリプトンガス、ネオンガス、キセノンガス、窒
素ガス、ヘリウムガスからなる群から選択される少なく
とも一種類のガスを含む反応ガスを用いて行うことを特
徴とする請求項1記載の半導体装置の製造方法を提供す
るものである。
The invention according to claim 2 is performed using a reaction gas containing at least one kind of gas selected from the group consisting of argon gas, krypton gas, neon gas, xenon gas, nitrogen gas, and helium gas. A method of manufacturing a semiconductor device according to claim 1 is provided.

【0008】[0008]

【作用】以上説明した本発明の製造方法によれば、SO
Gの塗布工程において下層SOG膜の塗布後前記ガスに
よるプラズマ照射による表面処理を実施する事で、下層
SOG膜中に残留する有機成分のSi−OR、Si−
H,Si−CH等に影響を与えること無く下層SOG
膜層の表面にあるSi−OR、Si−H,Si−CH
を分解するため下層SOG膜層と上層SOG膜層の密着
性が確保可能である。
According to the manufacturing method of the present invention described above, the SO
By performing surface treatment by plasma irradiation with the gas after the application of the lower SOG film in the G application process, Si-OR and Si- of organic components remaining in the lower SOG film are applied.
H, Si—CH 3 etc. without affecting lower layer SOG
Si-OR on the surface of the membrane layer, Si-H, Si-CH 3
Therefore, the adhesion between the lower SOG film layer and the upper SOG film layer can be ensured.

【0009】また、請求項2に係る半導体装置の製造方
法によれば、アルゴンガス、クリプトンガス、ネオンガ
ス、キセノンガス、窒素ガス、ヘリウムガスからなる群
から選択される少なくとも一種類のガスを含む反応ガス
を用いて前記プラズマ照射行うことで、さらに下層SO
G膜中に残留する有機成分のSi−OR、Si−H,S
i−CH等に影響を与えること無く下層SOG膜層の
表面にあるSi−OR、Si−H,Si−CHを分解
するため、効率よく上層SOG膜層や第2のCVD酸化
膜層との密着性の向上が得られる。
According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a reaction including at least one gas selected from the group consisting of argon gas, krypton gas, neon gas, xenon gas, nitrogen gas, and helium gas. By performing the plasma irradiation using a gas, the lower layer SO
Organic components Si-OR, Si-H, S remaining in the G film
Si-OR in no surface of the lower SOG layer to affect the i-CH 3 and the like, Si-H, in order to decompose the Si-CH 3, efficiently upper SOG layer and the second CVD oxide film layer And an improvement in the adhesion to the substrate.

【0010】[0010]

【発明の実施の形態】本発明に係る実施例について、図
面に基づき説明をする。図1は、本発明に係る半導体装
置の製造工程の一部を示す断面図である。図1(1)に
示す工程では、所望の処理が行われた半導体基板101
上に、配線膜をスパッタし、これをパターニングして配
線層103を形成する。続いて、全面に膜厚が5000
Å程度のCVD酸化膜層102を形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the present invention. In the step shown in FIG. 1A, the semiconductor substrate 101 on which desired processing has been performed is performed.
On top, a wiring film is sputtered and patterned to form a wiring layer 103. Subsequently, the film thickness is 5000 on the entire surface.
A CVD oxide film layer 102 of about Å is formed.

【0011】図1(2)に示す工程では、図1(1)に
示す工程で形成したCVD酸化膜102上に,SOGを
回転塗布した後、80℃から250℃の熱処理を行うこ
とでSOG膜層を形成する。SOGの塗布による平坦化
は、SOGの耐クラック性(以下、無機系SOGの場合
クラック限界が1500Å程度であるのに対し、有機系
SOGは、2500Åと材質により様々な値を示す。)
の膜厚を1回から複数回塗布することで所定の平坦性を
確保している。特に、複数回SOGの塗布を行うことに
より所望の平坦性を得る場合、下層のSOG膜104と
上層のSOG膜105の間に表面処理を行わない場合
は、下層のSOG膜104膜表面にSi−OR基や、S
i−H基、Si−CHがあるため、下層のSOG膜1
04と上層のSOG膜105の密着性が確保されず、S
OGの塗布が不能になったり、仮に塗布が出来ても塗布
後のベーク処理(SOG膜を400℃以上の熱で重合を
促進し絶縁膜としての膜質を確保する作業)時に、膜が
剥がれたり、割れてしまうので、表面処理としてO
ラズマ処理や、O処理を行い、下層SOG104表面
にあるSi−OR基や、Si−H基を分解しSi−O基
等に安定化させることで上層に塗布するSOGの密着性
を確保していた。
In the step shown in FIG. 1B, SOG is spin-coated on the CVD oxide film 102 formed in the step shown in FIG. Form a film layer. The flattening by SOG coating is the crack resistance of SOG (hereinafter, the crack limit is about 1500 ° in the case of inorganic SOG, and 2500 ° in the case of organic SOG, which shows various values depending on the material).
A predetermined flatness is ensured by applying the film thickness from once to a plurality of times. In particular, when a desired flatness is obtained by applying SOG a plurality of times, and when the surface treatment is not performed between the lower SOG film 104 and the upper SOG film 105, the surface of the lower SOG film 104 is coated with Si. -OR group or S
Since there is an i-H group and Si-CH 3 , the underlying SOG film 1
04 and the SOG film 105 of the upper layer are not secured.
OG coating becomes impossible, or even if coating can be performed, the film may be peeled off during baking after application (work to promote polymerization of the SOG film with heat of 400 ° C. or more to secure film quality as an insulating film). O 2 plasma treatment or O 3 treatment is performed as a surface treatment to decompose the Si—OR group or Si—H group on the surface of the lower layer SOG 104 and stabilize it into a Si—O group or the like. The adhesion of the SOG applied to the upper layer was ensured.

【0012】しかし、この方法の場合、下層となるSO
G膜104の最表面だけの反応に留まらず膜中に進入し
たOラジカルや、Oが上記分解、昇華反応を起こす
ためにSOG膜が、部分的に反応し膜の割れ(マイクロ
クラック)や、剥がれを引き起こす副作用があった。
However, in the case of this method, the lower layer SO
The SOG film partially reacts because the O 2 radicals and O 3 that have entered the film in addition to the reaction on the outermost surface of the G film 104 cause the above-described decomposition and sublimation reactions, and the film is cracked (micro crack). Also, there were side effects that caused peeling.

【0013】そこで、SOG膜中にあるSi−OR,S
i−Hと積極的に反応をしない不活性ガスであるArガ
スを用いたプラズマにより表面処理を行うことで密着性
の確保が可能となった。
Therefore, the Si-OR, S in the SOG film
By performing surface treatment using plasma using Ar gas, which is an inert gas that does not actively react with i-H, adhesion can be ensured.

【0014】Arプラズマは、不活性ガスである為ラジ
カル化しづらくイオン化するのが殆どであることより、
ArイオンによりSOG膜表面がイオン衝撃で物理的な
エネルギーが与えられ、発熱することによるベーク効果
と、衝撃によりSOG膜の最表面にあるSi−OR基
や、SI−H基のボンドが切れるためにOプラズマ処
理や、O処理を行ったものと同様の効果が得られ且
つ、最表面での反応効果となる。
Since Ar plasma is an inert gas and is hardly radicalized and is almost ionized,
Physical energy is given to the surface of the SOG film by ion bombardment due to Ar ions, and a bake effect due to heat generation, and a bond of Si-OR group or SI-H group on the outermost surface of the SOG film is broken by bombardment. The same effects as those obtained by performing O 2 plasma treatment or O 3 treatment can be obtained, and a reaction effect on the outermost surface can be obtained.

【0015】また、たとえArガスがラジカル化しても
不活性ガスであるためSOG膜中にある前述のものとは
直接反応しないので膜の劣化の恐れがない。
Further, even if Ar gas is radicalized, it is an inert gas and does not directly react with the above-mentioned one in the SOG film, so there is no fear of deterioration of the film.

【0016】この効果は、Arガスだけではなく、アル
ゴンガス、クリプトンガス、ネオンガス、キセノンガ
ス、窒素ガス、ヘリウムガスからなる群から選択される
少なくとも一種類のガスを含む反応ガスを用いることで
も同様の効果が得られるが、製造に於ける経済性、入手
のしやすさの点よりArの方が優れる。また、Arガス
プラズマは、低圧での放電安定性を得るために高周波電
力を1.5から2キロワット入れることが必要となる反
面、非常にイオン性が強いので、放電部内構成部品への
ダメージや、発熱が大きいため、ウェーハの温度コント
ロールが問題となる。
This effect can also be obtained by using a reaction gas containing at least one gas selected from the group consisting of argon gas, krypton gas, neon gas, xenon gas, nitrogen gas and helium gas in addition to Ar gas. However, Ar is superior from the viewpoint of economical efficiency in production and availability. Also, Ar gas plasma requires 1.5 to 2 kilowatts of high-frequency power to obtain discharge stability at low pressure, but has very strong ionicity. Since the heat generation is large, temperature control of the wafer becomes a problem.

【0017】特に今回の事例のように,AL配線層間に
用いるSOGの表面処理の場合ALとSiの反応が加速
される400℃以上になるとALと、半導体基板の接触
抵抗に影響を与えるばかりでなく、半導体基板中へのA
Lの拡散によるリークを引き起こすため、プラズマ処理
によるウェーハ温度の過昇温を防止するための処理時間
の短縮化1分処理から15秒への短縮、ウェーハ裏面か
らの熱伝導率向上、低パワー下での放電安定化を行うこ
とでSOGの最表面にあるSi−OR基や、SI−H基
のボンドを切ったり、重合を促進為に最も適したウェー
ハ温度である約250℃から350℃にコントロールす
る必要があった。
In particular, as in this case, in the case of surface treatment of SOG used between AL wiring layers, when the reaction between AL and Si is accelerated to 400 ° C. or more, it only affects AL and the contact resistance of the semiconductor substrate. No, A in the semiconductor substrate
In order to cause leakage due to diffusion of L, shortening of processing time to prevent excessive temperature rise of wafer temperature by plasma processing, shortening from 1 minute processing to 15 seconds, improvement of thermal conductivity from the back side of wafer, low power To stabilize the discharge of Si-OR group and SI-H group on the outermost surface of SOG, and to reduce the temperature of the wafer, which is most suitable for promoting polymerization, from about 250 ° C to 350 ° C. I needed to control.

【0018】[0018]

【発明の効果】以上説明した本発明の製造方法によれ
ば、SOGの多層塗布工程においてプラズマ照射による
表面処理を実施する事で、下層SOG膜層中の残留有機
成分のSi−OR、Si−H,Si−CH等にに影響
を与えること無く下層SOG膜層の表面にあるSi−O
R、Si−H,Si−CHを分解するため下層SOG
膜層と上層SOG膜層の密着性が確保可能である。
According to the manufacturing method of the present invention described above, the surface treatment by plasma irradiation is performed in the multi-layer coating process of SOG, so that the remaining organic components Si-OR and Si- H, Si-O on the surface of no lower SOG layer affecting the Si-CH 3, etc.
Lower SOG to decompose R, Si-H, the Si-CH 3
Adhesion between the film layer and the upper SOG film layer can be ensured.

【0019】また、請求項2に係る半導体装置の製造方
法によれば、アルゴンガス、クリプトンガス、ネオンガ
ス、キセノンガス、窒素ガス、ヘリウムガスからなる群
から選択される少なくとも一種類のガスを含む反応ガス
を用いて前記プラズマ照射行うことで、さらに下層SO
G膜中に残留する有機成分のSi−OR、Si−H,S
i−CH等に影響を与えること無く下層SOG膜層の
表面にあるSi−OR、Si−H,Si−CHを分解
するため、効率よく上層SOG膜層や第2のCVD酸化
膜層との密着性の向上しSOGの剥がれ、割れの発生を
防止することが可能である。
Further, according to the method of manufacturing a semiconductor device according to the second aspect, the reaction including at least one gas selected from the group consisting of argon gas, krypton gas, neon gas, xenon gas, nitrogen gas, and helium gas. By performing the plasma irradiation using a gas, the lower layer SO
Organic components Si-OR, Si-H, S remaining in the G film
Si-OR in no surface of the lower SOG layer to affect the i-CH 3 and the like, Si-H, in order to decompose the Si-CH 3, efficiently upper SOG layer and the second CVD oxide film layer It is possible to prevent SOG peeling and cracking from occurring by improving the adhesion to the SOG.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例に係る半導体装置の製造工程の
一部を示す部分断面図である。
FIG. 1 is a partial cross-sectional view showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

101 半導体基板 102 第1のCVD酸化膜層 103 配線 104 下層SOG膜層 105 上層SOG膜層 106 プラズマ照射 107 第2のCVD酸化膜層 Reference Signs List 101 semiconductor substrate 102 first CVD oxide film layer 103 wiring 104 lower SOG film layer 105 upper SOG film layer 106 plasma irradiation 107 second CVD oxide film layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体装置のSOGの塗布工程に於いて、
SOGを1から複数回連続して塗布する工程と、下層S
OGの塗布と上層SOGの塗布の間にプラズマ照射によ
る表面処理を行う工程を有する事を特徴とする半導体装
置の製造方法。
In an SOG coating process of a semiconductor device,
A step of continuously applying SOG from one to a plurality of times;
A method for manufacturing a semiconductor device, comprising a step of performing a surface treatment by plasma irradiation between application of OG and application of an upper layer SOG.
【請求項2】前記プラズマ照射は、アルゴンガス、クリ
プトンガス、ネオンガス、キセノンガス、窒素ガス、ヘ
リウムガスからなる群から選択される少なくとも一種類
のガスを含む反応ガスを用いて行うことを特徴とする請
求項1記載の半導体装置の製造方法。
2. The method according to claim 1, wherein the plasma irradiation is performed using a reaction gas containing at least one gas selected from the group consisting of argon gas, krypton gas, neon gas, xenon gas, nitrogen gas, and helium gas. The method for manufacturing a semiconductor device according to claim 1.
JP32808097A 1997-11-28 1997-11-28 Manufacture of semiconductor device Withdrawn JPH11162969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32808097A JPH11162969A (en) 1997-11-28 1997-11-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32808097A JPH11162969A (en) 1997-11-28 1997-11-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11162969A true JPH11162969A (en) 1999-06-18

Family

ID=18206298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32808097A Withdrawn JPH11162969A (en) 1997-11-28 1997-11-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11162969A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6746963B2 (en) 2001-05-01 2004-06-08 Tokyo Ohka Kogyo Co., Ltd. Method for processing coating film and method for manufacturing semiconductor element with use of the same method
US6794311B2 (en) * 2000-07-14 2004-09-21 Applied Materials Inc. Method and apparatus for treating low k dielectric layers to reduce diffusion

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6794311B2 (en) * 2000-07-14 2004-09-21 Applied Materials Inc. Method and apparatus for treating low k dielectric layers to reduce diffusion
US6746963B2 (en) 2001-05-01 2004-06-08 Tokyo Ohka Kogyo Co., Ltd. Method for processing coating film and method for manufacturing semiconductor element with use of the same method

Similar Documents

Publication Publication Date Title
KR20060088562A (en) Plasma processing method and plasma processing apparatus
JP3250518B2 (en) Semiconductor device and manufacturing method thereof
JPH11162969A (en) Manufacture of semiconductor device
KR20100016479A (en) Dry etching method
JP4032447B2 (en) Manufacturing method of semiconductor device
JPH10261596A (en) Manufacture of semiconductor device
JP2005294640A (en) Method for manufacturing semiconductor device
JP2834667B2 (en) Method for manufacturing semiconductor device
JPH01319942A (en) Forming method for insulating film
JPH0456453B2 (en)
JP3363614B2 (en) Method for manufacturing semiconductor device
JPH06216116A (en) Insulation film formation method by silicone resin
JP4616492B2 (en) Method for forming insulating film of semiconductor element
GB2301224A (en) Method of forming a SOG film in a semiconductor device
JP2808401B2 (en) Method for manufacturing semiconductor device
KR100780686B1 (en) Method for fabricating semiconductor device
JP3008996B2 (en) Method of forming insulating film
JP3327994B2 (en) Method for manufacturing semiconductor device
JP3473302B2 (en) Method for forming coating type insulating film, method for manufacturing semiconductor device, and semiconductor device
JPH1022382A (en) Manufacture of semiconductor device
KR100210897B1 (en) Process for forming barrier metal layer in semiconductor device
JPH09199495A (en) Sog film forming method of semiconductor device
JP3252582B2 (en) Method for manufacturing semiconductor device
KR100341847B1 (en) Method of forming a bit line in a semiconductor device
JPH025551A (en) Semiconductor device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20050201