JPH11162872A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having an interconnection which is capable of having a low contact resistance with a semiconductor substrate, without conducting a heat treatment other than the one at 400-500 deg.C which is indispensable to a normal semiconductor integrated circuit device manufacturing process and which includes a TiW alloy which exhibits superior property as a barrier even for a single layer. SOLUTION: In a semiconductor integrated circuit device, wherein a contact hole 13a formed in an insulating film 13 formed on a semiconductor substrate 11 is filled with a metal, a TiW alloy layer 14 having a Ti density of 20 at.% at least and 50 at.% at most against the total density of W and Ti and an oxygen density of 1.0 at.% at least and 20 at.% at most or a TiW alloy layer 14, having the Ti density of 5 at.% at least and less than 20 at.% and the oxygen density of 0.5 at.% at least and 15 at.% at most is formed on part of the semiconductor substrate which is exposed at the bottom of the contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device characterized by a TiW wiring buried in a contact hole and a method of forming the same, and a method of manufacturing the same. .

[0002]

2. Description of the Related Art When a metal plug or metal wiring such as W or Al is buried in a contact hole, as disclosed in, for example, JP-A-2-96331 and JP-A-1-138718, In many cases, a TiW alloy or a Ti layer is formed between the semiconductor substrate and the metal wiring or between the semiconductor substrate and the metal wiring. This is formed for the purpose of obtaining an ohmic contact with the semiconductor substrate or preventing interdiffusion between the metal plug or metal wiring and the semiconductor substrate, and is called a contact layer and a barrier layer, respectively. Further, Ti is a material having a low contact resistance with the semiconductor substrate and an excellent material as a contact layer. However, Ti or oxygen gas or the like when forming Al or W laminated on the semiconductor substrate or Ti by the CVD method is used. Poor barrier properties. Therefore, a barrier layer such as TiN is often laminated on the Ti layer.

[0003] TiW commonly used for LSI wiring
The Ti concentration of the alloy is 20 at% to 30 at%. At this time, TiW has advantages such as excellent barrier properties as compared with Ti and less occurrence of film peeling during metal embedding.

However, the contact resistance between the TiW alloy and the semiconductor substrate is larger than the contact resistance between the Ti and the semiconductor substrate, and there is a problem that a trouble due to poor resistance occurs. In particular, when heat treatment is performed at 400 ° C. to 500 ° C., T
In the case of a TiW alloy having an i concentration of 20 at% to 30 at%,
The contact resistance with the semiconductor substrate becomes extremely high, causing trouble. Here, the heat treatment at 400 ° C. to 500 ° C.
In a normal semiconductor integrated circuit device manufacturing process, it is inevitable to form a silicon oxide insulating film after forming a barrier layer such as TiW.

Therefore, in US Pat. No. 4,888,297,
Ti concentration of about 90 at% to 97 at for the contact layer
% TiW alloy has been shown to be used, and Babco
ck et al. (J. Appl. phys. 53, 1982, p.
6898-6905) It is recommended to use a TiW alloy having a Ti concentration of 80 at%.

However, since the TiW alloy having such a composition has insufficient barrier properties, a TiW alloy having a composition different from that of the contact layer, that is, Ti63a is used.
A TiW alloy layer of 30 at% or less of t% is laminated as a barrier layer.

Further, as disclosed in JP-A-5-175346, a heat treatment is performed at 600 to 750 ° C. after forming a barrier layer such as TiW.
There is also a method of reducing the contact resistance between the iW alloy and the semiconductor substrate, but in that case, a new heat treatment step must be added to the normal semiconductor integrated circuit device manufacturing process,
There was a problem that manufacturing cost increased.

[0008]

SUMMARY OF THE INVENTION The present invention relates to a method for fabricating a semiconductor integrated circuit device which is used in a normal process of manufacturing semiconductor integrated circuit devices.
It is an object of the present invention to provide a semiconductor integrated circuit device having a wiring made of a TiW alloy, which has a low contact resistance with a semiconductor substrate even without performing a special heat treatment other than a heat treatment at a temperature of 1 ° C. and has a sufficiently high barrier property, and a method of manufacturing the same. It is the purpose.

[0009]

In order to achieve the above object, the present invention relates to a semiconductor integrated circuit device in which a metal is buried in a contact hole formed in an insulating film formed on a semiconductor substrate. A TiW alloy having a Ti concentration of 20 at% or more and 50 at% or less and a total oxygen concentration of 1.0 at% or more and 20 at% or less with respect to the total concentration of W and Ti on the semiconductor substrate exposed at the bottom. Layer or Ti concentration is at least 5 at% and 20
at% and the oxygen concentration is at least 0.5 at%.
% At least 15 at% or less. Also,
Sputtering is performed by using an Ar gas containing 0.1 vol% to 20 vol% of oxygen gas and 1 vol% to 50 vol% of hydrogen gas of the entire flow rate, or by applying a bias current to a semiconductor substrate and performing sputtering. The semiconductor integrated circuit device is manufactured by forming a film.

[0010] T with respect to the sum of the concentration of W and Ti in the TiW alloy
whether the i concentration is 20 at% or more and 50 at% or less and the oxygen concentration is 1.0 at% or more and 20 at% or less;
Alternatively, the Ti concentration relative to the sum of the W and Ti concentrations is 5 at%.
Not less than 20 at% and the oxygen concentration is 0.5 a
400% to 50 ° C.
Even if heat treatment at 0 ° C. is performed, no amorphous silicide layer is formed between the TiW alloy layer having the BCC structure and the semiconductor substrate.
The contact resistance between the W alloy and the semiconductor substrate is kept low.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail.

When a TiW alloy is formed on a semiconductor substrate by sputtering, the Ti concentration becomes 0 at% to 90 at%.
The TiW alloy has a BCC structure in the range of (J. App.
l. phys. 53, 1982, P. 6898-690
5). A TiW alloy that is industrially frequently used as a barrier layer has a Ti concentration of 20 at% to 30 at%. When this is heat-treated at a temperature of 400 to 500 ° C., the TiW alloy having a BCC structure and the An amorphous silicide layer having a thickness of about 1 nm to 2 nm is generated therebetween. The generation of this amorphous silicide layer greatly increases the contact resistance between the semiconductor substrate and the TiW alloy layer.

As a method for preventing this, Japanese Patent Application Laid-Open No. 5-175
No. 346 discloses that a barrier layer of a TiW alloy or the like is formed and then subjected to a high-temperature heat treatment at 600 ° C. to 750 ° C., so that the Ti, W and the crystalline ternary elements of the semiconductor substrate element are formed between the TiW alloy and the semiconductor substrate. A method of forming an alloy epitaxially has been proposed. However, in this method, a new heat treatment step is added to the normal semiconductor integrated circuit device manufacturing process, and thus there is a problem that the cost increases. FIG. 1 shows a cross-sectional structure of a typical semiconductor integrated circuit. In the silicon oxide insulating film 3 formed on the substrate 1, a contact hole 3 a is formed on the n-type diffusion layer 2 of the substrate 1, and a TiW alloy layer 4 and a W layer are formed therein and on the silicon oxide insulating film 3. 5 is formed. After forming the TiW alloy layer 4 and the W layer 5, a silicon oxide insulating film 6 (spin on glass: SOG)
Is heated to a temperature of 400 ° C to 500 ° C.
Further, when SOG is formed in a later step, the temperature may be 400 ° C. to 5 ° C.
A heat treatment at 00 ° C. is performed. Therefore, 400 ° C. to 500
C. heat treatment is inevitable. The present inventors have found that an amorphous silicide layer is not formed between the TiW alloy having the BCC structure and the semiconductor substrate even when the TiW alloy having the composition of the present invention is heat-treated at a temperature of 400 ° C. to 500 ° C. It has been found that this makes it possible to prevent an increase in contact resistance between the semiconductor substrate and the TiW alloy layer without performing high-temperature heat treatment at 600 ° C. to 750 ° C. Further, the TiW alloy of the composition of the present invention has a sufficient barrier property, so that one layer can serve both as a contact layer and a barrier layer. This is achieved by intentionally mixing an appropriate amount of oxygen,
It is considered that the barrier property is higher than that of the conventional TiW alloy because oxygen enters defects such as grain boundaries.

The reasons for limiting the composition will be described below. Regarding claim 1, Ti with respect to the sum of the concentrations of W and Ti
When the concentration (hereinafter, abbreviated as Ti concentration) is 20 at% or more, and when the oxygen concentration is less than 1.0 at%, 400 ° C. to 50 ° C.
An amorphous silicide layer is generated between the TiW alloy having the BCC structure and the semiconductor substrate by the heat treatment at a temperature of 0 ° C., and the contact resistance with the semiconductor substrate is increased by the heat treatment. Therefore,
When the Ti concentration is 20 at% or more, the lower limit of the oxygen concentration is 1.0 at%. In addition, the contact resistance with the semiconductor substrate tends to increase as the oxygen concentration increases. In particular, when the oxygen concentration exceeds 20 at%, the contact resistance with the semiconductor substrate rapidly increases. Therefore, the upper limit of the oxygen concentration is 20
at%.

When the Ti concentration exceeds 50 at%,
An amorphous TiW layer is generated between the TiW alloy having the BCC structure and the semiconductor substrate by the heat treatment at a temperature of 400 ° C. to 500 ° C. regardless of the oxygen concentration, and the contact resistance with the semiconductor substrate is increased by the heat treatment. Therefore, the upper limit of the Ti concentration is 50 at.
%.

Next, according to claim 2, the Ti concentration is 20a.
When the oxygen concentration is less than 0.5 at%,
An amorphous silicide layer is generated between the semiconductor substrate and the TiW alloy having the BCC structure by the heat treatment at a temperature of 00 ° C. to 500 ° C. Therefore, when the Ti concentration is less than 20 at%, the lower limit of the oxygen concentration is 0.5 at%. Further, the contact resistance with the semiconductor substrate tends to increase as the oxygen concentration increases, and particularly when the oxygen concentration exceeds 15 at%, the contact resistance with the semiconductor substrate rapidly increases. Therefore, the upper limit of the oxygen concentration is 15 at%. When the Ti concentration is 5 at
%, The contact resistance with the semiconductor substrate does not increase due to the heat treatment, but the contact resistance with the semiconductor substrate before the heat treatment is already large. Therefore, the lower limit of the Ti concentration is 5 at%.

Next, the reasons for limiting the gas components in the method of manufacturing a semiconductor integrated circuit device according to the present invention will be described. T
In general, an argon gas is used as a sputtering gas to form an iW alloy by sputtering, and a gas obtained by mixing oxygen with argon gas is used as a sputtering gas to form a TiW oxide film or a TiW alloy containing oxygen by sputtering. In general, when a metal target is formed by sputtering using a gas obtained by mixing oxygen with argon gas, when the oxygen gas concentration exceeds a certain critical value, the oxygen concentration in the formed TiW alloy rapidly increases, and It becomes an oxidized film. Therefore, in order to precisely control the oxygen concentration in the TiW alloy, it is necessary to use hydrogen gas as a buffer for the oxidation reaction. In order to form a TiW alloy having an oxygen concentration of 0.5 at%, oxygen gas is added to the sputtering gas at a total flow rate of 0.1 vol.
1% or more. Therefore, the lower limit of the oxygen gas concentration is 0.1 vol%. When the oxygen gas exceeds 20 vol% of the total flow rate, the oxygen concentration in the TiW alloy exceeds 20 at% regardless of the hydrogen gas concentration.
Therefore, the upper limit of the oxygen gas concentration is 20 vol%. On the other hand, the hydrogen gas concentration is 1 vol.
%, But the effect does not change even if it exceeds 50 vol%, and the deposition rate of the TiW alloy may be sharply reduced since the argon gas concentration is relatively reduced. Therefore, the concentration range of hydrogen gas is 1 vol.
% Or more and 50 vol% or less.

[0018]

Embodiment 1 FIG. 2 is a sectional view of a contact hole portion of a semiconductor integrated circuit device showing one embodiment of the present invention. A 1.5 μm-thick silicon oxide film 13 is formed as an interlayer insulating film on a p-type silicon substrate 11, and an approximately 0.3 μm-thick n-type diffusion layer 2 provided on a part of the p-type silicon substrate 1 is formed. A contact hole 13a having a diameter of 0.5 μm is formed in the silicon oxide film 13 above. A TiW alloy layer 14 is formed in the contact hole 13a so that the film thickness outside the contact hole becomes 100 nm (about 20 nm at the bottom of the hole). Here, in this embodiment, in order to control the Ti concentration, T
Using two targets of i and W, the power applied to each target is adjusted while rotating the substrate, and sputtering is performed at the same time.
At% and 3 at% were prepared. The sputtering was carried out in an argon gas containing 1.8 vol% of the total flow rate of oxygen gas and 8.9 vol% of hydrogen while heating the substrate to 300 ° C. A W layer 15 having a thickness of 100 nm outside the contact hole is formed on the TiW alloy layer 14 by C
It was buried by the VD method, and W was removed by etching using a photolithography method except for the peripheral portion of the contact hole 13a. A silicon oxide film 16 as an interlayer insulating film was formed thereon, and only the silicon oxide film 16 around the contact hole 13a was removed again by photolithography. After subjecting the contact resistance measurement samples produced by this method to heat treatment at 450 ° C. for 3 hours in an argon atmosphere, the contact resistance of each sample was measured.
The oxygen concentration in the TiW alloy was measured by an EDS analysis at the time of observation with a transmission electron microscope described later. TiW
Table 1 shows the measurement results of the oxygen concentration in the alloy and the contact resistance before and after the heat treatment.

[0019]

[Table 1]

When the Ti concentration is 70 at% and the oxygen concentration is 9 at%
% Of TiW, the contact resistance was 2015 Ω, and the contact resistance of Ti at 3 at% and the oxygen concentration of 3 at% was as high as 980 Ω, respectively. The concentration is 30at
% And an oxygen concentration of 5 at%, the resistance value was as small as 340Ω.

Next, the substrates Si and TiW of each sample were prepared.
The cross-sectional structure (interface structure) of the contact portion of the alloy was observed with a transmission electron microscope, and amorphous Ti was added between the substrate Si and the TiW alloy.
It was determined whether a W layer was present. FIG. 3 shows an observation result of an interface structure between a TiW alloy having a Ti concentration of 70 at% and an oxygen concentration of 9 at% and an Si substrate as an example outside the scope of the present invention. It was found that an amorphous (TiW) Si layer having a thickness of about 2 nm was formed between the Si substrate and the TiC alloy having the BCC structure. FIG. 4 shows an example of the present invention where the Ti concentration is 3
It is an observation result of an interface structure between a TiW alloy having an oxygen concentration of 0 at% and an oxygen concentration of 5 at% and a Si substrate. BC directly on Si substrate
A TiW alloy having a C structure is formed, and a Si substrate and a BC
It was found that there was no amorphous silicide layer between the TiW alloys having the C structure. As described above, in the semiconductor integrated circuit device of the present invention, no amorphous silicide layer causing a high resistance was formed between the Si substrate and the TiW alloy having the BCC structure.

Example 2 A contact hole was formed on a Si substrate having the same contact hole as that of Example 1 so that the thickness of the contact hole outside the contact hole was 100 nm (about 20 nm at the bottom of the hole).
m) A TiW alloy layer 14 was formed. Here, in this example, a target having a Ti concentration of 30 at% was used, and a sample sputtered with only argon gas while heating the substrate to 300 ° C. and 1.6 vol% of the total flow rate of the oxygen gas and 16 vol% of hydrogen were included. A sample was prepared by sputtering with argon gas. After the formation of the TiW alloy, a sample for contact resistance measurement was manufactured in the same process as in Example 1. After subjecting each sample for contact resistance measurement to heat treatment at 450 ° C. for 30 minutes to 3 hours in an argon atmosphere, the contact resistance of each sample was measured.

FIG. 5 shows the dependence of the contact resistance of each sample on the heat treatment time. In the case of a sample prepared by sputtering only with argon gas, a heat treatment
Although the contact resistance was as low as 15Ω, the contact resistance increased with time in the further heat treatment. On the other hand, when the film was formed by sputtering with an argon gas containing hydrogen and oxygen according to the present invention, a sufficiently low contact resistance was maintained without depending on the time in the heat treatment up to 3 hours. This suggests that in the case of the present invention, the reliability is high even after a heat treatment step, which is inevitable in a semiconductor integrated circuit device manufacturing process such as SOG baking after the formation of a TiW layer.

Example 3 A 100 nm TiW film was formed on a silicon substrate, and two targets of Ti and W were used to control the Ti concentration ratio.
It was fabricated by adjusting the power applied to each target while rotating the substrate and sputtering simultaneously. The power of each target is controlled so that the Ti concentration becomes 30 at%, oxygen gas is supplied at 10 vol% of the total flow rate, and hydrogen is supplied at 40 vol%.
Film formation was performed while applying a bias of RF 100 W to the substrate with an argon gas containing 1%. In addition, T
The power of each target was adjusted so that the i concentration became 30 at% and 70 at%, and samples sputtered with only argon gas were also produced.

In order to evaluate the barrier properties of these three samples against oxygen, an oxygen gas was introduced into a device provided with a heater in a vacuum chamber at a pressure of 3 mTorr, and heat treatment was performed at 450 ° C. for 10 minutes. went. Next, the depth direction distribution of the oxygen concentration of each sample was measured by photoelectron spectroscopy. The results are shown in the graphs of FIGS. In the samples (FIGS. 6 and 7) in which the power of each target was adjusted so that the Ti concentration became 30 at% and 70 at% and sputtered using only argon gas, respectively (FIGS. 6 and 7), a thick oxide of Ti was formed on the film surface. On the other hand, in the sample (FIG. 8) manufactured by the process according to the present invention, the Ti oxide was present only extremely thinly on the surface, indicating that the barrier property against oxygen was high. This indicates that according to the present invention, it is possible to directly cover the interlayer insulating film without laminating a barrier layer such as TiN, and it is possible to use the capacitor oxide film as an electrode. .

[0026]

According to the present invention, 400.degree. C. to 500.degree. C. which is inevitable in a normal semiconductor integrated circuit device manufacturing process.
The contact resistance with the semiconductor substrate is low even if no special heat treatment other than the heat treatment of
It is possible to provide a semiconductor integrated circuit device having a wiring containing an iW alloy, thereby reducing manufacturing costs.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a contact hole portion of a conventional typical semiconductor integrated circuit device.

FIG. 2 is a cross-sectional view of a contact hole portion of a semiconductor integrated circuit device according to the present invention used for contact resistance measurement.

FIG. 3 shows a T concentration of 70 at% and an O concentration of 9 at%.
The transmission electron micrograph which shows the metal structure of what formed the iW alloy on the board | substrate Si, and heat-processed at 450 degreeC for 3 hours.

FIG. 4 shows a T concentration of 30 at% and an O concentration of 5 at%.
The transmission electron micrograph which shows the metal structure of what formed the iW alloy on the board | substrate Si, and heat-processed at 450 degreeC for 3 hours.

FIG. 5 is a graph showing heat treatment time dependence of contact resistance of a sample manufactured by sputtering only with an argon gas and a sample formed by sputtering with an argon gas containing hydrogen and oxygen.

FIG. 6 is a graph showing the barrier property against oxygen of a sample sputtered only with argon gas by adjusting the power of each target so that the Ti concentration becomes 30 at%. O1
The curves indicated by s, Ti2p, and W4f are the oxygen 1
It shows photoelectron intensity due to excitation of s orbital electrons, Ti 2p orbital electrons, and W 4f orbital electrons, which are proportional to the concentrations of oxygen, Ti, and W, respectively.

FIG. 7 is a graph similar to FIG. 6, showing the barrier property against oxygen of a sample sputtered with only argon gas by adjusting the power of each target so that the Ti concentration becomes 70 at%.

FIG. 8 is a diagram showing the barrier property against oxygen of a sample sputtered by adjusting the power of each target so that the Ti concentration becomes 30 at% and applying a bias of RF 100 W to the substrate with an argon gas containing oxygen and hydrogen while applying a bias of RF 100 W to the substrate. 6 and a graph similar to FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-type silicon substrate 2 n-type diffusion layer 3 interlayer insulating film (silicon oxide) 3 a contact hole 4 TiW alloy layer 5 W layer 6 interlayer insulating film (silicon oxide) 11 p-type silicon substrate 12 n-type diffusion layer 13 interlayer insulating film (Silicon oxide) 13a Contact hole 14 TiW alloy layer 15 W layer 16 Interlayer insulating film (silicon oxide)

Claims (4)

[Claims] 1. A semiconductor integrated circuit device in which a metal is buried in a contact hole opened in an insulating film formed on a semiconductor substrate, wherein:
The Ti concentration with respect to the sum of the concentrations of W and Ti is 20 at% or more and 50 at% or less, and the oxygen concentration is 1.0 at
A semiconductor integrated circuit device, wherein a metal wiring including a TiW alloy layer of not less than at% and not more than 20 at% is formed. 2. A semiconductor integrated circuit device in which metal is buried in a contact hole opened in an insulating film formed on a semiconductor substrate, wherein:
The Ti concentration with respect to the sum of the concentrations of W and Ti is 5 at% or more and less than 20 at%, and the oxygen concentration is 0.5
A semiconductor integrated circuit device, wherein a metal wiring including a TiW alloy layer having a content of at least 15 at% or less is formed. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein in the step of forming the TiW layer, oxygen gas having a total flow rate of 0.1 vol% or more and 20 vol% or less; 1 vol% or more 50
A method for manufacturing a semiconductor integrated circuit device, comprising: forming a film by sputtering using an argon gas containing a hydrogen gas of not more than vol%. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein in the step of forming the TiW layer, an oxygen gas having a total flow rate of 0.1 vol% or more and 20 vol% or less; 1 vol% or more 50
A method for manufacturing a semiconductor integrated circuit device, wherein a bias current is applied to a semiconductor substrate to form a film by sputtering using an argon gas containing hydrogen gas of not more than vol%.