JPH11154738A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To readily produce an intermediate memory capacity which corresponds to a memory capacity of a multiple of four. SOLUTION: A cell array block and a control circuit for controlling operation of the cell array block constitute a sub-chip A, and a plurality of sub-chips A are used to obtain a memory of desired capacity. In addition, an interval region D is assured between adjoining sub-chips A, and a cell array block not required due to memory capacity reduction is separated from the control circuit for controlling cell array block operation with the interval region D.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device using a semiconductor memory.

[0002]

2. Description of the Related Art A semiconductor memory such as a dynamic RAM has a memory capacity which increases by a factor of four, and accordingly, the number of control circuits for controlling them increases, and as a result, the current consumption also increases. As a countermeasure,
As disclosed in Japanese Patent Application Laid-Open No. 4-144276, a cell array block and a circuit for controlling the operation of the cell array block are each divided, and only a selected portion is operated to reduce current consumption. You are.

According to the technique disclosed in Japanese Patent Application Laid-Open No. 4-144276, a circuit B for controlling the entirety and a bonding pad C are arranged at the center of a chip, and both sides thereof have a half of the total memory capacity. , A cell array block and a circuit for controlling the operation of the cell array block are arranged. Further, as shown in FIG. 5, the cell array block and a circuit for controlling the operation of the cell array block are divided so that the memory capacity is reduced to １ ／, and the operation of the divided cell array block and the cell array block is performed. The current consumption is reduced by limiting the operation area of the subchip A including the control circuit. In FIG.
B ₂ is a circuit for controlling the whole in common, C ₂ is a common bonding pad, F is a circuit for controlling only the left half sub-chip A, and G is a bonding pad used only in the left half sub-chip A.

[0004] A subchip A composed of a cell array block and a circuit for controlling the operation of the cell array block includes:
It is also possible to further subdivide.

[0005] The memory capacity is increased by a factor of 4, but some systems require intermediate capacity depending on the system configuration. Conventionally, measures have been taken by using a capacitor having a large capacity in the dividing operation.

[0006]

However, in the conventional example, there is a problem that the chip size is increased by an unnecessary memory capacity, and the cost is increased accordingly. Further, even if an attempt is made to delete a part that is not required forcibly, a part commonly used in a circuit for controlling the operation of the cell array block remains in a protruding form, resulting in a problem that the chip size becomes larger than originally possible. .

The reason is that it is not assumed that a cell array block that is not required for reducing the memory capacity and a circuit that controls the operation of the cell array block are separated on a specific surface.

An object of the present invention is to provide a semiconductor device capable of more quickly responding to a memory capacity required in a system configuration than in the past and supplying the semiconductor device quickly.

[0009]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a semiconductor memory whose memory capacity increases by a factor of four. A plurality of sub-chips each including a cell array block divided by a multiple and a circuit for controlling the operation of the cell array block, the sub-chip having an isolated area for each adjacent area, A metal wiring is provided only in the upper layer, and the sub chips are connected to each other by the metal wiring.

Further, the isolation region has a width of at least 1 μm.

The sub-chips are arranged inside and outside with an isolation region interposed therebetween.

The sub-chips are arranged in a block-like manner in an area centered on the isolation area.

Further, the semiconductor device according to the present invention is a semiconductor device having a semiconductor memory whose memory capacity increases by a factor of four, wherein the cell array block is divided by a multiple of the original memory capacity, And a control circuit for controlling the operation of the plurality of sub-chips, the control circuit is arranged at an intersection that passes through the center of the chip body, and the sub-chip is evenly arranged at the corner of the intersection And an isolation region for dividing a sub chip on the chip body into right and left around the intersection.

According to the present invention, a subchip A is constituted by a cell array block and a control circuit for controlling the operation of the cell array block, and a desired memory capacity is obtained by using a plurality of the subchips A. Further, an isolation region D is secured between adjacent sub-chips A, and a cell array block which is not necessary for reducing memory capacity and a control circuit for controlling the operation of the cell array block are separated from each other.
And disconnect.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a configuration diagram showing a semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is an enlarged view of a portion I in FIG.

Referring to FIG. 1, the semiconductor device according to the first embodiment of the present invention is basically intended for a semiconductor device having a semiconductor memory such as a dynamic RAM whose memory capacity is increased by a factor of four. It has a plurality of sub chips A and an isolation region D.

The sub-chip A is composed of a cell array block divided by a multiple of the original memory capacity and a control circuit for controlling the operation of the cell array block. As many as the original memory capacity before the division is provided.

The isolation region D is a blank region formed in a region adjacent to the plurality of sub-chips A, has metal wiring only in the uppermost layer, and is formed by connecting adjacent sub-chips A with each other by the metal wiring. It is.

In the first embodiment of the present invention shown in FIGS. 1 and 2, a common bonding pad C is provided at the center of the chip body.
Are provided linearly on the left and right sides, control circuits B and B for controlling the whole are provided linearly along both sides thereof, and two sub-chips A and A are provided on the left and right sides outside the control circuit B, and a straight line D-shaped isolation regions are provided, and two sub-chips A, A are provided on the right and left outside the isolation regions. That is, a plurality of sub-chips A, A are provided in line inside and outside with the isolation region D interposed therebetween, and the position of the sub-chip to be separated is defined by the isolation region D.

In the case shown in FIG. 1, the sub-chip A is composed of a cell array block divided by eight times the original memory capacity and a control circuit for controlling the operation of the cell array block.

Further, the isolation region D separating the adjacent sub chips A has a width of at least 1 μm, has a metal wiring E in the uppermost layer, and connects the adjacent sub chips A with each other by the metal wiring E. It has a connected structure. In this case, the sub-chip A has a minimum area, and is arranged not in a shape in which only some of the patterns protrude, but in a square shape in which data are uniformly arranged.

(Embodiment 2) FIG. 3 is a configuration diagram showing a semiconductor device according to Embodiment 2 of the present invention. In the semiconductor device according to the second embodiment of the present invention, the sub chip A
It is characterized in that it is arranged in a block shape in an area centered on the isolation area D.

More specifically, referring to FIG. 3, the sub-chip A includes a cell array block and a control circuit for controlling the operation of the cell array block.

[0025] Then, the intersection through the center of the chip body, to place the common bonding pad C ₁ straight in the transverse direction. The common bonding pad C ₁ is separated into the left and right in the isolated region D in the vertical direction to be described later, a part is used as a bonding pad G which is used only in the sub chip A in the left half.

Furthermore, along the two sides of the cross section through the center of the chip body, the control circuit B ₁ for controlling the entire commonly provided, the sub chip A evenly at the four corners of the intersection through the center of the chip body The chip body is divided into right and left by a vertical isolation region D crossing the center intersection of the chip body.
Further, a control circuit is composed of a control circuit F used only for the left (or right) sub chip A and a control circuit B ₁ used for the upper and lower two sub chips A on the right (or left) side. The longitudinal direction of the control circuit common bonding pad C ₁ Some B ₁ is provided in conjunction.

As shown in FIG. 3, a part of a circuit B ₁ for controlling the whole is shared along a surface for separating the same.
Make sure that no projecting parts are formed. Further, an isolation region D of 1 μm or more is secured, and the right adjacent sub-chips A are connected to each other using a metal wiring provided on the uppermost layer of the isolation region D, and used as a wiring for transmitting and receiving signals. Also, placing the common part of the bonding pad C ₁ to the outside of an extension of disconnection surface of the control circuit B _1. Also in this case, the sub chip A has the same configuration as above.

[0028]

As described above, according to the present invention, 1
The memory capacity is reduced by half so that the outer sub-chips can be easily separated from the isolated area having no pattern at intervals of μm or more.
It is possible to quickly provide a mask pattern of a semiconductor device constituted by the semiconductor memory described above.

The reason is that the operation of the circuits and design patterns for controlling the entire circuit has already been confirmed in the semiconductor memory before the memory capacity is reduced to half.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is an enlarged view of a portion I in FIG. 1;

FIG. 3 is a configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a configuration diagram showing a conventional semiconductor device.

FIG. 5 is a configuration diagram showing a conventional semiconductor device.

[Explanation of symbols]

 A Sub-chip B Control circuit for controlling the whole B1 and B2 Control circuit for controlling the whole C Bonding pads C1 and C2 Bonding pads common to D D Isolation region E Top layer metal wiring

Claims (5)

[Claims] 1. A semiconductor device comprising a semiconductor memory whose memory capacity increases by a factor of four, comprising: a cell array block divided by a multiple of the original memory capacity; and a circuit for controlling the operation of the cell array block. Having a plurality of sub-chips, each of the sub-chips has an isolation region for each adjacent region, and the isolation region has a metal wiring only in an uppermost layer,
A semiconductor device wherein the sub-chips are connected to each other by the metal wiring. 2. The semiconductor device according to claim 1, wherein the isolation region has a width of at least 1 μm. 3. The semiconductor device according to claim 1, wherein the sub chips are arranged inside and outside with an isolation region interposed therebetween. 4. The semiconductor device according to claim 1, wherein the sub-chip is arranged in a block shape in an area centered on an isolated area. 5. A semiconductor device provided with a semiconductor memory whose memory capacity increases by a factor of four, comprising: a cell array block divided by a multiple of the original memory capacity; and a control circuit for controlling the operation of the cell array block. A plurality of sub-chips comprising: a control circuit disposed at an intersection passing through the center of the chip body; and the sub-chips disposed evenly at corners of the intersection; A semiconductor device provided with an isolation region which is divided right and left around the intersection.