JPH11154680A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of offset of the mask alignment of an exposure system, when a semiconductor device is made compact. SOLUTION: By forming respective regions of an emitter, a base and a collector through self-alignment technology, a mask is not required and offset is prevented. Furthermore, the dimensions of an N-type collector extracting part 12 and an outer base 13 are determined by the film thicknesses of an N-type polysilicon 10 and a P-type polysilicon 7. The distances between the polysilicons and between a P-type polysilicon 7 and an emitter 15 are determined by the film thicknesses of Si3 N4 . Since the film thickness of the polysilicon and Si3 N4 can be controlled at units of several tens of Å, the semiconductor device can be formed at 1 μm or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device realizing miniaturization and high-speed operation.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices have been subjected to submicron processing for high integration and high speed processing, miniaturization, and reduction of parasitic capacitance.

For this reason, in the current photolithography method, it is difficult to realize processing of a submicron size or less due to a pattern shift, and a fine pattern is formed by a self-alignment (self-alignment) technique.

A conventional method for manufacturing a semiconductor device will be described with reference to FIG. First, as shown in FIG. 6A, an n-type buried collector layer 32 is formed on a P-type semiconductor substrate 31,
An n-type epitaxial layer 33 is formed thereon. Further, the main surfaces of the emitter and base regions are protected by a nitride film 34, and an oxide film 35 is formed therearound.

[0005] Next, as shown in FIG.
The nitride film 34 is changed to an oxide film 36 during the formation, and the periphery thereof is etched by photolithography. Further, a polycrystalline silicon 37 is formed, n-type ion implantation is performed, and a heat treatment is performed so as to reach the buried collector layer 32. Then, an extraction collector region 38 is formed. Further, the polycrystalline silicon on the main surface of the oxide film 36 is removed by photolithography.

[0006] Next, as shown in FIG.
Is removed, the oxide film 42 is vapor-phase grown on the entire surface, the external base region 39 is selectively opened, and after growing the polycrystalline silicon 40, P ⁺ type ion implantation is performed. Form. Further, the base region is selectively opened in the oxide film 42, and the base region 41 is formed by P-type ion implantation.

[0007] Next, as shown in FIG.
Is grown, the emitter region is opened, and the emitter region 44 is formed by ion implantation of n ⁺ type. Then base 4
5. Opening the collector 46 completes each base region and collector region.

Further, a method of manufacturing a semiconductor device by a self-alignment technique is disclosed in Japanese Patent Application Laid-Open Nos. 8-293504 and
-310520.

[0009]

However, the conventional example shown in FIG. 6 has a problem that the parasitic capacitance of the external base region, the intrinsic base region, and the emitter region increases.

The reason is that the mask alignment accuracy of the current exposure apparatus is about ± 0.2 μm, so that the buried collector region and the external base region and the margin between the external base region and the emitter region need to be 0.4 μm. Is increased.

Further, the manufacturing methods disclosed in Japanese Patent Application Laid-Open Nos. 8-293504 and 6-310520 have a problem that the collector region becomes large, which leads to an increase in parasitic capacitance and transistor size.

The reason for this is that the collector lead-out region is located on the outer periphery of the LOCOS and the trench. Usually, the base extraction electrode and the collector extraction electrode are arranged above the locos and trenches to reduce parasitic capacitance, and the locos and trench widths are increased to several μm or more, and the buried collector region is accordingly enlarged.

An object of the present invention is to provide a method of manufacturing a semiconductor device which realizes miniaturization, high speed, and high integration of elements by a self-alignment technique.

[0014]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises forming a buried collector region of a reverse conductivity type on a semiconductor substrate, and forming a buried collector region of the reverse conductivity type on the substrate. Forming an epitaxial layer, selectively removing the nitride film grown on the epitaxial layer main surface,
A collector extraction, an external base, an intrinsic base, and a fabrication method, wherein an oxide film serving as an emitter opening region is grown under the nitride film, and selectively etched to etch back the nitride film; A step of growing conductive type polycrystalline silicon and performing an etch back, and a step of growing a nitride film and performing an etch back.

[0015] Further, reverse conductivity type ion implantation is performed to reach a reverse conductivity type buried collector from the epitaxial layer.

A reverse conductivity type polycrystalline silicon is grown on the main surface of the epitaxial layer, a step of etching back, a step of growing a nitride film and an oxide film for planarization, a step of etch back, and a heat treatment. Forming a collector lead region of the mold and an external base of one conductivity type at the same time; and removing an oxide film serving as the emitter opening region to form an intrinsic base of one conductivity type.

Further, an emitter of the opposite conductivity type is formed from the main surface of the intrinsic base by ion implantation.

[0018] Further, a polycrystalline silicon of the opposite conductivity type is grown on the main surface of the intrinsic base, etched back, and an emitter is formed by heat treatment.

Further, an insulating film is grown on the main surface of the semiconductor device, and aperture windows are selectively formed as emitter, base and collector, and an emitter electrode, a base electrode and a collector electrode are formed respectively.

According to the self-alignment of the present invention, the dimensions of the emitter / base / collector region are determined by the thickness of the insulator or polycrystalline silicon. Miniaturization can be realized.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1A is a plan view showing a semiconductor device according to Embodiment 1 of the present invention, and FIG.
FIG. 2 is a sectional view taken along line XX ′ of FIG.

As shown in FIG. 1 (b), a region which becomes a semiconductor device after being separated from other elements by the LOCOS 6 has N
^- N-type diffused -type polysilicon 10 collector lead 1
N-type diffusion layer 9 previously diffused by N-type ion implantation
Electrically connects the buried collector 2 with the buried collector 2.

Next, the external base 13 is formed by diffusion of the P-type polysilicon 7 insulated from the N-type polysilicon 10 by the thickness of the Si ₃ N ₄ film 8. Further, P-type ions are implanted from an emitter opening window separated by the thickness of the Si ₃ N ₄ film 5 to form an intrinsic base 14 connected to an external base 13 by thermal diffusion.
The respective regions are completed by performing N-type ion implantation to be 5.

At this time, in the emitter / base / collector region, it is possible to eliminate a mask misalignment caused by an exposure machine in each region by a self-alignment technique. Since the size of each region is determined by the thickness of the polysilicon, it can be controlled within several tens of square meters.

Next, a specific example of Embodiment 1 of the present invention will be described in detail as Example 1 with reference to the drawings. FIG.
FIG. 3G is a structural cross-sectional view showing Example 1 of the present invention in the order of steps. First, as shown in FIG. 2A, an N-type buried collector 2 is formed in a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 having a thickness of about 1 μm is grown. Thereafter, the SiO ₂ film 4 is coated on the main surface of the epitaxial
Grow 000 $. The thickness at this time is finally adjusted by the design value of the parasitic capacitance of the emitter, base and collector electrodes. Further, the oxide film 4 is formed by photolithography so as to have a width of about several hundreds to about 1000 so as to selectively have a final emitter width.

Next, as shown in FIG. 2 (b), a Si ₃ N ₄ film 5 (nitride film) is grown on the entire
Is selectively removed by photolithography, and LOCOS 6 is formed by thermal oxidation.

[0028] Next, as shown in FIG. 2 (c), Si ₃ N ₄ film 5 are etched back leaving the side wall of the SiO ₂ film 4, the polysilicon 7 doped with boron to 1000Å growth, Si ₃ N by etching back _{4 The} film is left on the side wall of the film 5. Similarly, a Si ₃ N ₄ film 8 is grown at 1000 ° and is left on the side wall of the boron-doped polysilicon 7 by etch back. afterwards,
N-type ion implantation is performed, and an epitaxial layer depth of 0.5
The connection to the buried collector 2 is made from about μm.

[0029] Next, as shown in FIG. 2 (d), the polysilicon 10 doped with phosphorus was 1000Å grown, is formed on the sidewall of the Si ₃ N ₄ film 8 by etching back, 2000 Å or more so as to cover each etchback territory Of the Si ₃ N ₄ film 11 and the SiO ₂ film 19 (silicon oxide film)
Grow over Å.

Next, as shown in FIG. 3E, an etch-back is performed so that each etch-back area becomes flat. Thereafter, heat treatment is applied to form an N-type collector lead 12 and a P-type external base 13 directly below the polysilicons 10 and 7, respectively. At this time, boron-doped polysilicon 7 is 1 × 10 ²⁰
cm ^-3 , phosphorus-doped polysilicon 10 is 1 × 10 ²¹ cm
^Keep the concentration at about ^-3 .

Next, as shown in FIG. 3F, the SiO ₂ film 4 is removed, P-type ion implantation is performed at about 1 × 10 ¹⁶ cm ^-3 , and heat treatment is performed so as to connect to the external base 13. An intrinsic base 14 is formed, and N-type ion implantation is performed at 1 × 10
^{The process} is performed at about ²¹ cm ⁻³ to form the emitter 15.

Next, as shown in FIG. 3 (g), a SiO ₂ film 16 is grown and each contact region (emitter, base,
The collector is selectively opened, and an emitter electrode and a collector electrode are formed to complete each region.

(Embodiment 2) Next, Embodiment 2 of the present invention
Will be described with reference to FIG. 4A is a front view, and FIG. 4B is a cross-sectional view taken along line XX ′ of FIG. 4A.

The second embodiment of the present invention is characterized in that the N-type epitaxial layer 3 is thinned to about 0.5 μm to reduce the collector resistance in order to realize an operation at a higher frequency than the first embodiment. Things. In this case, since the epitaxial layer 3 is sufficiently thin, the buried collector 2 is connected only by diffusion of the N-type polysilicon 10, and the N-type diffusion layer 9 is unnecessary. If the emitter 15 is directly ion-implanted from the main surface of the intrinsic base 14, a channel is formed in the depth direction and it is difficult to make the emitter junction shallower. It is possible to form a shallow emitter 15.

Further, a specific example of Embodiment 2 of the present invention will be described as Example 2. FIGS. 5A to 5C are cross-sectional views illustrating a second embodiment of the present invention in the order of steps. FIG. 5 (a)
As shown in FIG. 7, when the epitaxial layer 3 is sufficiently thin, 0.5 μm, the N-type collector lead 12 is connected to the buried collector 2 only by diffusion of the phosphorus-doped polysilicon 10, so that the N-type diffusion layer 9 by ion implantation is unnecessary. Becomes

Next, as shown in FIG. 5B, the SiO ₂ film 4 is removed, and ion implantation for forming the intrinsic base 14 is performed.
An N-type doped polysilicon 18 (phosphorus or arsenic) is grown at a concentration of about 2 × 10 ²¹ cm ^−3, etched back, and heat-treated to form the emitter 15.

Next, as shown in FIG. 5C, an SiO ₂ film 10 is grown, each contact (emitter / base / collector) area is selectively opened, and an electrode is formed. (Emitter, base, and collector) is completed.

[0038]

As described above, according to the present invention, it is possible to prevent misalignment of a mask by an exposure apparatus.
The dimensional correction due to the displacement becomes unnecessary, and the element can be reduced accordingly.

The reason is that the emitter, base and collector are formed by a self-alignment technique.

Further, since the dimensional method of each region (emitter / base / collector) and the distance between the regions can be controlled in units of several tens of square meters, it is possible to realize a significant reduction in the size of the device.

The reason is that each region (emitter, base,
This is because the distance between the collector and each region is determined by the thickness of the insulator or the polycrystalline silicon.

[Brief description of the drawings]

FIG. 1A is a plan view showing a first embodiment of the present invention,
FIG. 2B is a sectional view taken along line XX ′ of FIG.

FIG. 2 is a cross-sectional view showing Embodiment 1 of the present invention in the order of manufacturing steps.

FIG. 3 is a sectional view showing Embodiment 1 of the present invention in the order of manufacturing steps.

FIG. 4A is a plan view showing a second embodiment of the present invention,
FIG. 4B is a cross-sectional view taken along line XX ′ of FIG.

FIG. 5 is a sectional view showing Example 2 of the present invention in the order of manufacturing steps.

FIG. 6 is a sectional view showing a conventional example in the order of manufacturing steps.

[Explanation of symbols]

1 P-type substrate 2 buried collector 3 epitaxial layer 4,6,16,19 SiO ₂ film _{5 · 8 · 11 Si 3 N} 4 film 7 boron-doped poly silicon 10 phosphorous doped poly silicon 9 N-type diffusion layer 12 N-type collector lead-out 13 P-type external base 14 P-type intrinsic base 15 Emitter 16 Emitter electrode 17 Collector electrode 18 N-type polysilicon

Claims (6)

[Claims] 1. A buried collector region of a reverse conductivity type is formed on a semiconductor substrate, an epitaxial layer of a reverse conductivity type is formed on the substrate, and a nitride film grown on a main surface of the epitaxial layer is selectively removed. A collector extraction, an external base, an intrinsic base, and a method of manufacturing a semiconductor device having an insulating film surrounding a region where an emitter is to be formed, wherein an oxide film serving as an emitter opening region is grown below the nitride film; Selectively etching and etching back the nitride film; growing a conductive type polycrystalline silicon in the epitaxial layer, etching back; and growing a nitride film and etching back. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein ion implantation of a reverse conductivity type is performed from said epitaxial layer to reach a buried collector of a reverse conductivity type. 3. A process of growing polycrystalline silicon of the opposite conductivity type on the main surface of the epitaxial layer, performing an etch-back process, growing a nitride film and an oxide film for planarization, performing an etch-back process, and performing a heat treatment. Forming a collector leading region of the opposite conductivity type and an external base of the one conductivity type at the same time; and removing an oxide film serving as the emitter opening region to form an intrinsic base of the one conductivity type. 3. The method for manufacturing a semiconductor device according to claim 1, wherein 4. The method of manufacturing a semiconductor device according to claim 1, wherein an emitter of the opposite conductivity type is formed from the main surface of the intrinsic base by ion implantation. 5. The method according to claim 1, wherein polycrystalline silicon of the opposite conductivity type is grown on the intrinsic base main surface, etched back, and an emitter is formed by heat treatment. 6. An insulating film is grown on the main surface of the semiconductor device,
6. The method according to claim 4, wherein an opening window selectively serving as an emitter / base / collector is formed, and an emitter electrode, a base electrode, and a collector electrode are formed, respectively.