JPH11149277A - Driving method of liquid crystal display device and driving circuit thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hold high display quality without causing deterioration or flicker of a liquid crystal even if dislocation is generated in the wiring pattern of a switching element by setting offset voltage between the center potential of receptive signal voltage and drive voltage, and making the offset voltage capable of being changed over. SOLUTION: A positive polarity signal is formed from an image signal VD by a positive polarity signal making circuit 2, a negative polarity signal is formed from the image signal VD by a negative polarity signal making circuit 3, and the positive and negative polarity signals are added to an output circuit 4. In the positive polarity signal making circuit 2, when the positive polarity signal is formed from the image signal VD, according to either of respective potentials VC11, VC12 from a changeover circuit 5, dislocation of the center potential of the image signal VD is changed to anyone of respective offset voltages. In the negative polarity signal making circuit 3, according to either of respective potentials VC21, VC22 from a changeover circuit 6, dislocation of the center potential of the image signal VD is changed to anyone of respective offset voltages.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of a display device and a driving circuit thereof, and more particularly, to a TFT (Thin Film T).
The present invention relates to a driving method of an active matrix type liquid crystal display device using a ransistor element or the like and a driving circuit thereof.

[0002]

2. Description of the Related Art As is well known, there is an active matrix type liquid crystal display device. In this active matrix type liquid crystal display panel, a pair of substrates are arranged to face each other, and a liquid crystal is sandwiched between these substrates. In addition, a common electrode is provided on one substrate, and a plurality of signal lines and a plurality of scanning lines are arranged on the other substrate so as to be orthogonal to each other, and for each region defined by each signal line and each scanning line. , Each pixel electrode is provided, and each TFT element is connected to these pixel electrodes. Each scan line is sequentially scanned, and each time, each TFT element along the scan line is turned on through the scan line, and a signal voltage is applied along each scan line through each signal line and each turned on TFT element. Apply to each pixel electrode. When the scanning of each scanning line is completed, each signal voltage is applied to all the pixel electrodes, and one image is displayed.

In a liquid crystal display panel of a color display,
Red (R), green (G), and blue (B) color filters are superposed on each pixel electrode to form each color pixel of each color.

As an arrangement method of each color pixel, a stripe arrangement, a mosaic arrangement, and a delta arrangement are well known. The sequences are shown in FIGS. 7 (a), (b) and (c). Each of these arrangements has its own characteristics. In general, a delta arrangement is used for a small liquid crystal display device having a small number of pixels. This is because, in the delta arrangement, the images in the adjacent rows work so as to interpolate with each other, so that the horizontal resolution is apparently improved.

FIG. 8 is a diagram showing the overall configuration of a conventional delta-aligned liquid crystal display device. In FIG. 8, 100 is T
FT-type liquid crystal display panels 101 and 102 are a gate driver and a data driver for driving the liquid crystal display panel;
3 is a gate line (scanning line), 104 is a source line (signal line), 105 is a TFT element, and 106 is a pixel electrode.
Although not shown, a common electrode is provided to face the liquid crystal display panel 100.

In the liquid crystal display panel 100, a plurality of gate lines 103 are connected to a gate driver 101, a plurality of source lines 104 are connected to a source driver 102, and each intersection of each gate line 103 and each source line 104. Each TFT element 105 is formed, and each TFT element 105 is provided with each pixel electrode 10.
6 are connected.

In the delta arrangement, a connection structure between a source line and a pixel shown in FIG. 9 other than that shown in FIG. 8 is known. The difference between FIG. 8 and FIG. 9 is the correspondence between the source line 104 and the color filter. In the connection structure of FIG. 8, two colors (for example, R and G)
9 are assigned to the color filters of FIG.
In this connection structure, only one color (for example, R) color filter is allocated to the source line 104. FIG.
In the case of this connection structure, it is necessary to switch the data signal supplied to the source line 104 according to each color signal, and usually includes a color switching circuit. In contrast, in the case of the connection structure in FIG. 9, a data signal can be supplied to the source line 104 without switching the color signal. Japanese Patent Application Laid-Open No. Sho 60-218626 ("Color liquid crystal display device", invented by Hamada) discloses a prior patent relating to a device of a delta arrangement of a type in which only one color (for example, R) color filter is allocated to the source line 104. In addition, the applicant is Sharp Corporation. In this document, a configuration of a liquid crystal display device as shown in FIG. 9 is proposed, and details concerning a driving method thereof are described.

On the other hand, an equivalent circuit of each pixel is shown in FIG.
Is represented as In the figure, CLC is called a pixel capacitance and is a capacitance determined by a liquid crystal which is a dielectric between the pixel electrode 106 and the common electrode 107. The potential difference between both electrodes of this capacitance is a voltage actually applied to the liquid crystal. Becomes Further, Cs is an auxiliary capacitor, and Cgd is a TFT element 1 which is a switching element.
The stray capacitance caused by the gate electrode G and the drain electrode D in FIG.

To write data in each pixel, after turning on the TFT element 105, a required voltage is applied to the pixel electrode 106 via the source line 104 to charge the pixel capacitance CLC and the auxiliary capacitance Cs. After these capacitors CLC and Cs are charged, even if the TFT element 105 is turned off, the charged electric charge is stored in the pixel electrode 106, and the liquid crystal between the pixel electrode 106 and the common electrode 107 has a predetermined charge. Voltage continues to be applied.

When a DC voltage is continuously applied to the liquid crystal for a long period of time, its characteristics deteriorate. Therefore, so-called AC driving is performed so that a positive and a negative voltage are alternately applied to the pixel electrode 106.

There are various structures for forming the auxiliary capacitance Cs. Here, the auxiliary capacitance Cs is formed between the pixel electrode 106 and the common electrode 107.

Referring to FIG. 8, a gate driver 101 is shown.
Controls ON / OFF of each TFT element 105 for each row (corresponding to each gate line 103) of the liquid crystal display panel 100. For example, each of the gate lines 103 is sequentially selected, and An ON signal is supplied to each of the TFT elements 105 along the line, and these TFT elements 105 are turned on.

The data driver 102 controls the source line 1 of each column.
A required signal voltage is applied to each of the pixel electrodes 106 through an external video signal 04. For each source line 104, an external video signal VD (R signal is VD (R) and G signal is VD (R).
The signals of (G) and B are VD (B). ) Are sampled to form respective signal voltages, and these signal voltages are supplied to each source line 104.

The data driver 102 is configured, for example, as shown in FIG. 11 when receiving an analog video signal VD.

In FIG. 11, reference numeral 110 denotes a shift register, and 111 denotes a sample and hold circuit. The shift register 110 forms each sampling pulse TSMP based on a data start pulse DSP and a data clock DCK input from the outside. Each sampling pulse TSMP is supplied to each sample and hold circuit 111 in order from the first column. Each sample-and-hold circuit 111 samples and holds an external video signal VD in response to each sampling pulse TSMP, and then applies each signal voltage to each source line 104.
Output to

FIG. 12 shows a specific example of the sample hold circuit 111. In the figure, a switch ASWSMP is controlled by a sampling pulse TSMP.
Is on, the video signal VD is
And the sample capacitor CSMP is charged. Subsequently, the switch ASW is output by the output pulse OE.
H is controlled, and when the switch ASWH is on, the charge charged in the sample capacitor CSMP is transferred to the hold capacitor CH. And hold capacitor CH
Is output to the source line 104 through the buffer Amp as a signal voltage. Therefore, the data held by the sample and hold circuit 111 is updated at regular intervals, and a signal voltage corresponding to the updated data is output to the source line 104.
Output period.

In a liquid crystal display device of a delta arrangement in which only one color (for example, R) color filter is allocated to the source line 104, the sampling of the video signal VD is usually performed in comparison with the odd rows. The sampling timing of the even-numbered rows is shifted by 1.5 pixels.
This is because the positional relationship of each pixel along one source line 104 is shifted by 1.5 pixels between odd rows and even rows. To solve this problem, a start pulse delay circuit 112 is provided as shown in FIG.
12, the data start pulse DSP is controlled to generate a shift of 1.5 pixels between the odd-numbered row and the even-numbered row.

FIG. 13 shows the driving voltage VCO of the common electrode 107.
3 shows a configuration of a common electrode drive circuit for forming M. Regarding the drive voltage VCOM of the common electrode 107, there are two types, that is, the case of DC drive and the case of AC drive.

In the common electrode driving circuit 113 shown in FIG. 13, two DC voltage sources 113-1 and 113-1 are output by an output circuit 113a.
The voltage from 113-2 is alternately output.
The switching by the output circuit 113a has a cycle (for example, synchronized with the AC drive of the video signal VD) according to the control signal C from the outside, and thus a drive voltage VCOM for AC drive can be obtained. .

When the driving voltage VCOM is to be DC-driven, the common electrode driving circuit 113 shown in FIG. 13 requires only one DC voltage source and does not need the control signal C.

The output circuit 113a outputs the central potential of the drive voltage VCOM for AC driving in accordance with the external potential Vc.
Alternatively, the drive voltage VCOM for DC drive is determined.

FIG. 14 shows the configuration of a polarity switching circuit necessary for AC driving. Polarity switching circuit 114 shown in FIG.
Is provided in front of (or inside) the data driver 102 for AC driving the video signal VD so that positive and negative voltages are alternately applied to the pixel electrode 106 of the liquid crystal. .

The operation of the polarity switching circuit 114 will be briefly described. In the polarity switching circuit 114, the video signal VD is converted into a positive signal generation circuit 114-1 and a negative signal generation circuit 11.
4-2, a positive signal generation circuit 114-1 forms a positive signal from the video signal VD, and a negative signal generation circuit 114-2 forms a negative signal from the video signal VD. A positive signal and a negative signal are applied to the output circuit 114a. The output circuit 114a outputs a positive polarity signal generation circuit 114
-1 from positive signal and negative signal generation circuit 114-2
Is switched and output as a video signal VD.

The positive signal generating circuit 114-1 and the negative signal generating circuit 114-2 are connected to external potentials Vc1,
The central potential of the video signal VD (the central potential combining the positive and negative signals) is determined according to Vc2.

FIG. 15 shows the input / output relationship of the polarity switching circuit 114. The graph of FIG. 15A shows the video signal V
In the case where only D is driven by AC and the drive voltage VCOM of the common electrode 107 is driven by DC, the graph of FIG.
The case where both the video signal VD and the drive voltage VCOM of the common electrode 107 are AC driven is shown.

Here, the center potential of the video signal VD and the drive voltage VCOM of the common electrode 107 (when the drive voltage VCOM is DC driven) are the same, or the center potential of the video signal VD and the center potential of the drive voltage VCOM (drive On the assumption that the voltage VCOM is AC-driven).
4 shows an input / output relationship.

In the DC drive shown in FIG. 15A, the positive signal is proportional to the video signal VD and the negative signal is based on the center potential of the video signal VD and the drive voltage VCOM of the common electrode 107. It is inversely proportional to the video signal VD.

In the AC drive shown in FIG. 15B, the signal of the positive polarity is proportional to the video signal VD and the signal of the negative polarity is determined based on the drive voltage VCOM at the time of outputting the signal of the positive polarity. The signal of negative polarity is inversely proportional to the video signal VD with reference to the drive voltage VCOM at the time of output.

Normally, when forming a positive polarity signal and a negative polarity signal from the video signal VD, consideration is given to the fact that the relationship between the voltage applied to the liquid crystal and the transmittance of the liquid crystal is non-linear. Since it is created, the input / output relationship of the polarity switching circuit 114 is not linear, but it has nothing to do with the essence of this patent, so we will not discuss it this time.

[0030]

By the way, the pixel electrode 1
The voltage applied to the transistor 06 includes a potential change ΔV (ΔV = ΔVG × Cgd / (Cgd + CLC + C) caused by the stray capacitance Cgd at the timing when the TFT element 105 is turned on from off.
s)). Where △ VG is T
This is the potential difference of the gate signal input to the gate electrode G of the FT element 105 (that is, the potential difference of the gate signal when the TFT element 105 is turned on and when it is turned off).

This potential variation ΔV is obtained by applying either a positive signal or a negative signal to the pixel electrode 106.
Since they are generated in the same direction (positive or negative direction), the center potential of the video signal VD and the drive voltage VCOM of the common electrode 107 (when the drive voltage VCOM is DC driven), or the center potential of the video signal VD and the drive voltage It is conceivable that an offset voltage ΔVoff having the same magnitude as the potential fluctuation ΔV for canceling the potential fluctuation ΔV is multiplied between the center potentials of VCOM (when the driving voltage VCOM is AC-driven).

FIGS. 16 and 17 are timing charts showing signals in a liquid crystal display panel in which only the video signal VD is AC-driven and the driving voltage VCOM of the common electrode 107 is DC-driven.

Here, a row inversion driving method for inverting the polarity of the video signal VD to plus or minus for each row (one gate line 103) of the liquid crystal display panel 100 is illustrated. Also, the polarity of the video signal VD of each row is inverted to positive or negative for each frame (vertical period).

First, in FIG. 16, (a) shows a timing waveform of the horizontal synchronizing signal Hsync, and (b) synchronizes with the horizontal synchronizing signal Hsync with respect to the voltage VCOM of the common electrode 107 for each row. The video signal VD to be inverted is shown. The center potential of the video signal VD and the drive voltage VCOM of the common electrode 107
Is applied with an offset voltage ΔVoff.
(C) shows the timing waveform of the sampling pulse TSMP (m) in the m-th column, and (d) shows the sampling pulse T SMP in the m-th column.
The signal waveform of the sample capacitor CSMP in the sample-and-hold circuit 111 in the m-th column in which the video signal VD is charged in response to SMP (m) is shown, and (e) shows the timing waveform of the output pulse OE. The output pulse OE is normally supplied to all the sample and hold circuits 111 at the same timing. Further, (f) shows the case where the sample capacitor CSMP (m) in the m-th column is set to m in response to the output pulse OE.
The signal waveform moved to the hold capacitor CH (m) in the column is shown, and (g) and (h) show the gate signal VG in the n-th row.
(N) and the timing waveform of the gate signal VG (n + 1) in the (n + 1) th row are shown. (I) and (j) denote the n-th row and n + 1 from the m-th column hold capacitor CH (m).
The signal voltage applied to each pixel electrode 106 in the row is shown.

Here, when the gate signal VG switches from on to off, the voltage of the pixel electrode 106 changes to the stray capacitance Cgd.
Is caused by the potential difference ΔVoff because the potential difference of the offset voltage ΔVoff is multiplied in advance between the center potential of the video signal VD and the driving voltage VCOM of the common electrode 107. After that, the gate signal VG
(After switching from ON to OFF), an appropriate signal voltage is applied to the pixel electrode 106.

FIG. 17 shows a part of each signal in FIG. 16 over two vertical periods. As described above, one row (one gate line 103) of the liquid crystal display panel 100
The polarity of the video signal VD is inverted to positive and negative for each frame, and the polarity of the video signal VD for each row is inverted to positive and negative for each frame (vertical period). Therefore, the voltages applied to the pixel electrodes 106 in the n-th row and the (n + 1) -th row are mutually inverted, and when viewed in each vertical period, the n-th row in the first vertical period and the next vertical period The voltages applied to the pixel electrodes 106 of the (n) th and (n + 1) th rows are inverted. In any case, a potential change ΔV occurs from the timing when the TFT element 105 is turned on to the time when it is turned off.

Here, the offset voltage ΔVo is applied between the central potential of the video signal VD and the drive voltage VCOM of the common electrode 107.
Since the potential difference of ff is applied in advance, an appropriate voltage is finally applied to the pixel electrode 106.

Next, FIGS. 18 and 19 show the video signal VD
6 is a timing chart showing signals in a liquid crystal display panel in which a driving voltage VCOM of a common electrode 107 is AC-driven.

Since the timing of each signal is basically the same as in FIGS. 16 and 17, only the differences will be described. As shown in FIG. 18B, a potential difference of the offset voltage ΔVoff is multiplied in advance between the center potential of the video signal VD and the center potential of the drive voltage VCOM of the common electrode 107. FIG. 18B shows the drive voltage VCOM of the common electrode 107 that is AC-driven in synchronization with the video signal VD. As shown in FIGS. 18 (i) and (j), the gate signal VG
Is switched from on to off, a potential change ΔV occurs in the voltage of the pixel electrode 106, but a potential difference of the offset voltage ΔVoff between the center potential of the video signal VD and the center potential of the drive voltage VCOM of the common electrode 107. Is applied beforehand, after the potential variation ΔV occurs (the gate signal VG
(After switching from ON to OFF), an appropriate voltage is applied to the pixel electrode 106.

Since the drive voltage VCOM of the common electrode 107 is an AC drive, the potential applied to the pixel electrode 106 is changed accordingly, but the potential difference between the pixel electrode 106 and the common electrode 107 does not change. .

FIG. 19 shows a part of each signal in FIG. 18 over two vertical periods. Pixel electrode 10
Considering an ideal state, the potential difference between 6 and the common electrode 107 preferably does not change until a voltage is newly applied to the pixel electrode 106 in the next vertical period.

Here, as a specific method for realizing the above-mentioned matter, for example, the polarity switching circuit 11 shown in FIG.
4 are appropriately set, and the common electrode 10
7, the driving voltage VCOM (when the driving voltage VCOM is DC-driven) or the central potential of the driving voltage VCOM (the driving voltage VCOM
, The center potential of the video signal VD is increased by an offset voltage ΔVoff, or conversely,
The potential Vc of the common electrode driving circuit 113 shown in FIG. 13 is appropriately set so that the driving voltage VCOM of the common electrode 107 (when the driving voltage VCOM is DC-driven) or the driving voltage VCOM is higher than the center potential of the video signal VD. Center potential (drive voltage VC
It is conceivable to lower the OM by AC driving) by the offset voltage ΔVoff.

As a prior patent relating to this type of driving method, there is, for example, Japanese Patent Application Laid-Open No. 5-35226 (“Liquid Crystal Display Device”, filed by Seiko Epson Corporation).
This document includes the central potential of the video signal VD and the common electrode 10.
7 (when the driving voltage VCOM is DC driven), or the center potential of the video signal VD and the driving voltage VCOM.
A method is described in which a potential difference is applied between the central potentials (when the driving voltage VCOM is driven by AC). As a result, a DC voltage is applied to deteriorate the liquid crystal or to cause display unevenness. It is described that a highly reliable liquid crystal display device with high display quality can be achieved without performing the above.

However, the source line 1 shown in FIG.
When a liquid crystal display device of a delta arrangement of a type in which only one color filter (for example, R) is assigned to 04 is employed, the following problems occur.

FIG. 20 shows a layout near a pixel in the liquid crystal display device of FIG. In FIG. 20, a TFT element 105 includes a gate electrode G connected to a gate line 103, a source electrode S connected to a source line 104, a pixel 1
The drain electrode D is connected to a drain electrode D, for example, an active layer 108 made of amorphous silicon.

In this liquid crystal display device, for example, in the n-th gate line 103, the source line 1
The TFT element 105 on the right side of the source line 104
, The TFT element 105 on the left side of the source line 104 is connected to the source line 104 in the (n + 1) th row.

As described above, for each row, the left and right TFT elements 1
05 is alternately connected to the source line 104,
For example, in a photolithography process of forming a pattern of the gate electrode G in the manufacturing process, the pattern of the gate electrode G may be shifted left or right with respect to the source electrode S and the drain electrode D, and the n-th row and the (n + 1) -th row The stray capacitance Cgd generated by the gate electrode G and the drain electrode D and the stray capacitance Cgs generated by the gate electrode G and the source electrode S of the TFT element 105 differ between eyes. In other words, at least the stray capacitance C
gd is different.

Since the floating capacitance Cgd causes the potential fluctuation ΔV as described above, the potential fluctuation ΔV of the pixel electrode 106 also changes with the fluctuation of the floating capacitance Cgd.

The reason why the stray capacitance Cgd differs between an odd-numbered row and an even-numbered row will be briefly described with reference to FIG.

FIGS. 21 (a) to 21 (c) show inverted staggered T
FIG. 21 is a plan view of the FT element 105, and FIGS.
FIG. 21 is a cross-sectional view taken along the line CC ′ in FIGS. 21 (a) to 21 (c).

Here, the stray capacitance Cgd of the TFT element 105 in the nth row is represented by Cgd (n), and the stray capacitance Cgs is represented by Cgs.
(N) The stray capacitance Cgd of the TFT element 105 in the (n + 1) th row
Is the stray capacitance Cgd (n + 1), and the stray capacitance Cgs is Cgs (n +
1). The floating capacitance Cgd corresponds to the area where the gate electrode G and the drain electrode D overlap, and the floating capacitance Cgs corresponds to the area where the gate electrode G and the source electrode S overlap. Further, 120 is a gate insulating film, 121 is TF
It is a T substrate.

First, as shown in FIGS. 21 (a) and 21 (d), when there is no shift in the wiring pattern, the stray capacitance Cgd
(N) and the stray capacitance Cgs (n) are equal to each other, and the stray capacitance Cgd (n) in the nth row and the stray capacitance Cgd (n +
1) are also equal to each other.

However, for example, in FIG.
As shown in (e), when the patterns of the gate line 103 and the gate electrode G in the n-th row are shifted to the left with respect to the source electrode S and the drain electrode D, the stray capacitance Cgd (n) decreases, The stray capacitance Cgs (n) increases. At this time,
In the (n + 1) th row, as shown in FIGS. 21C and 21F, the stray capacitance Cgd (n + 1) increases, and the stray capacitance Cgs (n)
+1) becomes smaller. That is, Cgd (n) <Cgd (n + 1) due to the shift of the wiring pattern, and the n-th row and n
The stray capacitance Cgd becomes non-uniform between the + 1st row.

As described above, between the n-th row and the (n + 1) -th row, the TFT
When a difference occurs in the stray capacitance Cgd of the element 105, the potential fluctuation ΔV of the pixel electrode 106 caused by the stray capacitance Cgd differs between the n-th row and the (n + 1) -th row. Between the center potential of the signal VD and the drive voltage VCOM of the common electrode 107 (when the drive voltage VCOM is DC driven) or between the center potential of the video signal VD and the center potential of the drive voltage VCOM (when the drive voltage VCOM is AC driven) ), Even if a constant offset voltage ΔVoff is applied, the potential fluctuation ΔV cannot be surely canceled. As a result, the pixel electrode 1
06, a DC voltage is applied, and the liquid crystal deteriorates,
Flicker is generated, and the display quality is significantly reduced.

Therefore, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to prevent the liquid crystal from deteriorating and flickering even if the wiring pattern of the switching element is shifted. An object of the present invention is to provide a driving method and a driving circuit of a liquid crystal display device which can maintain high display quality.

[0056]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method in which a plurality of scanning lines and a plurality of signal lines are arranged so as to intersect with each other and each area defined by each scanning line and each signal line. In each case, each pixel electrode is provided, and each pixel electrode is provided with a respective switching element, and for each signal line, each pixel electrode on both sides of the signal line is selectively passed through the respective switching element. Connected to the signal line, a common electrode is arranged to face each pixel electrode, and while applying each signal voltage from each signal line to each pixel electrode via each switching element, a driving voltage is applied. A method of driving a liquid crystal display device applied to the common electrode, wherein an offset voltage is set between a central potential of each signal voltage and the drive voltage, and the offset voltage can be switched.

According to such a configuration, it is possible to switch the offset voltage between the central potential of each signal voltage and the drive voltage, so that it is possible to respond to the potential fluctuation ΔV of the pixel electrode caused by the stray capacitance Cgd of the switching element. By switching the offset voltage, the potential fluctuation ΔV of the pixel electrode can always be canceled.

When the drive voltage is an AC voltage, an offset voltage is set between the center potential of each signal voltage and the center potential of the drive voltage.

The offset voltage may be switched by switching the center potential of each signal voltage.

Further, according to the present invention, a plurality of scanning lines and a plurality of signal lines are arranged so as to intersect with each other, and a pixel electrode is provided for each region defined by each scanning line and each signal line.
Each pixel electrode is provided with a respective switching element, and for each signal line, each pixel electrode on both sides of the signal line is selectively connected to the signal line via a respective switching element. A common electrode is disposed so as to face each other, and while applying each signal voltage from each of the signal lines to each of the pixel electrodes via each of the switching elements, a drive voltage is applied to the common electrode. A driving circuit, comprising: first switching means for switching a central potential of each signal voltage, wherein switching of the central potential of each signal voltage by the first switching means causes the switching between the central potential of each signal voltage and the driving voltage. The offset voltage can be switched.

In this case as well, the offset voltage can be switched by switching the center potential of each signal voltage by the first switching means. Therefore, the offset voltage can be switched according to the potential variation ΔV of the pixel electrode caused by the stray capacitance Cgd of the switching element. By switching this offset voltage, the potential fluctuation ΔV of the pixel electrode can always be canceled.

When the drive voltage is an AC voltage, an offset voltage is set between the center potential of each signal voltage and the center potential of the drive voltage.

The first switching means may switch the central potential of the signal voltage every time each scanning line is scanned. In this case, it is assumed that the stray capacitance Cgd of the switching element is different for each scanning line, and the potential variation ΔV of the pixel electrode is different for each scanning line. , By switching the central potential of the signal voltage,
The potential fluctuation ΔV of the pixel electrode is always offset.

The first switching means may have a plurality of preset potentials as a central potential of each signal voltage, and selectively switch these preset potentials.

The first switching means may have at least two preset potentials as a central potential of each signal voltage, and may selectively switch each preset potential each time each scanning line is scanned. . In this case, it is assumed that the stray capacitance Cgd of the switching element is different between the odd-numbered and even-numbered rows of each scanning line, and that the potential variation ΔV of the pixel electrode is different between the odd-numbered and even-numbered rows of each scanning line. By switching the central potential of the signal voltage between the odd and even rows of the scanning line, the potential variation ΔV of the pixel electrode is always canceled.

The first switching means has at least two preset potentials as a central potential of each signal voltage, and
Each of the preset potentials may be selectively switched every vertical scanning period. In this case, it is assumed that the polarity of each signal voltage is inverted every vertical scanning period, and the central potential of the signal voltage is switched with the inversion of the polarity.

The center potential of each signal voltage may be adjustable.

[0068]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Basic Principle of the Present Invention) First, FIG.
, A delta liquid crystal display device of a type in which a color filter of only one color (for example, R) is allocated to a source line 104, an equivalent circuit of a pixel as shown in FIG. 10, and a data driver as shown in FIG. The basic principle of the present invention will be described on the premise of a sample hold circuit 111 as shown in FIG.

In the basic type of the present invention, the potential variation ΔV (ΔV = ΔVG × Cgd / (Cgd + CLC + C) caused by the stray capacitance Cgd is obtained at the timing when the TFT element 105 is turned off.
s)) occurs and the stray capacitance Cgd is not constant (that is, the potential variation ΔV is not constant), the video signal VD
Of the common electrode 107 and the drive voltage VCOM of the common electrode 107 (when the drive voltage VCOM is DC-driven) or the video signal VD
Between the center potential of the driving voltage VCOM and the center potential of the driving voltage VCOM (when the driving voltage VCOM is AC-driven), the offset voltage ΔVoff is multiplied by the offset voltage ΔVoff, and the potential variation ΔV
Is changed in the same manner as described above, and this potential fluctuation ΔV is always canceled out.

FIG. 1 and FIG. 2 show signals in a liquid crystal display device to which the present invention is applied, in which only the video signal VD is AC-driven and the driving voltage VCOM of the common electrode 107 is DC-driven. ing.

Here, a row inversion driving method in which the polarity of the video signal VD is inverted between positive and negative for each row (one gate line 103) of the liquid crystal display panel 100 is illustrated. Also, the polarity of the video signal VD of each row is inverted to positive or negative for each frame (vertical period).

First, in FIG. 1, (a) shows a timing waveform of the horizontal synchronizing signal Hsync, and (b) synchronizes with the horizontal synchronizing signal Hsync with respect to the voltage VCOM of the common electrode 107 for each row. The video signal VD to be inverted is shown. Between the center potential of the video signal VD and the drive voltage VCOM of the common electrode,
The offset voltages △ Voff1 and △ Voff2 are switched and applied for each row. (C) shows the timing waveform of the sampling pulse TSMP (m) in the m-th column,
(D) shows the signal waveform of the sample capacitor CSMP in the sample-and-hold circuit 111 of the m-th column in which the video signal VD is charged in response to the sampling pulse TSMP (m) of the m-th column, and (e) shows the output pulse. 4 shows an OE timing waveform. The output pulse OE is normally supplied to all the sample and hold circuits 111 at the same timing. Further, (f) shows a signal waveform moved from the mth column sample capacitor CSMP (m) to the mth column hold capacitor CH (m) in response to the output pulse OE, and (g) and (h) show the signal waveform. The timing waveforms of the gate signal VG (n) on the n-th row and the gate signal VG (n + 1) on the (n + 1) -th row are shown. (I) and (j) show the pixel electrodes 10 in the n-th row and the (n + 1) -th row from the hold capacitor CH (m) in the m-th column.
6 shows the signal voltage applied.

Here, when the gate signal VG switches from on to off, the stray capacitance C
A potential variation ΔV due to gd occurs, and the n-th row and n
There is a difference in the stray capacitance Cgd of the TFT element 105 between the + 1st row and the pixel electrode 106 due to the stray capacitance Cgd.
Is different between the nth row and the (n + 1) th row, and two potential fluctuations ΔV1 and ΔV2 occur.

In the present invention, as is clear from FIG. 1B, any one of the offset voltages ΔVoff1 and ΔVoff2 is applied between the center potential of the video signal VD and the drive voltage VCOM of the common electrode. The offset voltages ΔVoff1 and ΔVoff2 are switched for each row. On the other hand, the magnitude of the offset voltage {Voff1 is equal to the potential fluctuation of the n-th row}.
The magnitude of the other offset voltage ΔVoff2 is equal to the potential fluctuation ΔV2 of the (n + 1) th row. Therefore, even if the potential fluctuations ΔV1, ΔV2 of the n-th row and the (n + 1) th row are different, the potential fluctuations ΔV1, ΔV2 can be offset by the offset voltages ΔVoff1, ΔVoff2, and the gate signal VG is turned on. After switching from to OFF, an appropriate signal voltage is applied to the pixel electrode 106.

FIG. 2 shows a part of each signal in FIG. 1 over two vertical periods. As mentioned earlier,
The polarity of the video signal VD is inverted to positive and negative for each row (one gate line 103) of the liquid crystal display panel 100, and the polarity of the video signal VD for each row is inverted to positive and negative for each frame (vertical period). I have. Therefore, the voltages applied to the pixel electrodes 106 in the n-th row and the (n + 1) -th row are mutually inverted, and when viewed in each vertical period, the n-th row in the first vertical period and the next vertical period The voltages applied to the pixel electrodes 106 of the (n) th and (n + 1) th rows are inverted. In any case, any one of the potential fluctuations ΔV1 and ΔV2 occurs for each row at the timing of turning on and off the TFT element 105, and the potential fluctuations ΔV1 and ΔV2 occur alternately for each row. .

Here, the offset voltages ΔVoff1 and ΔVoff2 are applied between the central potential of the video signal VD and the drive voltage VCOM of the common electrode so that the potential fluctuations ΔV1 and ΔV2 cancel each other.
, The appropriate signal voltage is applied to the pixel electrode 106 after the gate signal VG switches from on to off.

FIGS. 3 and 4 show a liquid crystal display device to which the present invention is applied.
5 is a timing chart showing signals in a liquid crystal display device that drives both the driving voltages VCOM of the liquid crystal display device in AC.

Here, since the timing of each signal is basically the same as in FIGS. 1 and 2, only different points will be described. As shown in FIG. 3B, the driving voltage VCOM of the common electrode 107 is changed for each row in synchronization with the horizontal synchronization signal Hsync.
5 shows an inverted video signal VD. Between the center potential of the video signal VD and the center potential of the drive voltage VCOM of the common electrode, each offset voltage ΔVoff1, ΔVoff2
Is switched and hung. FIG. 3B 'shows the drive voltage VCOM of the common electrode 107 which is AC-driven in synchronization with the video signal VD, and the center potential of the drive voltage VCOM. As shown in FIGS. 3 (i) and 3 (j), when the gate signal VG switches from on to off, the voltage of the pixel electrode 106 has a potential variation ΔV caused by the stray capacitance Cgd, and n rows There is a difference in the stray capacitance Cgd of the TFT element 105 between the first and n + 1th rows, and the potential change ΔV of the pixel electrode 106 caused by the stray capacitance Cgd differs between the nth and n + 1th rows. Although potential fluctuations ΔV 1 and ΔV 2 occur, the central potential of the video signal VD and the driving voltage VCOM of the common electrode 107 are generated.
Between the center potentials Voff1 and Voff2
Are previously multiplied, each potential variation ΔV
1, after the occurrence of ΔV2 (after the gate signal VG switches from on to off), an appropriate voltage is applied to the pixel electrode 10
6 will be applied.

Since the drive voltage VCOM of the common electrode 107 is an AC drive, the potential applied to the pixel electrode 106 is changed accordingly, but the potential difference between the pixel electrode 106 and the common electrode 107 does not change. .

FIG. 4 shows a part of each signal in FIG. 3 over two vertical periods. In an ideal state, the potential difference between the pixel electrode 106 and the common electrode 107 does not change until a voltage is newly applied to the pixel electrode 106 in the next vertical period.

(Embodiment) FIG. 5 shows a polarity switching circuit according to an embodiment of the driving circuit of the present invention. The polarity switching circuit 1 of this embodiment is used in place of the polarity switching circuit of FIG. This polarity switching circuit 1 includes a liquid crystal display device of a delta arrangement of a type in which a color filter of only one color (for example, R) is allocated to a source line 104 as shown in FIG. 9, an equivalent circuit of pixels as shown in FIG. It operates on the premise of a data driver as shown in FIG. 11 and a sample and hold circuit 111 as shown in FIG. 12, and is provided before (or inside) the data driver 102 and has a pixel electrode 1
The input video signal VD is AC-driven so that positive and negative voltages are alternately applied to 06.

The input / output relationship of the polarity switching circuit 1 is substantially the same as that shown in the graphs of FIGS. 15 (a) and 15 (b).
The difference is that it is shifted by one of Voff2.

As shown in FIG. 5, in the polarity switching circuit 1, a video signal VD is input to a positive signal generating circuit 2 and a negative signal generating circuit 3, and the positive signal generating circuit 2 converts the video signal VD into a positive signal. A negative signal is formed from the video signal VD by the negative signal generation circuit 3 while a positive signal and a negative signal are applied to the output circuit 4. The output circuit 4 receives an external control signal C
In accordance with 1, the positive signal from the positive signal generating circuit 2 and the negative signal from the negative signal generating circuit 3 are switched and output as the video signal VD.

The switching circuit 5 receives the potentials Vc11 and Vc12 and responds to the control signal C2 to switch the potentials Vc11 and Vc1.
2 is output to the positive polarity signal generation circuit 2.
The positive-polarity signal generation circuit 2 generates the positive-polarity signal from the video signal VD and outputs the potentials Vc11,
The shift of the center potential of the video signal VD is switched to one of the offset voltages ΔVoff1 and ΔVoff2 in accordance with one of Vc12. The switching circuit 6 is connected to each potential Vc21,
Vc22 is input, and one of the potentials Vc21 and Vc22 is output to the negative polarity signal generation circuit 3 in response to the control signal C2. When forming a negative polarity signal from the video signal VD, the negative polarity signal generation circuit 3 determines the offset of the center potential of the video signal VD according to one of the potentials Vc21 and Vc22 from the switching circuit 6 by using each offset voltage. It has been switched to either ΔVoff1 or ΔVoff2.

As a result, the output circuit 4 alternately outputs a positive signal whose center potential is shifted by the offset voltage ΔVoff1 and a negative signal whose center potential is shifted by the offset voltage ΔVoff2 for each row. A positive signal whose center potential is shifted by an offset voltage △ Voff2 and a negative signal whose center potential is shifted by an offset voltage △ Voff1 are alternately output for each row.

Here, focusing on each row of the liquid crystal display panel 100, for example, in one vertical period (frame),
A positive signal whose center potential is shifted by an offset voltage 正極 Voff1 is applied to each odd-numbered pixel electrode 106, and a negative signal whose center potential is shifted by an offset voltage △ Voff2 is applied to each even-numbered pixel electrode 106. Between the center potential of the video signal VD and the drive voltage VCOM of the common electrode 107 (when the drive voltage VCOM is DC-driven), or the center potential of the video signal VD and the drive voltage VCOM.
(When the drive voltage VCOM is AC driven), the offset voltages ΔVoff1 and ΔVoff2 can be switched and applied.

In the next one vertical period, the central potential is applied to the pixel electrodes 106 of each odd-numbered row by the offset voltage ΔV.
A signal of negative polarity shifted by off1 is applied, and the center potential is applied to the pixel electrodes 106 of each even-numbered row by an offset voltage △.
A positive polarity signal shifted by Voff2 can be added,
The central potential of the video signal VD and the drive voltage VC of the common electrode 107
Each offset voltage （Voff1, 1Voff2 is switched between OM (when driving voltage VCOM is DC driven) or between the center potential of video signal VD and the center potential of driving voltage VCOM (when driving voltage VCOM is AC driven). Can be hung.

FIG. 6 shows a specific example of the polarity switching circuit of FIG. In FIG. 6, a switch SW12 applies one of the potentials Vc11 and Vc12 to an operational amplifier OP1 in response to a control signal C2. The switch SW22 applies one of the potentials Vc21 and Vc22 to the operational amplifier OP2 in response to the control signal C2. Furthermore, each operational amplifier OP1,
OP2 receives the video signal VD from the input terminal Vin.

The operational amplifier OP1 includes resistors R11, R12,
R13 and R14 are connected, and the difference between the video signal VD and one of the potentials Vc11 and Vc12 is determined according to the ratio of the resistance values of these resistors to form a positive signal. Is output from the output terminal Vout1. The operational amplifier OP2 is connected to the resistors R2, R22, R23, and R24, and calculates the difference between the video signal VD and one of the potentials Vc21 and Vc22 according to the ratio of the resistance values of these resistors. ,
A negative signal is formed, and this negative signal is output to the output terminal V
Output from out2.

Each of the switches SW11 and SW21 outputs a control signal C
The signal is alternately switched in response to 1 to alternately output the positive signal from the operational amplifier OP1 and the negative signal from the operational amplifier OP2 to the output terminal Vout.

R11: R12, R13: R24, R21 = R
22, R23 = R24, the output voltage of the output terminal Vout1 =
Input voltage of input terminal Vin-potential Vc11 (or potential Vc1
2) A relational expression of output voltage of output terminal Vout2 = −input voltage of input terminal Vin + potential Vc21 (or potential Vc22) is obtained.

Next, the drive voltage VCOM of the common electrode 107 is divided into the case of DC drive and the case of AC drive,
1, Vc12 and potentials Vc21, Vc22 will be described. Here, the offset voltages ΔVoff1 and ΔVoff are set between the central potential of the video signal VD and the drive voltage VCOM of the common electrode 107.
You must consider multiplying one of the two.

First, when the drive voltage VCOM of the common electrode 107 is DC drive, the control signal C2 is applied during one vertical period.
When the potentials Vc11 and Vc22 are selected according to the following equation, the potential Vc11 = offset voltage− △ Voff for the signal of positive polarity
Assuming that 1 is set and the potential Vc22 = offset voltage2Voff2 is set for the signal of the negative polarity, the polarity of the positive and negative polarities is inverted for each row in the following one vertical period in the next vertical period. In accordance with the control signal C2, the potentials Vc12 and Vc21 are selected, and the potential Vc12 = offset voltage− △ Voff2 is set for the positive polarity signal, and the potential Vc21 = offset voltage △ Voff for the negative polarity signal.
1 is set.

When determined in this manner, in one vertical period, the output voltage of the output terminal Vout1 = the input voltage of the input terminal Vin + the offset voltage △ Voff1, and the output voltage of the output terminal Vout2 = −the input voltage of the input terminal Vin + the offset. Voltage △ V
off2, and in the next one vertical period, the output voltage of the output terminal Vout1 = the input voltage of the input terminal Vin + the offset voltage △ Voff2, and the output voltage of the output terminal Vout2 = −the input voltage of the input terminal Vin + offset voltage △ Voff1. Becomes

Thus, it is understood that the potentials Vc11 and Vc12 and the potentials Vc21 and Vc22 can determine the center potential (the center potential of the positive and negative signals) of the video signal VD.

Next, when the drive voltage VCOM of the common electrode 107 is AC drive, the control signal C2 is applied during one vertical period.
When the potentials Vc11 and Vc22 are selected according to the following equation, Vc11 = offset voltage− △ Voff1 is set for a positive polarity signal, and Vc22 = offset voltage △ Voff2 + drive voltage VCOM is set for a negative polarity signal. (However, the driving voltage VCOM for the signal of the negative polarity), in the following one vertical period, the positive and negative polarities are inverted for each row from the previous vertical period, and accordingly, each potential Vc12 according to the control signal C2. , Vc21 are selected, the potential Vc12 = offset voltage− △ Voff2 is set for the signal of the positive polarity, and the potential Vc21 = offset voltage △ Voff for the signal of the negative polarity.
1 + drive voltage VCOM is set (however, drive voltage VCOM for a signal of negative polarity).

With this determination, in one vertical period,
Output voltage of output terminal Vout1 = input voltage of input terminal Vin +
Offset voltage △ Voff1, output voltage of output terminal Vout2 =
−input voltage of input terminal Vin + offset voltage △ Voff2 +
The driving voltage becomes VCOM, and in the following one vertical period, the output voltage of the output terminal Vout1 = the input voltage of the input terminal Vin + the offset voltage △ Voff2, and the output voltage of the output terminal Vout2 = −the input voltage of the input terminal Vin + the offset voltage. △ V
off1 + drive voltage VCOM.

Thus, it can be seen that the potentials Vc11 and Vc12 and the potentials Vc21 and Vc22 can determine the central potential of the video signal VD (the central potential combining the positive and negative signals).

The positive signal and the negative signal thus formed are supplied to the video signal V through the switches SW11 and SW21 which are alternately switched according to the control signal C1.
It is switched and output as D.

The present invention is not limited to the above embodiment, but can be variously modified. For example,
Each potential Vc11, Vc12 and each potential Vc21, Vc22 may be adjustable. In this case, between the center potential of the video signal VD and the drive voltage VCOM of the common electrode 107 (when the drive voltage VCOM is DC driven), or between the center potential of the video signal VD and the center potential of the drive voltage VCOM (the drive voltage VCOM When AC drive is performed) Each offset voltage △ Voff applied beforehand
1, ΔVoff2 can be adjusted.

The common electrode driving circuit 11 shown in FIG.
3, the center potential of the AC drive voltage VCOM or the DC drive voltage VCOM is lowered by a preset potential △ Voff ′, and the video signal VD is output by the polarity switching circuit 1 of the embodiment shown in FIG. Is increased by the remaining potential (offset voltage △ Voff1−potential △ Voff ′ or offset voltage △ Voff2−potential △ Voff ′), the center potential of the video signal VD and the common electrode 1
07 between the drive voltage VCOM (when the drive voltage VCOM is DC driven) or the center potential of the video signal VD and the drive voltage VC.
Each offset voltage ΔVoff1 and ΔVoff2 can be multiplied in advance between the center potentials of OM (when the driving voltage VCOM is driven by AC).

It is clear that the present invention is included in the above embodiment even if only the signal of the positive polarity or the signal of the negative polarity is shown in the above embodiment.

Further, the present invention has been described as being applicable to a TFT-type liquid crystal display device having a delta arrangement in which a color filter of only one color (for example, R) corresponds to the source line 104. It is not limited.
For example, in a liquid crystal display device in which a pixel electrode and a TFT element are alternately formed on the left and right sides of a source line for each gate line, a similar problem occurs. However, it is apparent that the present invention can solve this problem. is there.

Further, the above embodiment is not limited to the one described here. In short, between the central potential of the video signal VD and the drive voltage VCOM of the common electrode 107 (the drive voltage VCOM
If the potential difference applied between the center potential of the video signal VD and the center potential of the drive voltage VCOM (when the drive voltage VCOM is AC-driven) can be switched, the present invention is within the scope of the present invention. It is included.

[0105]

As described above, according to the present invention, the offset voltage between the central potential of each signal voltage and the drive voltage can be switched, and the pixel electrode caused by the stray capacitance Cgd of the switching element can be switched. According to the potential fluctuation ΔV,
By switching the offset voltage, the potential fluctuation ΔV of the pixel electrode can always be offset.

For this reason, even if the wiring pattern of the switching element is displaced, the liquid crystal does not deteriorate or flicker does not occur.
High display quality can be maintained.

[Brief description of the drawings]

FIG. 1 is a timing chart showing signals in a liquid crystal display device to which the present invention is applied, in which only a video signal VD is AC-driven and a common electrode driving voltage VCOM is DC-driven.

FIG. 2 is a timing chart showing a part of each signal of FIG. 1 over two vertical scanning periods.

FIG. 3 is a timing chart showing signals in a liquid crystal display device to which the present invention is applied, in which both a video signal VD and a common electrode drive voltage VCOM are AC driven.

FIG. 4 is a timing chart showing a part of each signal of FIG. 3 over two vertical scanning periods.

FIG. 5 is a block diagram showing a polarity switching circuit in one embodiment of the driving circuit of the present invention.

FIG. 6 is a diagram illustrating a specific example of the polarity switching circuit of FIG. 5;

7A is a diagram illustrating a stripe arrangement of each color pixel in the liquid crystal display panel, FIG. 7B is a diagram illustrating a mosaic arrangement of each color pixel in the liquid crystal display panel, and FIG. It is a figure showing the delta arrangement of a pixel.

FIG. 8 is a block diagram illustrating an overall configuration of a liquid crystal display panel in a delta arrangement.

FIG. 9 is a block diagram showing the overall configuration of another liquid crystal display panel having a delta arrangement.

FIG. 10 is a circuit diagram showing an equivalent circuit of a pixel.

FIG. 11 is a block diagram illustrating a data driver in the liquid crystal display device.

FIG. 12 is a block diagram illustrating a sample and hold circuit in a liquid crystal display device.

FIG. 13 is a block diagram showing a common electrode drive circuit in the liquid crystal display device.

FIG. 14 is a block diagram showing a conventional polarity switching circuit in a liquid crystal display device.

15A is a graph showing an input / output relationship of a polarity switching circuit in a case where only the video signal VD is AC-driven and a common electrode driving voltage VCOM is DC-driven, and FIG. 15B is a graph showing the video signal VD.
6 is a graph showing an input / output relationship of a polarity switching circuit when both the driving voltage VCOM of the common electrode and the common electrode are AC-driven.

FIG. 16 is a timing chart showing signals in a conventional liquid crystal display device in which only a video signal VD is AC-driven and a common electrode drive voltage VCOM is DC-driven.

FIG. 17 is a timing chart showing a part of each signal of FIG. 16 over two vertical scanning periods.

FIG. 18 is a timing chart showing signals in a conventional liquid crystal display device in which a video signal VD and a common electrode drive voltage VCOM are both AC-driven.

FIG. 19 is a timing chart showing a part of each signal of FIG. 18 over two vertical scanning periods.

20 is a plan view showing a layout near a pixel in the liquid crystal display device of FIG.

FIGS. 21 (a) to (c) are plan views of an inverted staggered TFT element, and FIGS. 21 (d) to (f) are C- views of (a) to (c).
It is sectional drawing which follows C '.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Polarity switching circuit 2 Positive signal creation circuit 3 Negative signal creation circuit 4 Output circuit 5, 6 Switching circuit

Continued on the front page (72) Inventor Makoto Miyago 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Tsuyoshi Matsukawa 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Yasuhiro Matsushima 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation

Claims (10)

[Claims] A plurality of scanning lines and a plurality of signal lines are arranged so as to intersect with each other, and a pixel electrode is provided for each region defined by each scanning line and each signal line. Switching elements are provided, and for each signal line, each pixel electrode on both sides of the signal line is selectively connected to the signal line via each switching element, and the common electrode is opposed to each pixel electrode. A driving method for a liquid crystal display device, wherein each signal voltage is applied to each of the pixel electrodes from each of the signal lines through each of the switching elements, and a driving voltage is applied to the common electrode. A driving method of a liquid crystal display device, wherein an offset voltage is set between a center potential of each of the signal voltages and the driving voltage, and the offset voltage can be switched. 2. The method according to claim 1, wherein the drive voltage is an AC voltage, and an offset voltage is set between a center potential of each signal voltage and the center potential of the drive voltage. 3. The driving method of a liquid crystal display device according to claim 1, wherein the offset voltage is switched by switching a center potential of each signal voltage. 4. A plurality of scanning lines and a plurality of signal lines are arranged so as to intersect with each other, and a pixel electrode is provided for each region defined by each scanning line and each signal line. The switching elements are provided, and for each signal line, each pixel electrode on both sides of the signal line is selectively connected to the signal line via each switching element, and the common electrode is opposed to each pixel electrode. A driving circuit of a liquid crystal display device, which applies each signal voltage from each signal line to each pixel electrode via each switching element, and applies a driving voltage to the common electrode. A first switching means for switching a central potential of each signal voltage; and an offset between the central potential of each signal voltage and the driving voltage by switching the central potential of each signal voltage by the first switching means. A drive circuit for a liquid crystal display device that can switch the voltage. 5. The method according to claim 4, wherein the drive voltage is an AC voltage, and an offset voltage is set between a central potential of each signal voltage and the central potential of the drive voltage. 6. The driving circuit according to claim 4, wherein the first switching means switches the center potential of the signal voltage every time each scanning line is scanned. 7. A driving circuit for a liquid crystal display device according to claim 4, wherein said first switching means has a plurality of preset potentials as a central potential of each signal voltage, and selectively switches among these preset potentials. . 8. The first switching means has at least two preset potentials as a central potential of each signal voltage, and selectively switches each preset potential each time each scanning line is scanned. 5. The driving circuit for a liquid crystal display device according to 4. 9. The first switching means has at least two preset potentials as a central potential of each signal voltage, and selectively switches each preset potential every one vertical scanning period. 3. A driving circuit for a liquid crystal display device according to claim 1. 10. The driving circuit according to claim 4, wherein a center potential of each signal voltage can be adjusted.