JPH11145807A - Signal control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress high frequency noises due to through-current and the leak of a higher harmonic caused by a higher harmonic component in a digital circuit which uses a clock signal. SOLUTION: In a signal inverter circuit 11, an inverted clock signal of rising/ falling time (ta1) of a potential is outputted to an output line D. In a signal operating circuit 12, the inverted clock signal and the control clock signal of rising/falling time (ta2) (ta2#ta1) of a potential are arithmetically operated, and the output clock signal of rising/falling time (ta3) (ta2<ta3<ta1) of a potential is generated. Since the rising/falling of the potential becomes dull in this output clock signal, a through-current is diffused. In addition, since the waveform of the output clock signal becomes approximately to that of a sine wave, the higher harmonics components of a clock itself are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit using a clock signal, and more particularly to a P-MOS, an NM which constitutes a microprocessor, a semiconductor memory and the like.
The present invention relates to a high-speed and large-scale digital integrated circuit such as an OS.

[0002]

2. Description of the Related Art In a general digital circuit, a clock is used as a signal for timing operation of the circuit. However, in a pulse signal used as a clock, if the rise / fall of the potential (when the transistor is turned on / off) is sharp, the circuit instantaneously generates a large current (through current).
Flows. Such a change in current that occurs in a short time causes unnecessary radiation, and in particular, a high-speed, large-scale digital (I
C) The circuit has a problem that high-frequency noise causes malfunction of peripheral devices.

Further, a square wave used as a clock includes a sine wave as a fundamental wave and an odd harmonic component equal to or higher than the third harmonic. Harmonic leakage becomes noise,
As in the case of the high frequency noise, there is a problem that a malfunction of the peripheral device occurs.

For this reason, conventionally, measures have been taken such as dividing the output-stage transistor into small pieces and intentionally giving a time difference to the operation of each transistor.

[0005]

Here, an example of the above-described countermeasures for shoot-through current will be described. In the inverter circuit shown in FIG. 5, both the P-channel transistor 21 and the N-channel transistor 22 have large (large) capacity.
Assuming that a transistor is used, as shown in FIG. 6, the output when the transistor is turned on has a sharp signal rise, so that an excessive through current flows. On the other hand, when a transistor having a large capacity is divided into a plurality of transistors having a small capacity (small) and connected by a delay element so as to provide a time difference between ON / OFF of each transistor, as shown in FIG. Since the rise of the signal becomes gentle and the peak of the through current is flattened, high frequency noise due to unnecessary radiation is suppressed. In addition, since harmonic components of a square clock are reduced, harmonic leakage can be suppressed.

However, when a circuit is composed of a plurality of transistors having a small capacity as described above, there is a problem that the circuit scale becomes large because a delay element and an OR gate are required.

An object of the present invention is to provide a signal control circuit that can suppress high-frequency noise and harmonic leakage without significantly increasing the circuit scale.

[0008]

In order to achieve the above object, a first aspect of the present invention is a signal inverting circuit which outputs an inverted clock signal having an inverted potential of an input clock signal and a rise / fall time ta1 of the potential. Circuit, the inverted clock signal, and potential rise / fall time ta
2 (ta2 << ta1) and the potential rise / fall time ta3 (ta2
And a signal operation circuit for generating an output clock signal of <ta3 <ta1).

The rise / fall time t of the above potential
a1, ta2, and ta3 refer to the time required for the rise / fall of each signal potential as shown in FIG. Although FIG. 8 illustrates only the rise of the potential, the same applies to the fall.

[0010] The invention of claim 2 is based on claim 1,
The inverted clock signal is formed by two transistors having a small ability to turn on and off according to the potential of the input clock signal, and the control clock signal is controlled by the potential of the clock signal having a short rise / fall time of the potential. It is characterized by being formed by two transistors having large on / off capability.

Here, a transistor having a small capacity is
A transistor having a long rise / fall time of the potential of a current flowing in the transistor is referred to, and a transistor having a high capability is a transistor having a short rise / fall time of the potential.

According to a third aspect of the present invention, in the second aspect, the clock signal having a short rise / fall time of the potential is a clock signal formed from a signal obtained by dividing the input clock signal by two. And

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a signal control circuit according to the present invention is applied to an inverter circuit will be described below.

FIG. 1 is a configuration diagram of an inverter circuit according to this embodiment. The inverter circuit 10 includes a signal inversion circuit 11 and a signal operation circuit 1 connected by an output line D.
2 is comprised.

The signal inverting circuit 11 is an inverter circuit composed of two transistors 13 and 14 having small capacities. The signal inverting circuit 11 is turned on and off alternately according to the potential level of the input A which is an input clock signal. In addition, the potential of VDD (main power supply) is output to the output line D as an inverted potential (inverted clock signal) of the input clock signal. The rising / falling time of the potential of the inverted clock signal is defined as ta1.

The signal operation circuit 12 is connected to two transistors 15 and 16 having a large capacity, and is connected to an output line D between the two transistors. The transistors 15 and 16 receive the input B and the input C as a clock signal having a short rise / fall time of the potential.
Is supplied. When the transistors 15 and 16 are turned on and off according to the potential levels of the inputs B and C,
The current flowing from VDD is a clock signal having a short potential rise / fall time (hereinafter, a control clock signal).
Is output to the output line D. The rise / fall time of the potential of the control clock signal is defined as ta2 (ta
2 << ta1). Then, the control clock signal and the inverted clock signal are calculated on the output line D,
An output clock signal as described later is output. The rise / fall time of the potential of the output clock signal is defined as ta3 (ta2 <ta3 <ta1).

The inputs B and C are clock signals formed from signals obtained by dividing the input A, which is an input clock signal, by two. This clock signal can be formed by a known frequency dividing circuit (not shown).

The transistors 13 and 15 are:
For example, P-channel MOS transistors can be used, and the transistors 14 and 16 can be N-channel MOS transistors.

Next, the basic operation of the above-described inverter circuit will be described with reference to FIG. 2 which is an equivalent circuit diagram of FIG.

In the signal inverting circuit 11, the transistor 13 is turned on when the level of the input A is L, and the transistor 14 is turned on when the level of the input A is H. Therefore, as the level of the input A changes to H and L alternately, the transistors 13 and 14 alternately turn on and off. When the transistor 13 is turned on, a signal corresponding to the potential of VDD is output to the output line D. However, since the transistor 13 has a small capacity, a signal (ta1) having a long rise time of the potential is output to the output line D. You.
When the transistor 14 is turned on, the potential output to the output line D is discharged to VSS. However, since the transistor 14 has a small capacity, a signal having a long potential falling time (ta1) is discharged. Therefore, the signal inverting circuit 11 outputs an inverted clock signal which is an inverted potential of the input A, which is an input clock signal, and which has a rise / fall time ta1 of the potential.

On the other hand, in the signal operation circuit 12, the transistor 15 is turned on when the level of the input C is L, and the transistor 16 is turned on when the level of the input B is H. Input B and input C are H and L with phases shifted by 1/4 cycle, respectively.
Appears, the transistors 15 and 16 are turned on and off every quarter cycle of the input A that is the input clock signal. When the transistor 15 is turned on, V
A control clock signal corresponding to the potential of DD is output to the output line D. However, since the transistor 15 has a large capacity,
The rise of the control clock signal when the transistor 15 is turned on becomes steep. Also, the transistor 16
Is turned on, the potential of the output line D is discharged to VSS. However, since the transistor 16 has a large capacity, the fall of the control clock signal when the transistor 16 is turned on becomes steep. Thus, transistor 1
Since both rise and fall when the switches 5 and 16 are turned on become steep, the control clock signal corresponding to the VDD potential has a short potential rise / fall time (ta2, (ta2 <<<<). ta1)) signal. Then, the rise / fall time of the potential (ta)
When the control clock signal of 2) and the inverted clock signal of the rise / fall time (ta1) of the potential flowing through the output line D are calculated, the output clock of the rise / fall time ta3 of the potential (ta2 <ta3 <ta1) is obtained. A signal will be generated. Rise of this potential /
In the output clock signal of the fall time ta3,
The waveform has such a waveform that the rise / fall of the waveform changes gradually up to the middle and becomes steep at the middle.

Next, the operation of the inverter circuit 10 shown in FIG. 1 will be described with reference to a timing chart shown in FIG. Here, a period of T0 to T4, which is an arbitrary cycle, will be described.

First, since the level of the input A is L during the period from T0 to T1, the transistor 13 is turned on (at this time, the transistor 14 is turned off), and a signal corresponding to the VDD potential passes through the transistor 13 to the output line D. Flows. Here, since the capacity of the transistor 13 is small, the potential of the output line D gradually increases. Here, since the transistors 15 and 16 are also off, the potential of the output line D directly becomes the output clock signal.

Next, at T1, since the level of the input C becomes L, the transistor 15 is turned on (at this time, the transistor 16 is turned off), and a signal corresponding to the potential of VDD flows from the transistor 15 to the output line D. Here, since the capacity of the transistor 15 is large, the potential of the output line D sharply increases. Thereafter, from T1 to T2, the voltage of the VDD level is held.

Next, at T2, since the level of the input A becomes H, the transistor 14 is turned on (at this time, the transistor 13 is turned off), and the potential of VDD on the output line D is discharged to VSS through the transistor 14. Is done. Here, since the capacity of the transistor 14 is small, the potential of the output line D gradually decreases from T2 to T3. Here, since the transistors 15 and 16 are also off, the potential of the output line D directly becomes the output clock signal.

Next, at T3, since the level of the input B becomes H, the transistor 16 is turned on (at this time, the transistor 15 is turned off), and the potential of VDD on the output line D is discharged to VSS through the transistor 16. Is done. Here, since the capacity of the transistor 16 is large, the potential of the output line D sharply decreases. Thereafter, the voltage level of VSS is held from T3 to T4.

As is apparent from the waveform of the output clock signal shown in FIG. 3, when an inverted clock signal having a slow rising / falling potential and a control clock signal having a fast rising / falling potential are calculated, the output is obtained. The clock signal becomes a signal approximating a sine wave with rising / falling of the potential.

As described above, when the change of the rise / fall of the output clock signal becomes gentle, it becomes difficult for the through current to flow, and the effect of high frequency noise due to unnecessary radiation can be eliminated. Incidentally, the through current generated by the inverter circuit of this embodiment is the same as that of FIG.
As shown in (1), since the signal has a short pulse width and a low wave height, unnecessary radiation can be significantly reduced.

Further, since the waveform of the output clock signal is a waveform approximating the sine wave which is the fundamental wave, harmonic components of the clock itself are reduced, and harmonic leakage can be eliminated.

In the output clock signal shown in FIG.
Although the potential of DD is held, the output clock signal can be formed at a potential of a predetermined threshold level equal to or lower than VDD.

Further, in the inverter circuit according to this embodiment, a divide-by-2 circuit for dividing the input A by 2 to form the inputs B and C is required. As compared with a configuration in which a large transistor is divided into a plurality of transistors and connected by delay elements, the increase in circuit scale can be made much smaller, so that high-frequency noise and harmonics can be reduced without significantly increasing the circuit scale. Wave leakage can be suppressed.

[0032]

As described above, according to the signal control circuit of the present invention, since the rise / fall of the potential of the output clock signal is reduced, the through current is dispersed, and high frequency noise due to unnecessary radiation is suppressed. be able to. Further, since the waveform of the output clock signal can be a waveform approximating a sine wave, harmonic components of the clock itself are reduced, and harmonic leakage can be suppressed. In addition, the increase in the circuit scale can be suppressed much less than when a circuit is formed by a plurality of transistors having a small capacity as in the related art.

Therefore, in the signal control circuit according to the present invention, it is possible to suppress high-frequency noise and harmonic leakage without greatly increasing the circuit scale, and to prevent a malfunction that causes a peripheral device to malfunction. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an inverter circuit according to an embodiment.

FIG. 2 is an equivalent circuit diagram of FIG.

FIG. 3 is a timing chart showing the operation of the inverter circuit according to the embodiment.

FIG. 4 is a current waveform diagram showing a through current in the embodiment.

FIG. 5 is a configuration diagram of a conventional inverter circuit.

FIG. 6 is a timing chart showing the relationship between input / output and through current in a conventional inverter circuit.

FIG. 7 is a timing chart showing the relationship between input / output and through current in a conventional circuit in which a through current measure is taken.

FIG. 8 shows rise / fall times ta1, t of a potential.
Explanatory drawing of a2 and ta3.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Inverter circuit 11 Signal inversion circuit 12 Signal operation circuit 13, 14 Transistor with small capacity 15, 16 Transistor with large capacity

Claims (3)

[Claims] 1. An inverted potential of an input clock signal,
A signal inverting circuit for outputting an inverted clock signal of a potential rising / falling time ta1, calculating the inverted clock signal and a control clock signal of a potential rising / falling time ta2 (ta2 << ta1), Rise / fall time ta of potential
3 (ta2 <ta3 <ta1), and a signal operation circuit for generating an output clock signal. 2. The inverted clock signal is formed by two transistors having a small ability to turn on and off according to the potential of an input clock signal, and the control clock signal is a clock signal having a short rise / fall time of the potential. 2. The signal control circuit according to claim 1, wherein the signal control circuit is formed by two transistors having a large ability to turn on and off according to the potential of the transistor. 3. The signal control circuit according to claim 2, wherein the clock signal having a short potential rising / falling time is a clock signal formed by dividing the input clock signal by two. .