JPH11126819A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve element separating ability of an element isolating region by reducing the parasitic capacitance in the region by partially forming a void (vacuum) section having a low dielectric constant in the region. SOLUTION: After a thermally oxidized film has been formed on a semiconductor substrate 11, a trench 15 is formed into the substrate 11 through the oxidized film, and another thermally oxidized film 16 is formed on the internal surface of the trench 15. Then, the trench 15 is filled up with a silicon nitride film 17, after a transistor has been formed in an element activating region, a BPSG film 25 is deposited on the whole surface of the substrate 11 and planarized. After a polysilicon film 26 and a silicon nitride film 27 have been successively deposited on the film 25, an opening 29 is formed by selectively removing the silicon nitride film 27 on the silicon nitride film 17, and voids 15 and 29 are formed by removing the silicon nitride films 17 and 27. Thereafter, a void (vacuum) region is formed by closing the top of the voids 15 and 29 by forming a thermally oxidizing film through thermal oxidation of the polysilicon film 26.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an element isolation structure with improved electrical isolation between elements and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a conventional element isolation method in the manufacture of a semiconductor device, there are a method of forming a field oxide film in an element isolation region, a field shield method, and a method of element isolation using an element isolation electrode.

[0003] Further, as an element isolation method, there is a method of making an element isolation region a gap. For example, JP-A-60-15
JP-A No. 0644 and JP-A-8-37230 disclose a manufacturing method and a manufacturing process for forming an element isolation structure by an element isolation technique using a cavity or a closed space.

According to the invention described in JP-A-60-150644, a pattern of a CVD oxide film formed on a semiconductor substrate is etched to a depth of 5
μm grooves are formed at 5 μm intervals.

Next, a thermal oxide film is formed inside the groove,
Next, only the thermal oxide film at the bottom of the groove is completely etched and removed by anisotropic etching. An example is shown in which silicon at the bottom of the groove is etched by about 1 μm by anisotropic etching of silicon to form a cavity wider than the groove.

According to the invention described in Japanese Patent Application Laid-Open No. Hei 8-37230, as Example 1, a groove for element isolation is formed on a semiconductor substrate, and a silanol organic solution is spin-coated in an inert gas atmosphere. Then, an insulating film such as a silicon oxide film is formed on the groove by applying a heat treatment. At this time, by optimizing the viscosity of the silanol organic solution and the number of revolutions at the time of application in accordance with the opening diameter of the groove, a silicon oxide film or the like is formed only on the upper part of the groove without allowing the solution to penetrate into the groove. It is stated that an insulating film can be formed to seal the space in the groove.

According to the second embodiment also described in Japanese Patent Application Laid-Open No. Hei 8-37230, a wall-shaped member is formed which is separated from the side wall of the groove for element isolation by a predetermined amount and is connected to the bottom surface of the groove. There is described an example in which a gap between the wall-shaped body and the side wall of the groove is sealed with the above-mentioned silanol organic solution to form a space.

[0008]

However, in order to reduce the dielectric constant and improve the element isolation capability, the method disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 60-150644 is used. If a void is formed in a portion within, for example, at least 1 μm from the substrate surface, a high-concentration diffusion layer is also formed on the substrate surface, so that a well cannot be formed. Therefore, there is a problem that it is very difficult to form device elements on the surface of the silicon substrate.

Usually, when an element isolation region is formed by a gap, there is a problem how to form an insulating film above the gap. In Example 1 described in JP-A-8-37230, when the viscosity of the silanol organic solution and the number of revolutions at the time of application are optimized according to the trench opening diameter as described above, the solution is placed inside the void. Do not let it penetrate,
It is stated that an insulating film can be formed on the gap.

However, since the element isolation region (trench opening diameter) generally has various dimensions in each region of the device, the void portion is actually sealed over a region of sub-half micron to several tens μm (that is, the gap is closed). It is difficult to infiltrate the silanol organic solution into all the trenches having various pattern widths).

On the other hand, in the second embodiment described in JP-A-8-37230, the width of the side wall (SW) for forming the air gap is not determined by the width of the trench.
Since the gap width between the wall and the side wall is defined, the above problem can be solved by keeping the gap width constant even if the groove width is different. However, in this case, most of the inside of the trench is formed not by a void but by a wall-shaped body, so that there is a problem that the effect of lowering the dielectric constant obtained by introducing the void is reduced.

If the width of the side wall is increased to increase the volume of the void portion, the wall-like body has an inversely tapered shape, which is an unstable process for miniaturization. There is a concern about falling and peeling.

Further, in the method described in Japanese Patent Application Laid-Open No. Hei 8-37230, after the trench is formed, the gap formed in the trench is formed so as to be covered with an insulating film. Since the design rule of the isolation region is determined not by the trench isolation width but by the processing size of the insulating film to be overlaid, there is a disadvantage that the miniaturization is disadvantageous by a margin more than a margin for matching the trench pattern and the insulating film pattern. There was also.

An object of the present invention is to make it possible to stably form a void region, which is an element isolation structure, to easily form an insulating film above a void, to be suitable for miniaturization, and to have devices of various sizes. It is an object of the present invention to provide a semiconductor device capable of forming an isolation structure (a gap therein) and a method for manufacturing the same.

[0015]

According to the present invention, there is provided a semiconductor device comprising:
A first element isolation structure and a second element isolation structure formed in a semiconductor substrate, wherein the semiconductor substrate includes a first element active region defined by the first element isolation structure, and a second element isolation region. A second element active region defined by the element isolation structure of (1), wherein the first element isolation structure comprises a first groove formed in the semiconductor substrate, and is provided in the first groove. The second device isolation structure includes a first cavity region formed, and the second device isolation structure includes one of a device isolation structure including an insulating film and a field shield device isolation structure including electrodes. .

In one embodiment of the semiconductor device according to the present invention, a first insulating film formed on the semiconductor substrate including the first groove and the first insulating film on the first groove are provided. A second cavity region formed in the first and second cavities.
Are connected to form a cavity region.

In one embodiment of the semiconductor device according to the present invention, the semiconductor device further comprises a second groove formed in the first insulating film on the first groove, wherein the first insulating film has The cavity region is sealed by the conductive film formed in the second groove.

In one embodiment of the semiconductor device according to the present invention, one of the first and second element active regions is a memory cell forming region, and one of the first and second element active regions is The other area is a peripheral circuit formation area.

In one embodiment of the semiconductor device of the present invention, an insulating layer is formed in at least a part of the semiconductor substrate.

The semiconductor device according to the present invention includes a first groove formed in a semiconductor substrate, a first insulating film formed on the semiconductor substrate including the first groove, and at least a portion of the first insulating film. A second groove formed in the first insulating film on the first groove, the first insulating film; and a second groove formed in the first insulating film on the first groove. The hollow region is sealed by the conductive film formed in the groove.

According to the semiconductor device of the present invention, a groove formed in a semiconductor substrate, a first insulating film formed on the semiconductor substrate including the groove, and a first insulating film formed on the groove are formed. It has a first gap region and a second gap region formed in at least a part of the groove, and the first and second gap regions are connected to form a cavity region.

In one embodiment of the semiconductor device of the present invention, a second insulating film is formed on the first insulating film, and the second insulating film seals the cavity.

In one embodiment of the semiconductor device of the present invention, the thickness of the second insulating film is equal to or larger than the width of the first void region.

In one embodiment of the semiconductor device according to the present invention, the first insulating film is provided with an opening reaching the second void region.

In one embodiment of the semiconductor device of the present invention, a second insulating film is formed on the first insulating film, and the thickness of the first insulating film is not less than the width of the opening. is there.

In one embodiment of the semiconductor device according to the present invention, a third insulating film is filled in the trench in a part of the region.

In one embodiment of the semiconductor device according to the present invention, a fourth insulating film is provided in at least a part of the semiconductor substrate.

In one embodiment of the semiconductor device according to the present invention, a part of the bottom of the groove is formed on a part of the fourth insulating film.

In one embodiment of the semiconductor device of the present invention, the semiconductor substrate is one of SOI and SIMOX.

In one embodiment of the semiconductor device of the present invention, the fourth insulating film is provided in a substantial area other than below the second void area.

In one embodiment of the semiconductor device according to the present invention, a conductive film is formed on the first insulating film, and the hollow region is sealed by the conductive film.

In one embodiment of the semiconductor device according to the present invention, the semiconductor substrate includes an element active region defined by at least a part of the groove.

A semiconductor device according to the present invention includes a groove formed in a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate including the groove, and a first film formed in at least a part of the groove. A hole, a first hole formed in the interlayer insulating film over the groove, and the first hole and the cavity region are connected to each other.

In one embodiment of the semiconductor device of the present invention, the semiconductor device has a conductive film formed in the first hole, and the hollow region is sealed by the conductive film.

In one embodiment of the semiconductor device of the present invention, the semiconductor device has an impurity diffusion layer formed on a surface layer of the semiconductor substrate and a second hole formed in the interlayer insulating film on the impurity diffusion layer. The bottom of the second hole is a surface layer of the impurity diffusion layer, has a conductive film formed in the second hole, and is electrically connected to the impurity diffusion layer. ing.

In one embodiment of the semiconductor device according to the present invention, the semiconductor device comprises an impurity diffusion layer formed on a surface layer of the semiconductor substrate, and a first conductive film formed in the first hole. The first conductive film closes the cavity region, has a second hole formed in the interlayer insulating film on the impurity diffusion layer, and has a bottom portion of the second hole formed by the impurity diffusion layer. A second conductive film formed in the second hole is formed as a surface layer of the layer, and the impurity diffusion layer and the second conductive film are electrically connected.

In one embodiment of the semiconductor device of the present invention, a memory cell region and a peripheral circuit region are provided on the semiconductor substrate, and the gap region is formed at least at a boundary between the memory cell region and the peripheral circuit region. Is formed.

In one embodiment of the semiconductor device according to the present invention, the peripheral region is separated by the gap region.

In one embodiment of the semiconductor device of the present invention, the groove in a part of the semiconductor substrate is filled with an insulating film, and the insulating film functions as the element isolation structure together with the gap region. I do.

In one embodiment of the semiconductor device of the present invention, the semiconductor substrate is a semiconductor substrate in which a semiconductor layer is formed on a semiconductor base via an insulating layer, and the groove reaches the insulating layer. And the gap region and the insulating layer are connected to each other.

According to the method of manufacturing a semiconductor device of the present invention, a first step of forming a groove in an element isolation region of a semiconductor substrate, an oxide film is selectively formed in the groove, and a nitride film is formed in the groove. A third step of forming an interlayer insulating film so as to cover the entire surface of the semiconductor substrate including the trench, and a fourth step of depositing a silicon film on the interlayer insulating film. A fifth step of forming an opening reaching the surface layer of the nitride film in the silicon film and the interlayer insulating film, a sixth step of removing the nitride film from the opening by wet etching, A step of sealing the opening by thermally oxidizing the silicon film, and a seventh step of sealing a cavity formed in the trench and in an opening of the interlayer insulating film.

In the method of manufacturing a semiconductor device according to the present invention, a first step of forming a groove in an element isolation region of a semiconductor substrate, and a step of selectively forming a thermal oxide film in the groove, and then forming a first nitride film In the trench, a third step of sequentially depositing an interlayer insulating film, a silicon film, and a second nitride film on the entire surface of the semiconductor substrate; and forming a first nitride film on at least the second nitride film. A fourth step of forming an opening, and a third step on the second nitride film.
A fifth step of forming a third nitride film, and a sixth step of forming a sidewall nitride film made of a third nitride film on a side wall of the second nitride film by etching back the third nitride film. Using the second nitride film and the sidewall nitride film as a mask, sequentially etching the silicon film and the interlayer insulating film until a surface layer of the first nitride film is exposed, The second layer having the surface layer of the nitride film as the bottom surface
A seventh step of forming an opening of the first nitride film;
An eighth step of removing the second nitride film and the sidewall nitride film by wet etching.

According to the method of manufacturing a semiconductor device of the present invention, a first step of forming a groove in an element isolation region of a semiconductor substrate, a second step of burying a nitride film in the groove, and the step of forming a groove are defined by the groove. A third step of forming a semiconductor element in an element active region of the semiconductor substrate, and a fourth step of forming an interlayer insulating film so as to cover the entire surface of the semiconductor substrate including the trench and the semiconductor element. A fifth step of forming both a first opening reaching the surface layer of the nitride film and a second opening reaching the surface layer of the semiconductor substrate in the semiconductor element in the interlayer insulating film; A sixth step of removing the first opening from the first opening by a wet etching method to make the inside of the groove a gap area, and sealing the gap area by embedding a conductive film in the first opening; In the second opening And a seventh step of electrically connecting the conductive film and the semiconductor element is embedded the conductive film.

According to a method of manufacturing a semiconductor device of the present invention, a first step of forming a groove in an element isolation region of a semiconductor substrate, a second step of burying a nitride film in the groove, and the step of forming the groove are defined by the groove. A third step of forming a semiconductor element in an element active region of the semiconductor substrate, and a fourth step of forming an interlayer insulating film so as to cover the entire surface of the semiconductor substrate including the trench and the semiconductor element. A fifth step of forming a first opening reaching the surface layer of the nitride film in the interlayer insulating film;
A sixth step of removing the nitride film from the first opening by a wet etching method to make the inside of the groove a void area; and a second opening reaching the surface layer of the semiconductor substrate in the semiconductor element. Is formed on the interlayer insulating film.
And a step of filling the first opening with a conductive film to seal the gap region, and filling the second opening with the conductive film to electrically connect the semiconductor element and the conductive film. An eighth step.

[0045]

According to the present invention, a nitride film buried in a trench and whose upper layer is covered with an interlayer insulating film is removed from an opening formed in the interlayer insulating film. The void region can be formed in an appropriate manner.

In the present invention, the void region can be easily sealed by oxidizing the silicon film. For example, the nitride film is removed from the void region (element isolation structure) having various dimensions. The number of openings can be increased.

In the present invention, a conductive film which is a wiring layer electrically connected to a semiconductor element formed in an element active region is formed, and at the same time, a void region can be sealed using the conductive film. .

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described as a first embodiment by using an N-channel MOS.
An example in which the present invention is applied to a transistor will be specifically described with reference to the drawings.

As shown in FIG. 1A, a pad oxide film 12 having a thickness of 30 nm is formed on the surface of a p-type semiconductor substrate 11 by a thermal oxide film method. A polysilicon film 13 and a silicon nitride film 14 are deposited thereon by CVD at a thickness of 100 nm and 50 nm, respectively.

After that, the polysilicon film 13 and the silicon nitride film 14 are patterned by photolithography and etching so as to cover the element formation region. That is, the polysilicon film 13 and the silicon nitride film 14 formed in the element isolation region are removed.

Next, using the silicon nitride film 14 as a mask, the pad oxide film 12 in the element isolation region is removed by etching. After that, similarly using the silicon nitride film 14 as a mask, the semiconductor substrate 11 in the element isolation region is etched to form a trench 15 having a depth of 300 [nm] and a width of 300 [nm] in the semiconductor substrate 11.

Next, as shown in FIG. 1B, a thermal oxide film 16 is selectively formed to a thickness of 10 [nm] on the semiconductor substrate 11 in the trench 15 by a thermal oxidation method. Thereafter, the semiconductor substrate 1 including the trench 15 is formed by CVD.
1, a silicon nitride film 17 having a thickness of 150 to 200 [n].
m] is deposited.

Next, as shown in FIG. 1C, the silicon nitride film 17 is etched back by reactive ion etching (RIE) until the polysilicon film 13 is exposed (exposed). As a result, the silicon nitride film 17 can be buried only inside the trench 15. Further, the polysilicon film 13 is completely removed by etching back by the RIE method.

Next, as shown in FIG. 2A, a silicon oxide film is deposited on the semiconductor substrate 11 to a thickness of 150 [nm]. Thereafter, the silicon oxide film is etched back by the RIE method to form a sidewall oxide film 18 made of a silicon oxide film on the side wall of the silicon nitride film 17.
Is formed, and the silicon oxide film 12 formed in the element formation region is removed.

Next, as shown in FIG. 2B, a gate oxide film 19 is formed on the element formation region of the semiconductor substrate 11 by a thermal oxidation method. Thereafter, a gate electrode 20 made of polysilicon doped with phosphorus (P) and a cap oxide film 21 are sequentially deposited on the gate oxide film 19 by the CVD method. Thereafter, the cap oxide film 21 and the gate electrode 2 are formed by photolithography and etching.
0 and the gate oxide film 19 are sequentially patterned.

After that, after depositing a silicon oxide film 22 on the semiconductor substrate 11, the silicon oxide film 22 is etched back by the RIE method to form the gate electrode 2
A sidewall oxide film 22 made of a silicon oxide film is formed on the sidewall of the zero. Further, an n-type impurity, for example, arsenic is ion-implanted into the semiconductor substrate 11 in the element formation region using the cap oxide film 21 formed in the element formation region as a mask.

As a result, an arsenic ion-implanted layer can be formed in a self-alignment manner on the surface layer of the element formation region of the semiconductor substrate 11. Next, a heat treatment is performed on the semiconductor substrate 11 to activate the arsenic ion implanted layer, and the n ⁺ -type source region 23 and the drain region 24 formed of the arsenic ion implanted layer are formed on the surface layer of the semiconductor substrate 11 on both sides of the gate electrode. To form

Next, as shown in FIG.
A BPSG film 25 having a thickness of 450 [nm] is deposited on the entire surface of the semiconductor substrate 11 by a method. Thereafter, the semiconductor substrate 11 is subjected to a heat treatment (for example, temperature: 850 [° C.], time: 30 [mi].
n]), the surface layer of the BPSG film 25 is flattened. Thereafter, a 100 nm thick polysilicon film 26 and a 100 nm thick silicon nitride film 27 are sequentially deposited on the BPSG film 25 by CVD.

Next, as shown in FIG. 3A, the silicon nitride film 27 is patterned by a photolithography technique and an etching technique, so that the silicon nitride film 27 on the silicon nitride film 17 has a diameter of 300 [nm].
The opening (hole) is formed. Further, the semiconductor substrate 11
A silicon nitride film 28 is deposited to a thickness of 100 [nm] on the entire surface of the substrate.

Next, the silicon nitride film 2 is formed by the RIE method.
8 is etched back to form the silicon nitride film 27.
Is formed on the side wall of the silicon nitride film. Next, the polysilicon film 26 and the BPSG film 25 are sequentially etched using the silicon nitride film 27 and the sidewall nitride film 28 as a mask, so that an opening 29 (100 nm in diameter) reaching the surface layer of the silicon nitride film 17 is formed. ]) To the polysilicon film 26
And a BPSG film 25.

Next, as shown in FIG.
By etching, for example, H _ThreePO_FourD.
Using a silicon nitride film 17, 27, 2
8 is removed. As a result, a cavity (empty) is formed in the trench 15.
(Gap) regions are formed.

As described above, the silicon nitride film 17 buried in the trench 15 and whose upper layer is covered with the BPSG film 25
Is removed from the opening 29 by using the trench 15 and the BP.
A cavity region can be stably formed between the SG film 25 and the SG film 25. Further, since the design rule of the element isolation structure is the width of the formed hollow region itself, it is suitable for miniaturization of the element.

Thereafter, by thermally oxidizing the polysilicon film 26, the polysilicon film 26 in the upper region of the opening 29 becomes a thermal oxide film 30 and the opening 29 is sealed.
In this manner, by thermally oxidizing the polysilicon film 26 formed in advance, even if a large number of openings 29 are formed, the polysilicon film 26 can be easily sealed.

Although not shown, the semiconductor device according to the present embodiment is manufactured by continuing the wiring process in order to set the semiconductor substrate 11, the gate electrode 20, the source 23, and the drain 24 to appropriate potentials.

As for the relationship between the diameter D of the opening 29 and the thickness T of the polysilicon film 26, according to a simulation result using the process simulator SUPREM4, the thickness T of the polysilicon film 26 and the opening T The relationship with the maximum opening diameter D that can close the opening 29 is as shown in the table below.

[0066]

[Table 1]

From the above results, it can be seen that the thickness T of the polysilicon film 26 is sufficient if it is equal to or larger than the diameter D of the opening.

As described above, in the method of manufacturing a semiconductor device according to the first embodiment of the present invention, a thermal oxide film 12 is formed on a semiconductor substrate 11, and the thermal oxide film 12 and the semiconductor substrate 11 are opened. Thus, a trench 15 is formed. afterwards,
After forming the thermal oxide film 16 on the inner wall of the trench 15,
A silicon nitride film 17 is buried in the trench 15 to form a trench isolation layer.

Next, after a MOS transistor is formed in the element formation region of the semiconductor substrate 11, a BPSG film 25 is deposited on the entire surface of the semiconductor substrate 11. After that, the surface layer of the BPSG film 25 is flattened. Next, a polysilicon film 26 and a silicon nitride film 27 are sequentially deposited on the BPSG film 25.

Next, the silicon nitride film 27 located on the silicon nitride film 17 embedded in the trench 15 is selectively removed, and an opening 29 is formed on the silicon nitride film 17. Next, the buried silicon nitride film 17 and the silicon nitride film 27 are removed by a wet etching method to form a void in the trench 15 and the opening 29.

Next, the polysilicon film 26 is thermally oxidized to form a thermal oxide film 30, and the trench 15 and the opening 29 are sealed by the thermal oxide film 30 to form a cavity region (a region that is substantially evacuated). Is formed, the parasitic capacitance in the element isolation region can be reduced, and the element isolation capability can be improved.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. 4, 5 (a) to 8, and 9 (a) to 9 (a).
This will be specifically described with reference to FIG. FIG. 4 is a schematic plan view of an N-channel MOS transistor according to the second embodiment, which is shown in FIGS.
10A to 10C show cross sections along the line II in FIG. 4 in the order of steps. The second embodiment is an example in which the present invention is applied to an N-channel MOS transistor as in the first embodiment, but includes a step of sealing a hollow region and a step of forming a wiring layer to a source / drain diffusion layer. Are performed simultaneously, thereby reducing the number of processes. In the second embodiment, members and the like corresponding to the components and the like of the N-channel MOS transistor shown in the first embodiment are denoted by the same reference numerals.

First, as shown in FIG. 5A, a pad oxide film 12 is formed on the surface of a p-type semiconductor substrate 11 by a thermal oxide film method.
Is formed with a film thickness of 30 [nm]. A polysilicon film 13 and a silicon nitride film 14 are deposited thereon by CVD at a thickness of 100 nm and 50 nm, respectively.

Thereafter, the polysilicon film 13 and the silicon nitride film 14 are patterned by photolithography and etching so as to cover the element formation region. That is, the polysilicon film 13 and the silicon nitride film 14 formed in the element isolation region are removed.

Next, using the silicon nitride film 14 as a mask, the pad oxide film 12 in the element isolation region is removed by etching. After that, similarly using the silicon nitride film 14 as a mask, the semiconductor substrate 11 in the element isolation region is etched to form a trench 15 having a depth of 300 [nm] and a width of 300 [nm] in the semiconductor substrate 11.

Next, as shown in FIG. 5B, a thermal oxide film 16 is selectively formed to a thickness of 10 nm on the semiconductor substrate 11 in the trench 15 by a thermal oxidation method. Thereafter, the semiconductor substrate 1 including the trench 15 is formed by CVD.
1, a silicon nitride film 17 having a thickness of 150 to 200 [n].
m] is deposited.

Next, as shown in FIG. 5C, the silicon nitride film 17 is etched back by reactive ion etching (RIE) until the polysilicon film 13 is exposed (exposed). As a result, the silicon nitride film 17 can be buried only inside the trench 15. Further, the polysilicon film 13 is completely removed by etching back by the RIE method.

Next, as shown in FIG. 6A, a silicon nitride film is deposited on the semiconductor substrate 11 to a thickness of 150 [nm]. Thereafter, the silicon oxide film is etched back by the RIE method, so that the side wall of the silicon nitride film 17 has a sidewall nitride film 39 made of a silicon nitride film.
Is formed, and the silicon oxide film 12 formed in the element formation region is removed.

Next, as shown in FIG. 6B, a gate oxide film 19 is formed on the element formation region of the semiconductor substrate 11 by a thermal oxidation method. Thereafter, a gate electrode 20 made of polysilicon doped with phosphorus (P) and a cap oxide film 21 are sequentially deposited on the gate oxide film 19 by the CVD method. Thereafter, the cap oxide film 21 and the gate electrode 2 are formed by photolithography and etching.
0 and the gate oxide film 19 are sequentially patterned.

Then, after depositing a silicon oxide film 22 on the semiconductor substrate 11, the silicon oxide film 22 is etched back by the RIE method to form the gate electrode 2
A sidewall oxide film 22 made of a silicon oxide film is formed on the sidewall of the zero. Further, an n-type impurity, for example, arsenic is ion-implanted into the semiconductor substrate 11 in the element formation region using the cap oxide film 21 formed in the element formation region as a mask.

As a result, an arsenic ion-implanted layer can be formed in a self-aligned manner on the surface layer of the element formation region of the semiconductor substrate 11. Next, a heat treatment is performed on the semiconductor substrate 11 to activate the arsenic ion implanted layer, and the n ⁺ -type source region 23 and the drain region 24 formed of the arsenic ion implanted layer are formed on the surface layer of the semiconductor substrate 11 on both sides of the gate electrode. To form

Next, as shown in FIG.
A BPSG film 25 having a thickness of 450 [nm] is deposited on the entire surface of the semiconductor substrate 11 by a method. Thereafter, the semiconductor substrate 11 is subjected to a heat treatment (for example, temperature: 850 [° C.], time: 30 [mi].
n]), the surface layer of the BPSG film 25 is flattened. Thereafter, a silicon nitride film 27 having a thickness of 100 [nm] is deposited on the BPSG film 25 by the CVD method.

Next, as shown in FIG. 7A, the silicon nitride film 27 is patterned by a photolithography technique and an etching technique, so that the silicon nitride film 27 on the silicon nitride film 17 has a diameter of 300 [nm].
Is formed, and at the same time, the source diffusion layer 23 is formed.
An opening is also formed at a position corresponding to the upper and drain diffusion layers 24. Further, a silicon nitride film 28 is deposited on the entire surface of the semiconductor substrate 11 to a thickness of 100 [nm].

Then, the silicon nitride film 28 is etched back by the RIE method to form the silicon nitride film 2.
A sidewall nitride film 28 made of a silicon nitride film 28 is formed on the side wall of the opening 7. Next, using the silicon nitride film 27 and the sidewall nitride film 28 as a mask, the BPSG film 25 is etched to form an opening 29 (diameter 1) reaching the surface layer of the silicon nitride film 17.
00 [nm]), and the openings 32 and 33 reaching the surface layers of the source layer 23 and the drain layer 24 are formed in the BPSG film 25.

Next, as shown in FIG.
By etching, for example, H _ThreePO_FourD.
Using a silicon nitride film 17, 27, 2
8 and the sidewall nitride film 39 are removed. The result
As a result, a cavity (void) region is formed in the trench 15.

In the second embodiment, the semiconductor substrate 11
Since the sidewall of the silicon nitride film 17 projecting upward is covered with the sidewall nitride film 39, the allowable range of the horizontal position of the opening 29 with respect to the silicon nitride film 17 can be widened. Therefore, even if the position of the opening 29 is slightly shifted, the silicon nitride film 17 can be surely removed via the sidewall nitride film 39.

Next, as shown in FIG. 7B, the entire surface is formed to a thickness of 100 [n] by sputtering or CVD.
m] of the titanium film (Ti) film 36 is formed. Since this titanium film 36 is formed on the surface layer of the source layer 23 and the drain layer 24, it has an effect of reducing the contact resistance of the wiring layer. The titanium film 36 passing through the opening 29
Is slightly deposited on the bottom surface of the trench 15.

Thereafter, a titanium nitride film (T.sub.T) having a thickness of about 20 nm is formed on the entire surface by sputtering or CVD.
iN) A film 37 is formed. The titanium nitride film 37 has the effect of preventing the diffusion and erosion of the wiring layer and improving the adhesion, and the surface layer of the source layer 23, the surface layer of the drain layer 24, and the opening 2
It is formed on the surface layer of the titanium film 36 formed on the side walls of 9, 32 and 33. The opening 2 is formed in the same manner as the titanium film 36.
The titanium nitride film 37 that has passed through 9 is also deposited on the titanium nitride film 36 formed on the bottom surface of the trench 15.

Next, as shown in FIG.
A tungsten (W) film 38 serving as a wiring layer having a thickness of about 400 [nm] is formed on the entire surface by the method. The openings 29 and the openings 32 and 33 can be filled with the tungsten film 38. Therefore, a wiring layer that is electrically connected to the source diffusion layer 23 and the drain diffusion layer 24 can be formed at the same time that the cavity region is closed and completed.

Thereafter, as shown in FIG.
The N-channel MOS transistor is completed by processing the tungsten film 38 on 5 into a predetermined wiring pattern.

As described above, in the method of manufacturing a semiconductor device according to the second embodiment of the present invention, a thermal oxide film 12 is formed on a semiconductor substrate 11, and the thermal oxide film 12 and the semiconductor substrate 11 are opened. Thus, a trench 15 is formed. afterwards,
After forming the thermal oxide film 16 on the inner wall of the trench 15,
A silicon nitride film 17 is buried in the trench 15 to form a trench isolation layer.

Next, after a MOS transistor is formed in the element formation region of the semiconductor substrate 11, a BPSG film 25 is deposited on the entire surface of the semiconductor substrate 11. After that, the surface layer of the BPSG film 25 is flattened. Next, a silicon nitride film 27 is sequentially deposited on the BPSG film 25.

Then, the silicon nitride film 27 buried in the trench 15, the silicon nitride film 27 located on the source diffusion layer 23 and the drain diffusion layer 24 are selectively removed, and the silicon nitride film 17 is left on the silicon nitride film 17. An opening is formed.
Next, the buried silicon nitride film 17 and the silicon nitride film 27 are removed by a wet etching method, so that a void is formed in the trench 15 and the opening 29. Openings 32 and 33 reaching the drain diffusion layer 24 are formed.

Next, the titanium film 36 and the titanium nitride film 37
Are sequentially formed, a tungsten film 38 is formed, and the upper portion of the opening 29 is sealed to form a cavity region (a region to be substantially evacuated). At the same time, the source diffusion layer 23 and the drain diffusion layer 24 are electrically connected. A wiring layer to be connected is formed.

Thereafter, by processing the tungsten film 38 on the BPSG film 25 into a predetermined wiring pattern,
The N-channel MOS transistor is completed.

In the second embodiment configured as described above, a tungsten film 38 is formed to close a cavity region, and a wiring layer electrically connected to the source diffusion layer 23 and the drain diffusion layer 24 is formed. It can be formed simultaneously. Therefore, a step for closing the cavity region can be omitted, and the number of steps in forming the N-channel MOS transistor can be reduced as a whole.

Note that, in the second embodiment, FIG.
The openings 29, 32, and 33 shown in (1) are formed at the same time, but they may be formed in another step. FIG. 6C in this case.
9A to 10 as modified examples of the following manufacturing process.
It is shown in (c).

As shown in FIG. 9A, the silicon nitride film 2 is formed by photolithography and etching.
7 is patterned to form a silicon nitride film 17.
The silicon nitride film 27 has a diameter of 300
An opening (hole) of [nm] is formed. Further, a silicon nitride film 28 having a thickness of 100 [n] is formed on the entire surface of the semiconductor substrate 11.
m].

Then, the silicon nitride film 28 is etched back by the RIE method so that the silicon nitride film 2
The sidewall nitride film 28 made of the silicon nitride film 28 is formed on the side wall of the opening 31 of FIG. Next, by using the silicon nitride film 27 and the sidewall nitride film 28 as a mask, the BPSG film 25 is etched to form the opening 29 reaching the surface layer of the silicon nitride film 17.
(100 [nm] in diameter) is formed on the BPSG film 25.

Next, as shown in FIG.
By etching, for example, H _ThreePO_FourD.
Using a silicon nitride film 17, 27, 2
8 and the sidewall nitride film 39 are removed. The result
As a result, a cavity (void) region is formed in the trench 15.

Next, as shown in FIG. 9C, by photolithography and subsequent dry etching,
A resist film 40 having an opening is formed on the source layer 23 and the drain layer 24. Then, the BPSG film 25 is etched using the resist film 40 as a mask to form openings 32 and 33 reaching the surface layers of the source layer 23 and the drain layer 24.

Next, after the resist film 40 is removed by an ashing process, as shown in FIG. 10A, a thickness of 100 [nm] is formed on the entire surface by a sputtering method or a CVD method.
A degree of titanium film 36 is formed. Thereafter, a titanium nitride film 37 having a thickness of about 20 [nm] is formed on the entire surface by sputtering or CVD.

Next, as shown in FIG.
A tungsten (W) film 38 having a thickness of about 400 [nm] is formed on the entire surface by Method D. The opening 29 is filled with the tungsten film 38 and the openings 32 and 33 are formed.
Can also be filled. Therefore, a wiring layer that is electrically connected to the source diffusion layer 23 and the drain diffusion layer 24 can be formed at the same time when the cavity region is completed.

Thereafter, as shown in FIG.
The N-channel MOS transistor is completed by processing the tungsten film 38 on the SG film 25 into a predetermined wiring pattern.

According to the modification of the second embodiment configured as described above, when the silicon nitride film 17 is removed by etching, the BPSG film 25 is formed on the source diffusion layer 23 and the drain diffusion layer 24. Since it remains as it is, damage to the source diffusion layer 23 and the drain diffusion layer 24 due to etching can be prevented.

(Third Embodiment) Next, a third embodiment of the present invention will be described in detail with reference to FIG. 11 and FIGS. FIG. 11 is a schematic diagram showing a plan configuration of an N-channel MOS transistor according to the third embodiment. FIGS.
2A to 2C show cross sections along the line I-II in the order of steps.
The third embodiment is an example in which the present invention is applied to an N-channel MOS transistor as in the first embodiment. However, an element isolation structure using a cavity region and a trench element isolation structure coexist on the same semiconductor substrate. It is characterized by
In the third embodiment, members and the like corresponding to the components and the like of the N-channel MOS transistor shown in the first embodiment and the second embodiment are denoted by the same reference numerals.

First, as shown in FIG. 12A, a pad oxide film 1 is formed on the surface of a p-type semiconductor substrate 11 by a thermal oxide film method.
2 is formed with a thickness of 30 [nm]. A polysilicon film 13 and a silicon nitride film 14 are deposited thereon by CVD at a thickness of 100 nm and 50 nm, respectively.

Thereafter, the polysilicon film 13 and the silicon nitride film 14 are patterned by photolithography and etching so as to cover the element formation region. That is, the polysilicon film 13 and the silicon nitride film 14 formed in the element isolation region are removed.

Next, using the silicon nitride film 14 as a mask, the pad oxide film 12 in the element isolation region is removed by etching. After that, similarly using the silicon nitride film 14 as a mask, the semiconductor substrate 11 in the element isolation region is etched to form a trench 15 having a depth of 300 [nm] and a width of 300 [nm] in the semiconductor substrate 11.

Next, as shown in FIG. 12B, a thermal oxide film 16 having a thickness of 10 [nm] is selectively formed on the semiconductor substrate 11 in the trench 15 by a thermal oxidation method. Thereafter, the semiconductor substrate 1 including the trench 15 is formed by CVD.
1, a silicon nitride film 17 having a thickness of 150 to 200 [n].
m] is deposited.

Next, as shown in FIG. 12C, the silicon nitride film 17 is etched back by reactive ion etching (RIE) until the polysilicon film 13 is exposed (exposed). As a result, the silicon nitride film 17 can be buried only inside the trench 15. Further, the polysilicon film 13 is completely removed by etching back by the RIE method.

Next, as shown in FIG. 13A, a silicon nitride film is deposited on the semiconductor substrate 11 to a thickness of 150 [nm]. Thereafter, the silicon oxide film is etched back by the RIE method, so that the sidewall nitride film 3 made of the silicon nitride film is formed on the side wall of the silicon nitride film 17.
9 is formed, and the silicon oxide film 12 formed in the element formation region is removed.

Next, as shown in FIG. 13B, a gate oxide film 19 is formed on the element formation region of the semiconductor substrate 11 by a thermal oxidation method. Thereafter, a gate electrode 20 made of polysilicon doped with phosphorus (P) and a cap oxide film 21 are sequentially deposited on the gate oxide film 19 by the CVD method. Thereafter, the cap oxide film 21 and the gate electrode 2 are formed by photolithography and etching.
0 and the gate oxide film 19 are sequentially patterned.

Thereafter, after depositing a silicon oxide film 22 on the semiconductor substrate 11, the silicon oxide film 22 is etched back by the RIE method to form the gate electrode 2
A sidewall oxide film 22 made of a silicon oxide film is formed on the sidewall of the zero. Further, an n-type impurity, for example, arsenic is ion-implanted into the semiconductor substrate 11 in the element formation region using the cap oxide film 21 formed in the element formation region as a mask.

As a result, an arsenic ion-implanted layer can be formed in a self-aligned manner on the surface of the semiconductor substrate 11 in the element formation region. Next, heat treatment is performed on the semiconductor substrate 11 to activate the arsenic ion implanted layer, so that the n ⁺ -type source region 23 and the drain region 24 formed of the arsenic ion implanted layer are formed on the surface layer of the semiconductor substrate 11 on both sides of the gate electrode. To form Further, a p-type impurity diffusion layer 41 is formed on the surface layer of the semiconductor substrate 11 other than on both sides of the gate electrode. The p-type impurity diffusion layer 41 is formed by a method of forming the gate electrode and the source region 2.
A resist film (not shown) covering the semiconductor substrate 11 including the third and drain regions 24 is formed, and the resist film is removed in other regions. Then, a p-type impurity is introduced into the surface layer of the semiconductor substrate 11 using the resist film as a mask. After the formation of the impurity diffusion layer 41, the resist film is removed.

Next, as shown in FIG.
The BPSG film 25 is deposited to a thickness of 450 [nm] on the entire surface of the semiconductor substrate 11 by the method D. Thereafter, a heat treatment (for example, temperature: 850 [° C.], time: 30 [m]
in]), the surface layer of the BPSG film 25 is flattened. Thereafter, a silicon nitride film 27 having a thickness of 100 [nm] is deposited on the BPSG film 25 by the CVD method.

Next, as shown in FIG. 14A, by patterning the silicon nitride film 27 by photolithography and etching, the silicon nitride film 27 on the silicon nitride film 17 has a diameter of 300 [n].
m] is formed. At this time, unlike the second embodiment, no opening is formed in the silicon nitride film 27 in the right region in FIG. Thereafter, a silicon nitride film 28 having a thickness of 100 is formed on the entire surface of the semiconductor substrate 11.
Deposit at [nm].

Then, the silicon nitride film 28 is etched back by the RIE method, thereby forming the silicon nitride film 2.
A sidewall nitride film 28 made of a silicon nitride film 28 is formed on the side wall of the opening 7. Next, using the silicon nitride film 27 and the sidewall nitride film 28 as a mask, the BPSG film 25 is etched to form an opening 29 (diameter 1) reaching the surface layer of the silicon nitride film 17.
00 [nm]) is formed on the BPSG film 25.

Next, as shown in FIG. 14B, the silicon nitride films 17, 27 and 27 are formed by wet etching using an etching solution such as an H ₃ PO ₄ solution.
28 and the sidewall nitride film 39 are removed. As a result, a cavity (void) region is formed in the trench 15,
Element isolation is achieved by this cavity region.

Here, the silicon nitride film 17 and the sidewall nitride film 39 filling the trench 15 in the region on the right side of FIG. 14B are not removed.
7, element isolation is achieved.

FIG. 11 is a plan view showing the semiconductor substrate 11 from which the element has been separated. Here, FIG.
FIG. 2 is a schematic diagram in which the BPSG film 0 and the BPSG film 25 are omitted. As described above, in the region on the right side of FIG. 11, element isolation is achieved by the silicon nitride film 17 in which the trench 15 is buried, and in the region on the left side, element isolation is achieved by the cavity region. An impurity diffusion layer 41 is formed at the boundary between these different element isolation structures.

Also in the third embodiment, since the side wall of the silicon nitride film 17 projecting above the semiconductor substrate 11 is covered with the sidewall nitride film 39, the horizontal position of the opening 29 with respect to the silicon nitride film 17 is set. Can be widened. Therefore, even if the position of the opening 29 is slightly shifted, the silicon nitride film 17 can be surely removed via the sidewall nitride film 39.

Thereafter, by thermally oxidizing the polysilicon film 26, the polysilicon film 26 in the upper region of the opening 29 becomes a thermal oxide film 30, and the opening 29 is sealed.
In this manner, by thermally oxidizing the polysilicon film 26 formed in advance, even if a large number of openings 29 are formed, the polysilicon film 26 can be easily sealed.

Next, as shown in FIG. 15, the thermal oxide film 30 and the BPSG film 25 are selectively removed by photolithography and subsequent dry etching, so that the opening 42 reaching the impurity diffusion layer 41 is formed. To form Then, an aluminum film is formed by sputtering, and the pattern is formed.
This forms aluminum wiring layer 43 connected to impurity diffusion layer 41.

Here, it is possible to apply a substrate potential from the aluminum wiring layer 43 to the semiconductor substrate 11 via the impurity diffusion layer 41.

Although not shown, the semiconductor device according to this embodiment is manufactured by continuing the wiring process in order to set the semiconductor substrate 11, the gate electrode 20, the source 23, and the drain 24 to appropriate potentials.

As described above, according to the third embodiment of the present invention, a trench-type element isolation structure in which a silicon nitride film 17 is buried and an element isolation structure including a cavity region are provided on the same semiconductor substrate. Thereby, element isolation can be performed in accordance with the isolation ability. Therefore, it is possible to increase the element isolation capability of a specific region on the semiconductor substrate.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be specifically described with reference to FIGS. 16 and 17 (a) to 20 (b). FIG. 16 is a schematic diagram showing a plan configuration of an N-channel MOS transistor according to the fourth embodiment, and FIGS. 17A to 20B show FIGS.
6 is a cross-sectional view taken along a line III-III in FIG. The third embodiment is an example in which the present invention is applied to an N-channel MOS transistor as in the first embodiment. However, an SOI in which a semiconductor layer is provided on a semiconductor substrate via an insulating layer as a semiconductor substrate is provided. The difference is that an element isolation structure composed of a cavity region using a substrate is provided at the boundary between the memory cell region and the peripheral circuit region of the semiconductor memory and at the peripheral circuit region. Incidentally, also in the fourth embodiment, the N-channel MOS shown in the first to third embodiments is used.
The same reference numerals are given to members and the like corresponding to the components and the like of the transistor.

First, as shown in FIG. 17A, a silicon semiconductor layer 53 is formed on a semiconductor substrate 51 with an insulating layer 52 interposed therebetween.
Is prepared, and a pad oxide film 12 having a thickness of 30 [nm] is formed on the surface of the p-type silicon semiconductor layer 53 by a thermal oxide film method. On top of that, CV
By a method D, a polysilicon film 13 and a silicon nitride film 14 are deposited to a thickness of 100 [nm] and 50 [nm], respectively.

Thereafter, the polysilicon film 13 and the silicon nitride film 14 are patterned by photolithography and etching so as to cover the element formation region. That is, the polysilicon film 13 and the silicon nitride film 14 formed in the element isolation region are removed.

Next, using the silicon nitride film 14 as a mask, the pad oxide film 12 in the element isolation region is removed by etching. After that, similarly using the silicon nitride film 14 as a mask, the silicon semiconductor layer 53 in the element isolation region is etched to form a trench 15 having a depth of 300 [nm] and a width of 300 [nm] in the semiconductor substrate 11. At this time, the trench 15 is formed so as to reach the insulating layer 52 of the SOI substrate 50.

Next, as shown in FIG. 17B, the silicon semiconductor layer 5 in the trench 15 is formed by a thermal oxidation method.
In step 3, a thermal oxide film 16 is formed to a thickness of 10 nm. Thereafter, the SO including the trench 15 is formed by CVD.
A silicon nitride film 17 having a film thickness of 150 to 20
0 [nm] is deposited.

Next, as shown in FIG. 17C, the silicon nitride films 14, 17 are etched back by reactive ion etching (RIE) until the polysilicon film 13 is exposed (exposed). As a result, the silicon nitride film 17 can be buried only inside the trench 15. Further, the polysilicon film 1 is formed by the RIE method.
3 is completely removed by etching back.

Next, as shown in FIG. 18A, after the pad oxide film 12 exposed on the surface is removed, the surface of the silicon semiconductor layer 53 is subjected to a heat treatment to thereby form a field shield gate insulating film. 44 is formed. Then, a conductive polysilicon film 45 is formed on the field shield gate insulating film 44 by the CVD method, and a silicon oxide film 46 is formed on the polysilicon film 45.

Thereafter, both the silicon oxide film 46 and the polysilicon film 45 are patterned by photolithography and subsequent dry etching.

Next, as shown in FIG.
A silicon oxide film is deposited on the I-substrate 50 to a thickness of about 150 [nm]. Thereafter, the silicon oxide film is etched back by the RIE method to thereby form the silicon nitride film 1.
On the side walls of the patterned silicon oxide film 46 and the polysilicon film 45, a sidewall oxide film 18 made of a silicon oxide film is formed. Here, the polysilicon film 45 functions as a shield plate electrode.
In the area on the left side shown in FIG. 2B, element isolation is performed by a field shield element isolation structure 54. After that, the silicon oxide film 12 formed in the element formation region is removed. The shield plate electrode performs element isolation by fixing it to a certain electrode, for example, a ground (ground) or 1/2 V _CC voltage.

In the fourth embodiment, the region separated by the field shield device isolation structure 54 is used as a memory cell region.

Next, as shown in FIG. 18C, a gate oxide film 19 is formed on the element formation region of the silicon semiconductor layer 53 by a thermal oxidation method. Thereafter, a gate electrode 20 made of polysilicon doped with phosphorus (P) and a cap oxide film 21 are sequentially deposited on the gate oxide film 19 by the CVD method. Thereafter, the cap oxide film 21, the gate electrode 20, and the gate oxide film 19 are sequentially patterned by photolithography and etching.

Thereafter, after depositing a silicon oxide film 22 on the SOI substrate 50, the silicon oxide film 22 is etched back by the RIE method to form the gate electrode 2.
A sidewall oxide film 22 made of a silicon oxide film is formed on the sidewall of the zero. Further, using the cap oxide film 21 formed in the element formation region as a mask,
An n-type impurity, for example, arsenic is ion-implanted into the I substrate 50.

As a result, an arsenic ion-implanted layer can be formed in a self-aligned manner on the surface of the element formation region of the silicon semiconductor layer 53. Next, by subjecting the SOI substrate 50 to heat treatment, the arsenic ion implanted layer is activated, and the n ⁺ -type source region 23 and the drain An area 24 is formed. The impurity diffusion layer 41 is formed on the surface of the silicon semiconductor layer 53 other than on both sides of the gate electrode. The source region 23 and the drain region 24 are formed by ion-implanting the surface layer of the silicon semiconductor layer 53 in the boundary region between the field shield plate electrode 45 and the trench 15 with a resist film (not shown). After the formation of the source and the drain, the resist pattern is removed.

Next, as shown in FIG.
A 450 nm thick BPSG film 25 is deposited on the entire surface of the SOI substrate 50 by Method D. After that, the SOI substrate 50
Heat treatment (for example, temperature: 850 [° C.], time: 30
[Min], the surface layer of the BPSG film 25 is flattened. Then, the BPSG film 2 is formed by the CVD method.
A silicon nitride film 27 having a thickness of 100 [nm] is deposited on the substrate 5.

Next, as shown in FIG. 19B, by patterning the silicon nitride film 27 by photolithography and etching, the silicon nitride film 27 on the silicon nitride film 17 has a diameter of 300 [n].
m] is formed. Thereafter, a silicon nitride film 28 is formed on the entire surface of the SOI substrate 50 to a thickness of 100 [n].
m].

Then, the silicon nitride film 28 is etched back by the RIE method to form the silicon nitride film 2.
A sidewall nitride film 28 made of a silicon nitride film 28 is formed on the side wall of the opening 7. Next, using the silicon nitride film 27 and the sidewall nitride film 28 as a mask, the BPSG film 25 is etched to form an opening 29 (diameter 1) reaching the surface layer of the silicon nitride film 17.
00 [nm]) is formed on the BPSG film 25.

Next, as shown in FIG. 20A, the silicon nitride films 17, 27 and 27 are formed by wet etching using an etching solution such as an H ₃ PO ₄ solution.
28 and the sidewall nitride film 39 are removed. As a result, a cavity (void) region is formed in the trench 15,
Element isolation is achieved by this cavity region.

Here, the region separated by the cavity region is used as a peripheral circuit region of the memory cell.

FIG. 16 is a plan view showing an SOI substrate 50 in which element isolation has been performed. Here, FIG.
FIG. 2 is a schematic diagram in which the BPSG film 0 and the BPSG film 25 are omitted. As described above, in the region on the right side of FIG. 16, element isolation is achieved by the cavity region formed in the trench 15, and in the region on the left side, element isolation is achieved by the field shield element isolation structure 54. An impurity diffusion layer 41 is formed at the boundary between these different element isolation structures.

Thereafter, the polysilicon film 26 is subjected to thermal oxidation, so that the polysilicon film 26 in the upper region of the opening 29 becomes a thermal oxide film 30 and the opening 29 is sealed.
In this manner, by thermally oxidizing the polysilicon film 26 formed in advance, even if a large number of openings 29 are formed, the polysilicon film 26 can be easily sealed.

Next, as shown in FIG. 20B, the thermal oxide film 30 and the BPSG film 25 are selectively removed by photolithography and subsequent dry etching to reach the impurity diffusion layer 41. An opening 42 is formed. A p-type impurity is introduced into the surface layer of the silicon semiconductor layer 53 through the opening 42 by, for example, an ion implantation method to form a p-type impurity diffusion layer 41. In a later step, the p-type impurity may be diffused by performing a heat treatment on the silicon semiconductor layer 53. Then, an aluminum film is formed by sputtering and patterned to form an aluminum wiring layer 43 connected to the impurity diffusion layer 41.

Here, a substrate potential can be applied to the semiconductor substrate 11 from the aluminum wiring layer 43 via the impurity diffusion layer 41. In the memory cell region, the device is isolated by the field shield device isolation structure 54, so that the substrate potential can be simultaneously applied to each active region. Thus, the threshold value of the transistor in the memory cell region can be stabilized.

Although not shown, in order to set the SOI substrate 50, the gate electrode 20, the source 23, and the drain 24 to appropriate potentials, the semiconductor device according to the present embodiment is manufactured by continuing the wiring process.

When an SOI substrate is used as a semiconductor substrate as in the fourth embodiment, after removing the silicon nitride films 17, 27 and 28 in the step shown in FIG. Wet etching for removing the insulating layer 52 of the substrate 50 may be performed.

FIG. 21 shows a modification in which the cavity (gap) region in the trench 15 is expanded in the lateral direction by this wet etching. By expanding the cavity (gap) region in the lateral direction, it is possible to further increase the element isolation capability in the memory cell region. In this case, as shown in FIG. 21, the insulating layer 52 of the SOI substrate 50 is removed in a quarter circle shape, and the silicon semiconductor layer 53 above the removed region is exposed.

As described above, according to the fourth embodiment of the present invention, the SOI substrate 50 in which the silicon semiconductor layer 53 is provided on the semiconductor substrate 51 with the insulating layer 52 interposed therebetween.
The trench 15 is allowed to reach the insulating layer 52 to form an element isolation structure including a cavity region. Accordingly, each element active region in the peripheral circuit region can be electrically independent, and the speed of the transistors in the peripheral circuit region can be increased.

Then, the peripheral circuit region can be reliably separated from the memory cell forming region partitioned by the field shield element isolation structure 54. Further, since the memory cell formation region is element-isolated by the field shield element isolation structure 54, the substrate potential can be applied from the aluminum wiring layer 43 through the impurity diffusion layer 41 to the entire region of the memory cell region. It is possible to stabilize the threshold value of the transistor in the cell region.

For example, SOI substrate 5 having insulating layer 52
FIG. 22 shows an overall configuration diagram of a semiconductor device composed of zeros. As described above, the semiconductor device is partitioned into four blocks, and blocks 1 and 2 are configured as memory cell areas, and blocks 3 and 4 are configured as peripheral circuit areas. 4th
As described in the first embodiment, it is preferable that the element isolation in the memory cell region (block 1 and block 2) be performed by the field shield element isolation structure 54. Further, the element isolation of the block 3 in the peripheral circuit area may be performed by the field shield element isolation structure 54, and the element isolation of the block 4 may be performed by the element isolation structure by the cavity region formed in the trench 15.

As a result, in the blocks 1, 2, 3 partitioned by the field shield element isolation structure 54,
By applying the substrate potential, the variation in the threshold value of the transistor can be minimized, and in the block 4 in which each element active region is independent, the operation speed of the transistor can be increased to be a high performance region. is there.

In this case, the element isolation structure for partitioning the blocks 1 to 4 has an SO structure so that an electric field is not transmitted between the blocks.
The blocks 1 to 4 are made electrically independent as an element isolation structure formed by a void region formed in the trench 15 reaching the insulating layer 52 of the I-substrate 50.

In the fourth embodiment, the method of applying the substrate potential to the memory cell formation region to stabilize the threshold value of the transistor in the memory cell formation region has been described.
In the peripheral circuit region, a guard ring effect can be provided for an electric field from a peripheral memory cell region or another peripheral circuit region.

For example, as shown in FIG. 23, a plurality of element active regions in the block 4 which is a peripheral circuit region are partitioned by an element isolation structure comprising a void region reaching the insulating layer 52, and each is electrically independent. It is configured as a region to be used. Then, an element active region 60 for providing a guard ring effect is formed so as to surround the block 4. By applying a predetermined potential to the element active region 60,
The block 4 can be guarded from the other blocks 1 to 3 so as to be an electrically independent area.

In this case too, block 1
4 and the element isolation structure surrounding the block 4 are designed so that an electric field is not transmitted between the blocks.
An element isolation structure including a void region reaching the insulating layer 52 of the OI substrate 50 is provided.

The division between the peripheral circuit area and the memory cell area is as follows.
As shown in a block 1 in FIG. 23, an element isolation structure including a void region reaching the insulating layer 52 may be formed in the block 1 so as to be divided into electrically independent blocks 1a and 1b. Also in this case, both of the blocks 1a and 1b may be used as a peripheral circuit formation region.

[0162]

According to the present invention, a void region can be stably formed as an element isolation structure, so that parasitic capacitance can be reduced and element isolation ability can be improved.

According to another feature of the present invention, it is easy to form an insulating film that seals the upper part of the void region, so that it is suitable for miniaturization, and the voids (cavities) are formed in the element isolation regions of various dimensions. Can be formed.

Further, according to another feature of the present invention, the formation of the conductive film for sealing the upper part of the gap can be performed simultaneously with the formation of the wiring layer of the semiconductor element, so that the number of manufacturing steps can be reduced. .

According to the present invention, it is possible to form an element isolation structure composed of a void region in a specific region on a semiconductor substrate, and to enhance the element isolation capability of the region.

According to the present invention, in a semiconductor device in which a memory cell and a peripheral circuit of the memory cell are formed,
By using the SOI substrate, the electrical isolation between the memory cell region and the peripheral circuit region can be reliably performed by the void region. In particular, the element isolation region in the peripheral circuit region can be enhanced to electrically connect the element formation region. It is possible to realize high-speed operation independently.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a schematic plan view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 6 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 7 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 8 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 11 is a schematic plan view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

FIG. 13 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

FIG. 14 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps.

FIG. 15 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps.

FIG. 16 is a schematic plan view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 17 is a schematic sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 18 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 19 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 20 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 21 is a schematic sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 22 is a schematic plan view illustrating an overall configuration of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 23 is a schematic plan view showing another example of the overall configuration of the semiconductor device according to the fourth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 11 semiconductor substrate 12 pad oxide film 13 polysilicon film 14 silicon nitride film 15 trench 16 thermal oxide film 17 silicon nitride film 18 sidewall oxide film 19 gate oxide film 20 gate electrode 21 cap oxide film 22 sidewall oxide film 23 source region 24 Drain region 25 BPSG film 26,45 polysilicon film 27 silicon nitride film 28 sidewall nitride film 29,32,33,42 opening 30 thermal oxide film 36 titanium film 37 titanium nitride film 38 tungsten film 39 side wall nitride film 40 resist 41 p-type impurity diffusion layer 44 field shield gate insulating film 43 aluminum wiring layer 46 silicon oxide film 50 SOI substrate 51 semiconductor substrate 52 insulating layer 53 silicon semiconductor layer 54 field shield element isolation structure 60 device active area

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 21/76 D

Claims (30)

[Claims] A first element isolation structure formed on a semiconductor substrate and a second element isolation structure formed on the semiconductor substrate, wherein the semiconductor substrate includes a first element isolation structure defined by the first element isolation structure. A second element active region defined by the region and the second element isolation structure, wherein the first element isolation structure comprises a first groove formed in the semiconductor substrate; A first cavity region formed in the first groove portion, wherein the second element isolation structure is one of an element isolation structure made of an insulating film and a field shield element isolation structure provided with electrodes. A semiconductor device characterized by comprising: 2. A first insulating film formed on the semiconductor substrate including the first groove, and a second insulating film formed on the first insulating film on the first groove.
2. The semiconductor device according to claim 1, further comprising: a cavity region formed by connecting the first and second cavity regions. 3. 3. A semiconductor device comprising: a second groove formed in the first insulating film on the first groove; and the first insulating film and a conductive film formed in the second groove. The semiconductor device according to claim 1, wherein the cavity region is hermetically sealed. 4. One of the first and second device active regions is a memory cell forming region, and the other of the first and second device active regions is a peripheral circuit forming region. The semiconductor device according to claim 1, wherein: 5. The semiconductor device according to claim 1, wherein an insulating layer is formed in at least a part of the semiconductor substrate.
5. The semiconductor device according to any one of items 4 to 4. 6. A first groove formed in a semiconductor substrate, a first insulating film formed on the semiconductor substrate including the first groove, and at least a part of the first groove. A second cavity formed in the first insulating film on the first groove.
Wherein the cavity region is sealed by a conductive film formed in the first insulating film and the second groove. 7. A groove formed in a semiconductor substrate, a first insulating film formed on the semiconductor substrate including the groove, and a first void region formed in the first insulating film on the groove. And a second void region formed in at least a part of the groove, wherein the first and second void regions are connected to form a cavity region. . 8. The semiconductor device according to claim 7, wherein a second insulating film is formed on said first insulating film, and said cavity region is sealed by said second insulating film. . 9. The semiconductor device according to claim 8, wherein the thickness of the second insulating film is equal to or larger than the width of the first gap region. 10. The semiconductor device according to claim 7, wherein the first insulating film has an opening reaching the second gap region. 11. The method according to claim 10, wherein a second insulating film is formed on the first insulating film, and a thickness of the first insulating film is equal to or larger than a width of the opening. 13. The semiconductor device according to claim 1. 12. The semiconductor device according to claim 7, wherein a third insulating film is filled in the trench in a part of the region. 13. The semiconductor device according to claim 7, further comprising a fourth insulating film in at least a part of the semiconductor substrate.
3. The semiconductor device according to claim 1. 14. The semiconductor device according to claim 1, wherein a part of the bottom of the groove is formed on a part of the fourth insulating film.
4. The semiconductor device according to 3. 15. The method according to claim 15, wherein the semiconductor substrate is an SOI, SIMO
The semiconductor device according to claim 7, wherein the substrate is one of X substrates. 16. The semiconductor device according to claim 13, wherein the fourth insulating film is provided in a substantial area other than below the second gap area. 17. The semiconductor device according to claim 7, wherein a conductive film is formed on the first insulating film, and the hollow region is sealed by the conductive film. 18. The semiconductor device according to claim 7, wherein the semiconductor substrate includes an element active region defined by at least a part of the groove. 19. A groove formed in a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate including the groove, a first hole formed in at least a part of the groove, A first hole formed in the interlayer insulating film, and the first hole and the cavity region are connected to each other. 20. A semiconductor device comprising a memory cell region and a peripheral circuit region on the semiconductor substrate, wherein the void region is formed at least at a boundary between the memory cell region and the peripheral circuit region. Item 8. The semiconductor device according to item 7. 21. An element isolation of said peripheral circuit region by said gap region.
3. The semiconductor device according to claim 1. 22. The semiconductor device according to claim 7, wherein the trench in a part of the semiconductor substrate is filled with an insulating film, and the insulating film functions as the element isolation structure together with the void region. 13. The semiconductor device according to claim 1. 23. The semiconductor substrate, comprising: a semiconductor substrate having a semiconductor layer formed on a semiconductor substrate via an insulating layer; wherein the groove is formed so as to reach the insulating layer; The semiconductor device according to claim 7, wherein the insulating layer is connected. 24. A first step of forming a groove in an element isolation region of a semiconductor substrate, and a second step of burying a nitride film in the groove after selectively forming an oxide film in the groove. A third step of forming an interlayer insulating film so as to cover the entire surface of the semiconductor substrate including the groove, a fourth step of depositing a silicon film on the interlayer insulating film, and reaching a surface layer of the nitride film. A fifth step of forming an opening to be formed in the silicon film and the interlayer insulating film, a sixth step of removing the nitride film from the opening by a wet etching method, and thermally oxidizing the silicon film. 7. A method of manufacturing a semiconductor device, comprising: a step of sealing an opening, the method including a step of sealing a hollow region formed in the groove and in an opening region of the interlayer insulating film. 25. A first step of forming a groove in an element isolation region of a semiconductor substrate, and a second step of burying a first nitride film in the groove after selectively forming a thermal oxide film in the groove. A third step of sequentially depositing an interlayer insulating film, a silicon film, and a second nitride film on the entire surface of the semiconductor substrate; and a fourth step of forming at least a first opening in the second nitride film. A fifth step of forming a third nitride film on the second nitride film; and etching back the third nitride film to form a third nitride film on a side wall of the second nitride film. A sixth step of forming a sidewall nitride film made of a nitride film of the above, and using the second nitride film and the sidewall nitride film as a mask, the silicon film until a surface layer of the first nitride film is exposed. And the interlayer insulating film are sequentially etched so that the surface layer of the first nitride film is A seventh step of forming a second opening, and an eighth step of removing the first nitride film, the second nitride film, and the sidewall nitride film by a wet etching method. Manufacturing method of a semiconductor device. 26. A first step of forming a groove in an element isolation region of a semiconductor substrate, a second step of embedding a nitride film in the groove, and an element active region of the semiconductor substrate defined by the groove A third step of forming a semiconductor element on the substrate; a fourth step of forming an interlayer insulating film so as to cover the entire surface of the semiconductor substrate including the groove and the semiconductor element; and reaching a surface layer of the nitride film. A fifth step of forming both the first opening and the second opening in the semiconductor element reaching the surface layer of the semiconductor substrate in the interlayer insulating film;
(4) a sixth step of removing the nitride film from the first opening by a wet etching method to make the inside of the groove a void area; and embedding a conductive film in the first opening to remove the void area. A method of manufacturing a semiconductor device, comprising: sealing and electrically connecting the semiconductor element and the conductive film by burying the conductive film in the second opening. 27. A first step of forming a groove in an element isolation region of a semiconductor substrate, a second step of embedding a nitride film in the groove, and an element active region of the semiconductor substrate defined by the groove A third step of forming a semiconductor element on the substrate; a fourth step of forming an interlayer insulating film so as to cover the entire surface of the semiconductor substrate including the groove and the semiconductor element; and reaching a surface layer of the nitride film. A fifth step of forming a first opening in the interlayer insulating film; and a sixth step of removing the nitride film from the first opening by a wet etching method to make the inside of the groove a void area. Forming a second opening reaching the surface layer of the semiconductor substrate in the semiconductor element in the interlayer insulating film; and embedding a conductive film in the first opening to seal the gap region. And the second The method of manufacturing a semiconductor device, characterized in that it comprises an eighth step of electrically connecting the conductive film and the semiconductor element is embedded the conductive film in the mouth. 28. The semiconductor device according to claim 19, further comprising a conductive film formed in the first hole, wherein the hollow region is sealed by the conductive film. 29. An impurity diffusion layer formed on the surface layer of the semiconductor substrate, and a second impurity diffusion layer formed on the interlayer insulating film on the impurity diffusion layer.
Wherein the bottom of the second hole is a surface layer of the impurity diffusion layer, and has a conductive film formed in the second hole. The impurity diffusion layer and the conductive film 20. The semiconductor device according to claim 19, wherein the semiconductor device is electrically connected. 30. A semiconductor device comprising: an impurity diffusion layer formed on a surface layer of the semiconductor substrate; and a first conductive film formed in the first hole, wherein the first conductive film forms the cavity region. Is sealed, and a second layer formed on the interlayer insulating film on the impurity diffusion layer is formed.
Wherein the bottom of the second hole is a surface layer of the impurity diffusion layer, and has a second conductive film formed in the second hole. The impurity diffusion layer and the second 20. The semiconductor device according to claim 19, wherein the conductive film is electrically connected to the conductive film.