JP2016139693A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including an SOI substrate, which has a long creepage distance on a top edge side of an opening formed in an active layer without an increase in size to achieve improved withstand voltage.SOLUTION: A semiconductor device 100 comprises: an SOI substrate 10 in which a support substrate 12, an embedded insulation layer 14 and an active layer 16 are laminated; a first insulation film 20; a second insulation film 30; an interlayer insulation film 40; a trench 50 which pierces the second insulation film 30, the first insulation film 20 and the active layer 16 and has a cavity inside and has a top edge blocked by the interlayer insulation film 40; and a first side etching region 52 which is provided in the first insulation film 20 and lies adjacent to the trench 50 and has a cavity inside, which contacts the cavity inside the trench 50. The second insulation film 30 has an etching selectivity higher than that of the first insulation film 20. An opening width W1 of the first insulation film 20 is wider than an opening width Wa of the active layer 16 and wider than an opening width W2 of the second insulation film 30.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an SOI (Silicon On Insulator) substrate, an insulating film formed on the SOI substrate, and a trench separating element formation regions.

  A semiconductor device including an element isolation trench (hereinafter referred to as “trench”) that electrically isolates a plurality of semiconductor elements formed on a semiconductor substrate is known. In particular, when an SOI substrate having a buried insulating layer is used as a substrate wafer and a trench having a depth reaching the buried insulating layer is formed, the element forming regions are separated by an insulator, so that pn junction separation is used. Problems caused by parasitic capacitance and parasitic transistors are reduced.

  The breakdown voltage of the trench in such a semiconductor device depends on the opening width of the trench and the relative dielectric constant inside the trench. Although the withstand voltage can be improved by widening the opening width of the trench, there is a problem that the semiconductor device is enlarged.

  2. Description of the Related Art A semiconductor device in which a cavity is provided inside a trench is known for the purpose of improving the breakdown voltage of the trench. In Patent Document 1, an SOI substrate and a groove formed in an element isolation region of a semiconductor layer of the SOI substrate and reaching a buried insulating layer are provided, and a groove and a partial region of the buried insulating layer in contact with the groove are hollow. A semiconductor device is disclosed.

JP 2012-142505 A

FIG. 4 shows an example of a conventional semiconductor device having a cavity inside a trench. In such a semiconductor device, since the air layer having a relative dielectric constant lower than that of SiO ₂ is present in the trench, the withstand voltage in the trench is improved. However, at the upper part of the trench of such a semiconductor device, there is a problem that the creepage distance (broken line in FIG. 4) between the active layers (element forming layers) is shortened by the interlayer insulating film closing the upper end of the trench, and the withstand voltage is lowered. there were.

  In order to solve this problem, it is conceivable to expand the cavity region inside the trench upward (on the wiring side). In this case, the insulation that closes the upper end of the trench by the subsequent CMP (Chemical Mechanical Polishing) process is considered. The film is thinned to open the trench, and there is a possibility that a wiring material in the wiring forming process, a resist material for patterning, or the like may enter the cavity region inside the trench from the opening. In addition, it is conceivable to extend the upper region of the active layer in the trench in the lateral direction (element formation region side). However, since the opening is filled when forming the insulating film that closes the upper end of the trench, Expansion in the direction is also difficult.

  The present invention has been made to solve such a problem, and is a semiconductor device including an SOI substrate, and the creepage distance on the upper end side of the opening of the trench provided in the active layer without increasing the size. An object of the present invention is to provide a semiconductor device that is long and has a further improved breakdown voltage in the trench.

  A semiconductor device according to the present invention includes an SOI substrate on which a support substrate, a buried insulating layer and an active layer are stacked, a first insulating film formed on the active layer, and the first insulating film. A second insulating film formed on the second insulating film, an interlayer insulating film formed on the second insulating film, at least the second insulating film, the first insulating film, and the active layer A trench having a cavity inside and having an upper end closed by the interlayer insulating film, and provided in the first insulating film, adjacent to the trench, and inside the cavity inside the trench A first side etching region having a cavity in contact with the first insulating film, wherein the second insulating film has a higher etching selectivity than the first insulating film, and the first insulating film The provided trench and the first The width of the opening of the id etching region is wider than the width of the opening of the trench provided in the active layer and wider than the width of the opening of the trench provided in the second insulating film. It is characterized by that.

  According to the semiconductor device of the present invention, the trench is provided in the active layer without increasing its size by forming a wider cavity in the upper portion so as to cover the cavity inside the trench provided in the active layer. It is possible to provide a semiconductor device in which the creepage distance on the upper end side of the opening of the trench is long and the withstand voltage in the trench is further improved.

It is sectional drawing which shows an example of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of an example of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the other example of the semiconductor device which concerns on this embodiment. It is a figure which shows the schematic cross section of the conventional semiconductor device.

  DESCRIPTION OF EMBODIMENTS Hereinafter, a mode for carrying out the present invention (hereinafter referred to as the present embodiment) will be described with reference to the drawings. As shown in FIG. 1, the semiconductor device 100 according to the present embodiment includes a SOI substrate 10 on which a support substrate 12, a buried insulating layer 14, and an active layer 16 are stacked, and a first layer formed on the active layer 16. One insulating film 20, a second insulating film 30 formed on the first insulating film 20, an interlayer insulating film 40 formed on the second insulating film 30, and at least a second Provided in the first insulating film 20 and the trench 50 that penetrates the insulating film 30, the first insulating film 20, and the active layer 16, has a cavity inside, and is closed at the upper end by the interlayer insulating film 40. A first side etching region 52 provided adjacent to the opening of the trench 50 and having a cavity in contact with the cavity inside the trench 50.

  The semiconductor device 100 includes an SOI substrate 10 in which a support substrate 12, a buried insulating layer 14, and an active layer 16 are stacked. A plurality of elements (not shown) are formed on the active layer 16 of the SOI substrate 10. . In the semiconductor device 100, the trench 50 electrically isolates a region where an element is formed. In FIG. 1, the configuration repeated in the horizontal direction of the semiconductor device 100 is omitted.

  The semiconductor device 100 includes a first insulating film 20 formed on the active layer 16 of the SOI substrate 10 and a second insulating film 30 formed on the first insulating film 20. The second insulating film 30 is characterized in that the etching selectivity is higher than that of the first insulating film 20. “Etching selectivity” means the ratio of the etching rate of another member to the etching rate of a certain member. “High etching selectivity” means the etching rate of another member with respect to the etching rate of a certain member. Means small. It is assumed that the etching selectivity of the second insulating film 30 is higher than that of the first insulating film 20, and isotropic etching is performed after the trench 50 is formed, whereby the first insulating film 20 and the trench 50 are formed. An adjacent first side etching region 52 is provided.

The combination of the first insulating film 20 and the second insulating film 30 is not limited as long as the second insulating film 30 has a higher etching selectivity than the first insulating film 20. However, for example, there is a combination in which a SiO ₂ film is used as the first insulating film 20 and a silicon nitride film (SiN film), a silicon carbide film (SiC film), or the like is used as the second insulating film 30.

The semiconductor device 100 includes an interlayer insulating film 40 formed on the second insulating film 30. The interlayer insulating film 40 closes the upper end of the trench 50, thereby forming a cavity region inside the trench 50 and preventing a wiring material or a resist material from entering the cavity inside the trench 50. Examples of the material for forming the interlayer insulating film 40 include a SiO ₂ film (oxide film) and the like, and a CVD method such as TEOS (Tetra Ethyl Ortho Silicate) from the viewpoint of reliability regarding insulation and resistance to heat treatment in a subsequent process. It is preferably a SiO ₂ film formed by (Chemical Vapor Deposition).

  The trench 50 is formed so as to penetrate at least the second insulating film 30, the first insulating film 20 and the active layer 16. The trench 50 has a cavity inside by closing the upper end portion thereof with the interlayer insulating film 40.

  In the first side etching region 52, the second insulating film 30 has a higher etching selectivity than the first insulating film 20, and after forming the trench 50, the first side etching region 52 is subjected to isotropic etching. This is a region adjacent to the trench 50 provided in the insulating film 20. Since the semiconductor device 100 includes the first side etching region 52, the width W1 of the opening provided in the first insulating film 20 by the trench 50 and the first side etching region 52 (hereinafter referred to as “opening width W1”). Is wider than the width Wa of the opening provided in the active layer 16 by the trench 50 (hereinafter referred to as “opening width Wa”), and the opening provided in the second insulating film 30 by the trench 50. It has a characteristic structure that is wider than the width W2 (hereinafter referred to as “opening width W2”).

  In the semiconductor device 100, since the opening width W2 is narrower than the opening width W1, a space is formed inside the first side etching region 52 without being filled with the interlayer insulating film 40 between the first insulating films 20. . The semiconductor device 100 is characterized in that a cavity inside the first side etching region 52 and a cavity inside the trench 50 are in contact with each other, whereby the semiconductor device 100 is provided in the active layer 16. A cavity region wider than the opening is formed above the opening of the trench 50, the creepage distance on the upper end side of the opening of the trench 50 provided in the active layer 16 is increased, and the withstand voltage of the trench 50 is increased. Improvement can be achieved.

  The second side etching region 54 is a region provided in the buried insulating layer 14 and is sandwiched between the support substrate 12 and the active layer 16. Similar to the first side etching region 52, the second side etching region 54 is formed by performing isotropic etching after forming the trench 50. The semiconductor device 100 preferably includes the second side etching region 54. By providing the second side etching region 54, the width Wb of the opening provided in the buried insulating layer 14 by the trench 50 and the second side etching region 54 (hereinafter referred to as “opening width Wb”) is the opening width Wa. Wider than. As a result, a cavity wider than the opening is formed below the opening of the trench 50 provided in the active layer 16, and the creepage distance on the lower end side of the opening of the trench 50 provided in the active layer is increased. This is because the withstand voltage of the trench 50 is improved.

  The “opening width” in the semiconductor device 100 of the present embodiment refers to the trench 50 in the direction perpendicular to the longitudinal direction of the trench 50 formed in the semiconductor device 100 and, in some cases, the first side etching region 52 or the second side etching region 52. This means the distance between the first insulating films 20 and the like facing each other through the trench 50 and the like in the opening formed by the side etching region 54. In the semiconductor device 100 of this embodiment, the opening width W1 and the opening width Wa are substantially constant in the vertical direction due to the characteristics of the method of forming the trench 50. However, the semiconductor device 100 of this embodiment is provided in the active layer 16. As long as a wide cavity common to the trench 50 and the first side etching region 52 is formed so that the creepage distance on the upper end side of the opening of the trench 50 is increased, the opening widths W1 and Wa are However, the present invention is not limited to an aspect that is substantially constant in the vertical direction.

  On the other hand, the opening width W2 is represented by the minimum value of the distance between the second insulating films 30 facing each other through the opening of the trench 50 in the direction perpendicular to the longitudinal direction of the trench 50 formed in the semiconductor device 100. The Since the minimum value in the second insulating film 30 is narrower than the opening width W1, that is, the second insulating film 30 projects in a bowl shape above the first side etching region 52, the first side This is because a cavity is formed in the etching region 52. Further, the opening width Wb is defined between the embedded insulating layers 14 facing each other through the openings of the trench 50 and the second side etching region 54 in the direction perpendicular to the longitudinal direction of the trench 50 formed in the semiconductor device 100. Represented by the maximum distance. If the maximum value in the buried insulating layer 14 is wider than the opening width Wa between the active layers 16, the creepage distance on the lower end side of the opening of the trench 50 provided in the active layer 16 becomes long, and the withstand voltage of the trench 50 is increased. Is further improved.

  The opening width W1 and the opening width Wb are not particularly limited as long as they are wider than the opening width Wa and the mechanical strength of the semiconductor device 100 is maintained. For example, the opening width W1 is equal to the opening width Wa. In contrast, the opening width Wb is preferably 200% to 500%, and the opening width Wb is preferably 200% to 500% with respect to the opening width Wa.

  The opening widths W1, W2, Wa, and Wb are determined by cutting the semiconductor device 100 in a direction perpendicular to the longitudinal direction of the trench 50 using a dry etching device, a wet etching device, or the like, and through the trench 50 or the like in the appearing cross section. The distance between the respective layers can be obtained by measuring using a known measuring means such as an electron microscope.

  In the semiconductor device 100, the trench 50 is preferably formed so as to penetrate the buried insulating layer 14 and reach the support substrate 12. In other words, it is preferable that a part of the support substrate 12 is exposed inside the trench 50. This is because the second side etching region 54 can be easily formed by isotropic etching and the opening width W2 can be made wider than the opening width W1.

  Although not shown, the semiconductor device 100 according to the present embodiment includes an element in an element formation region surrounded by the trench 50 of the active layer 16, and includes a wiring, a protective film, and the like above the interlayer insulating film 40.

  A method for manufacturing the semiconductor device 100 will be described with reference to FIG.

  In the semiconductor device 100 according to the present embodiment, the first insulation film 20 is formed on the active layer 16 of the SOI substrate 10 on which the support substrate 12, the buried insulating layer 14, and the active layer 16 are stacked. A film forming step; a second insulating film forming step of forming the second insulating film 30 on the first insulating film 20; and at least the second insulating film 30, the first insulating film 20 and the active layer 16 A trench forming step for forming the penetrating trench 50; a side etching step for forming the first side etching region 52 by isotropic etching; an interlayer insulating film is formed, and the upper end portion of the trench 50 is closed; 50 and an interlayer insulating film forming step for forming a cavity inside the first side etching region 52.

  An SOI substrate 10 on which a support substrate 12, a buried insulating layer 14, and an active layer 16 shown in FIG. As shown in FIG. 2B, a first insulating film 20 is formed on the active layer 16 of the SOI substrate 10, and a second insulating film 30 is formed on the first insulating film 20. A mask oxide film 32 is formed on the second insulating film 30 as necessary.

The first insulating film 20 is formed by a known method such as a thermal oxidation method. As described above, the second insulating film 30 is formed using a material having an etching selectivity higher than that of the first insulating film 20. When a SiN film is formed as the second insulating film 30, it is formed by a CVD method using heat or plasma. In the case of forming a deep trench, the thickness required for the etching mask may not be ensured only with the resist pattern. Therefore, the etching mask can be thickened by forming a mask oxide film 32 on the second insulating film 30 as necessary. The mask oxide film 32 is made of, for example, SiO ₂ and is formed by a known method such as a CVD method.

  As shown in FIG. 2C, a trench 50 that penetrates at least the second insulating film 30, the first insulating film 20, and the active layer 16 and reaches the buried insulating layer 14 is formed. More specifically, after forming a resist pattern (not shown) having an opening at a portion where the trench 50 is to be formed on the second insulating film 30 using a photolithography method, the resist pattern is used as an etching mask to form the trench. 50 is formed. When the mask oxide film 32 is formed on the second insulating film, the resist pattern is formed on the mask oxide film 32.

  The trench 50 is formed by anisotropic etching such as RIE (Reactive Ion Etching). The trench 50 to be formed may reach the support substrate 12 through the buried insulating layer 14 as shown in FIG.

  The trench formation step may be performed by dividing it into a plurality of anisotropic etchings. In the case of performing multiple times, for example, the second insulating film 30 and the mask oxide film 32 formed as necessary are selectively etched using the resist pattern as an etching mask by a dry etching method, a wet etching method, or the like. Then, an opening is formed, then the resist pattern is removed, and the first insulating film 20 is formed by a dry etching method or the like using the second insulating film 30 and the mask oxide film 32 formed as necessary as a hard mask. The active layer 16 may be etched to form a trench 50 reaching the buried insulating layer 14.

  As shown in FIG. 2D, a portion of the first insulating film 20 in contact with the trench 50 is removed by isotropic etching, and a side etching process for forming a first side etching region 52 is performed. The isotropic etching at this time includes wet etching or dry etching by CDE (Chemical Dry Etching). In the side etching step, as shown in FIG. 2D, the portion in contact with the trench 50 in the buried insulating layer 14 can be removed to form the second side etching region 54.

  By forming the first insulating film 20 with a material having a low etching selectivity with respect to the second insulating film 30, the first side etching region 52 shown in FIG. 1 is formed, and the opening width W1 is the opening width. It becomes wider with respect to each of W2 and opening width Wa. As a result, a cavity region wider than the opening of the trench 50 provided in the active layer 16 is formed, the creepage distance between the active layers 16 in the upper part of the trench 50 is increased, and the withstand voltage of the trench 50 is further improved. .

  In order to further improve the withstand voltage of the trench 50, the second side etching region 54 is formed in the side etching process, so that the opening width Wb becomes wider than the opening width Wa and is provided in the active layer 16. A cavity region wider than the opening of the trench 50 is preferably formed. This is because the creepage distance on the lower end side of the opening of the trench 50 provided in the active layer 16 is increased, and the withstand voltage of the trench 50 is further improved.

  As shown in FIG. 2E, an interlayer insulating film 40 is formed on the second insulating film 30 to fill the opening provided in the second insulating film 30, and the upper end of the trench 50 is covered. A blocking interlayer insulating film forming step is performed.

The formation of the interlayer insulating film 40 is performed by, for example, a CVD method. The formation of the interlayer insulating film 40 by the CVD method is performed under low coverage conditions, specifically, under conditions such as a high pressure condition or a high power condition, as necessary, so that the trench 50 and the first side etching are performed. The upper end of the trench 50 is closed while maintaining the cavity inside the region. As described above, the interlayer insulating film 40 is preferably an oxide film (SiO ₂ film) formed using silane (SiH ₄ ), TEOS (Tetra Ethyl Ortho Silicate), or the like. Depending on the formation conditions of the interlayer insulating film 40, the material of the interlayer insulating film 40 is deposited on the side surface of the active layer 16 in the trench 50, the bottom surface of the trench 50, etc., but the distance to the creepage distance on the lower end side of the opening of the trench 50 is not limited. Since the influence is small, the influence of these deposits on the withstand voltage is small.

  In addition to the above-described steps, the semiconductor device 100 includes a step of forming an element in an element formation region surrounded by the trench 50, a step of planarizing the interlayer insulating film 40 by CMP or the like as necessary, and an interlayer insulating film. It is manufactured by performing a process of forming a wiring, a protective film, etc. on the upper part of 40.

[Example 1]
A specific example of the manufacturing method of the semiconductor device 100 according to the present embodiment will be described with reference to FIG. A first insulating film 20 made of SiO ₂ is formed on the surface of the active layer 16 of the SOI substrate 10 (FIG. 2A) on which the support substrate 12, the buried insulating layer 14 and the active layer 16 are laminated by thermal oxidation. Further, a second insulating film 30 made of SiN and a mask oxide film 32 are formed by CVD (FIG. 2B).

  After a photoresist (not shown) is formed on the mask oxide film 32, the mask oxide film 32 and the second insulating film 30 are selectively opened by a dry etching method or a wet etching method. After the photoresist is removed, the first insulating film 20, the active layer 16, and the buried insulating layer 14 are opened by dry etching using the mask oxide film 32 and the second insulating film 30 as hard resist. In this manner, a trench 50 reaching the support substrate 12 of the SOI substrate 10 is formed (FIG. 2C).

Next, side etching is performed to remove a portion adjacent to the trench 50 in each of the first insulating film 20 and the buried insulating layer 14 by isotropic etching such as wet etching or chemical dry etching (CDE). (FIG. 2 (d)). Thereby, the first side etching region 52 and the second side etching region 54 are formed. In an isotropic etching such as a wet etching method or a chemical dry etching method (CDE method), the SiN film as the second insulating film 30 has an etching selectivity with respect to the SiO ₂ film as the first insulating film 20. Since it is high, the opening width W2 is narrower than the opening width W1. In this step, the mask oxide film 32 is removed.

An interlayer insulating film 40 was formed on the second insulating film 30 by CVD, and the upper end of the trench 50 was closed (FIG. 2E). The formation of the interlayer insulating film 40 by the CVD method was performed by a normal pressure CVD method using silane (SiH ₄ ) and oxygen (O ₂ ). Thus, the upper end portion of the trench 50 was closed while maintaining the cavities inside the trench 50 and the first side etching region 52, and the semiconductor device 100 according to this embodiment was manufactured.

[Example 2]
Another specific example of the method for manufacturing the semiconductor device 100 according to the present embodiment will be described with reference to FIG. In the method shown in FIG. 3, as shown in FIG. 3C, the trench 50 formed in the trench formation step is a trench 50 reaching the buried insulating layer 14. After the trench formation step, as in the first embodiment, the side etching step of the first insulating film 20 and the buried insulating layer 14 shown in FIG. 3D and the interlayer insulating film 40 shown in FIG. The semiconductor device 100 according to this embodiment was manufactured in order.

  The semiconductor device 100 of this embodiment has been described by taking the semiconductor device 100 shown in FIG. 1 and the method of manufacturing the semiconductor device 100 shown in FIGS. 2 and 3 as examples. It is not limited to.

  10 SOI substrate, 12 support substrate, 14 buried insulating layer, 16 active layer, 20 first insulating film, 30 second insulating film, 32 mask oxide film, 40 interlayer insulating film, 50 trench, 52 first side Etching region, 54 Second side etching region, 100 semiconductor device, W1 opening width of first insulating film, W2 opening width between second insulating films 30, Wa opening width between active layers, Wb between buried insulating layers Opening width.

Claims (1)

An SOI substrate on which a support substrate, a buried insulating layer and an active layer are laminated;
A first insulating film formed on the active layer;
A second insulating film formed on top of the first insulating film;
An interlayer insulating film formed on the second insulating film;
A trench that penetrates at least the second insulating film, the first insulating film, and the active layer, has a cavity inside, and has an upper end blocked by the interlayer insulating film;
A first side etching region provided in the first insulating film, adjacent to the trench, and having a cavity in contact with the cavity inside the trench;
A semiconductor device comprising:
The second insulating film has a higher etching selectivity than the first insulating film,
The width of the opening of the trench and the first side etching region provided in the first insulating film is wider than the width of the opening of the trench provided in the active layer, and the second Wider than the width of the opening of the trench provided in the insulating film,
Semiconductor device.