JP2010087373A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device, forming a trench structure without any tiny grooves on the surface of a substrate. <P>SOLUTION: The manufacturing method of the semiconductor device performs steps of: forming the trench extending from the surface of a mask layer to the internal portion of the silicon layer, onto the substrate having the silicon layer, an interlayer insulating film, and the mask layer; retracting the interlayer insulating film by etching from a wall surface exposed in the trench; for chamfering the corner of the silicon layer by etching; forming a lateral space by etching the interlayer insulating film; forming a trench insulating film on the surface of the silicon layer by oxidizing the silicon layer exposed in the trench and the lateral space; filling the trench and the lateral space with polysilicon; forming a gap by etching in between the polysilicon and the mask layer; and forming a cap insulating film on the surface of the polysilicon. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device having a structure in which a trench is filled with polysilicon and the upper portion of the polysilicon in the trench is covered with silicon oxide.

For example, as disclosed in Patent Document 1, a trench is filled with polysilicon, and the upper portion of the polysilicon in the trench is covered with silicon oxide (hereinafter, this structure is referred to as a trench structure). There is known a semiconductor device having The trench structure is used, for example, for element isolation in a semiconductor substrate. A typical method for forming the trench structure is as follows.
As shown in FIG. 13, an interlayer insulating film 116, a first mask layer 118, and a second mask layer 120 are stacked on a substrate 112 having a silicon layer 114. The interlayer insulating film 116 is made of silicon oxide (SiO ₂ ), the first mask layer 118 is made of silicon nitride (SiN), and the second mask layer 120 is made of silicon oxide. Next, the second mask layer 120, the first mask layer 118, the interlayer insulating film 116, and the silicon layer 114 are selectively etched to form trenches 130 in the substrate 112 as shown in FIG. .
After the trench 130 is formed, the second mask layer 120 is wet etched. Thereby, as shown in FIG. 15, the second mask layer 120 is removed. At this time, the interlayer insulating film 116 is also etched from the wall surface exposed in the trench 130. Therefore, after etching, the wall surface of the interlayer insulating film 116 recedes as shown in FIG.
After the second mask layer 120 is removed, the silicon layer 114 is dry etched (isotropic etching). As a result, as shown in FIG. 16, the corner 134 at the boundary between the upper surface of the silicon layer 114 and the trench wall surface is chamfered. That is, the corner part 134 is formed into a gently curved surface. The reason why the corner portion 134 is chamfered is to prevent the electric field from concentrating on the corner portion 134 when the semiconductor device is used.
After chamfering the corner 134, the surface of the silicon layer 114 exposed in the trench 130 is oxidized by a thermal oxidation method or the like. As a result, as shown in FIG. 17, a trench insulating film 132 is formed on the exposed surface. Silicon expands in volume during oxidation. For this reason, the width of the trench 130 becomes narrow. This volume expansion also occurs in the depth direction of the trench 130 (that is, the vertical direction in FIG. 17). Therefore, the interlayer insulating film 116 near the trench 130 is pushed up by the grown trench insulating film 132 and deformed. As a result, a convex portion 116b is formed on the upper surface of the interlayer insulating film 116, and a taper shape in which the trench width increases as the wall surface 116a of the interlayer insulating film 116 moves upward.
After the trench insulating film 132 is formed, polysilicon is deposited on the substrate 112 and the deposited polysilicon is etched back. As a result, a polysilicon layer 136 is formed in the trench 130 as shown in FIG.
After the polysilicon layer 136 is formed, the surface (upper surface) of the polysilicon layer 136 is oxidized by a thermal oxidation method or the like. Thereby, as shown in FIG. 19, a cap insulating film 138 is formed on the polysilicon layer 136. After the cap insulating film 138 is formed, the first mask layer 118 is removed by etching. Thereby, the trench structure shown in FIG. 20 is completed.

JP-A-8-274157

  In the trench structure forming method described above, when the trench insulating film 132 is formed, the convex portion 116b is formed on the upper surface of the interlayer insulating film 116 (see FIG. 17). Further, since the trench insulating film 132 is formed after chamfering the corners 134 of the silicon layer 114, after the trench insulating film 132 is formed, the shape of the upper portion of the trench 130 becomes wider toward the upper side (FIG. 17). reference). Therefore, when the polysilicon layer 136 is subsequently filled, as shown in FIG. 18, a wide portion 136 a that extends in the width direction of the trench 130 is formed at the upper end portion of the polysilicon layer 136. The wide portion 136a is formed so that the thickness decreases toward the end in the width direction of the trench 130 (the end in the left-right direction in FIG. 17). Thereafter, when the surface of the polysilicon layer 136 is oxidized, a cap insulating film 138 having a different thickness depending on the position in the width direction is formed as shown in FIG. That is, in the vicinity of the end portion of the wide portion 136a, the thickness of the polysilicon is small, so that the silicon oxide is not formed thick. On the other hand, in the vicinity of the central portion of the wide portion 136a (the central portion in the left-right direction in FIG. 17), since the polysilicon is thick, the silicon oxide is formed thick. Therefore, as shown in FIG. 19, the cap insulating film 138 is thin near the end of the wide portion 136a and thick near the center of the wide portion 136a. For this reason, as shown in FIG. 20, a minute groove 140 is formed on the upper surface of the substrate 112 after the trench structure is formed (the boundary between the cap insulating film 138 and the interlayer insulating film 116). If the groove 140 exists on the upper surface of the substrate 112, a problem occurs when metal wiring is formed on the substrate 112 thereafter. That is, the metal wiring is formed by forming a metal layer on substantially the entire surface of the substrate 112 and then etching away unnecessary portions of the formed metal layer. As described above, when the groove 140 is present on the upper surface of the substrate 112, there is a problem that the metal layer residue remains in the groove 140 after the etching of the metal layer.

  The present invention was created in view of the above-described circumstances, and an object thereof is to provide a method for manufacturing a semiconductor device capable of forming a trench structure without forming a minute groove on the surface of a substrate. And

In the semiconductor device manufacturing method of the present invention, a semiconductor device having a structure in which polysilicon is filled in a trench and the upper portion of the polysilicon in the trench is covered with silicon oxide is manufactured. In this manufacturing method, a silicon layer and an interlayer insulating film made of silicon oxide are stacked on the silicon layer, and are stacked on the interlayer insulating film and made of a material having an etching selectivity with respect to silicon oxide. For a substrate having a mask layer, a trench forming step, a wall surface recessing step, a chamfering step, a lateral space forming step, a trench insulating film forming step, a polysilicon filling step, a polysilicon removing step, and a cap An insulating film forming step is performed. In the trench formation step, a trench reaching the inside of the silicon layer from the surface of the mask layer is formed in the substrate by etching the mask layer, the interlayer insulating film, and the silicon layer. In the wall surface receding step, the wall surface is receded by etching the interlayer insulating film from the wall surface exposed in the trench after the trench forming step. In the chamfering step, the corner of the boundary between the upper surface of the silicon layer and the trench wall surface is chamfered by etching the surface of the silicon layer exposed in the trench after the wall surface receding step. In the side space forming step, after the chamfering step, the interlayer insulating film is etched from the wall surface exposed in the trench, thereby forming a side space extending laterally from the wall surface of the trench. In the trench insulating film forming step, after the side space forming step, the silicon layer exposed in the trench and in the side space is oxidized to thereby insulate the surface of the exposed silicon layer from the silicon oxide. A film is formed. In the polysilicon filling process, the trench and the side space are filled with polysilicon after the trench insulating film forming process. In the polysilicon removing process, after the polysilicon filling process, the filled polysilicon is partially removed by etching to form a gap between the remaining polysilicon and the mask layer. In the cap insulating film forming step, a cap insulating film made of silicon oxide is formed on the surface of the polysilicon by oxidizing the surface of the remaining polysilicon after the polysilicon removing step.
In this manufacturing method, a side space forming step is performed after the chamfering step. That is, the interlayer insulating film is etched from the wall surface exposed in the trench, and the wall surface is further retracted to form a side space extending laterally from the wall surface of the trench. Thereafter, in the trench insulating film forming step, the silicon layer exposed in the trench and in the side space is oxidized to form a trench insulating film on the surface thereof. Silicon expands during oxidation. The volume expansion occurs not only in the thickness direction of the formed silicon oxide but also in the plane on which the silicon oxide is formed. That is, the trench insulating film formed on the wall surface of the trench greatly expands in the depth direction of the trench. Here, the wall surface of the interlayer insulating film is largely retracted from the trench by forming the side space. For this reason, the interlayer insulating film is hardly affected by the volume expansion of the trench insulating film grown on the wall surface of the trench. Therefore, it is possible to suppress the interlayer insulating film from being pushed up during the formation of the trench insulating film, and it is possible to suppress the convex portion from being formed on the upper surface of the interlayer insulating film. Further, since the side space is formed after the chamfering process, the bottom surface of the side space (that is, the surface of the silicon layer) has a substantially planar shape. For this reason, the surface of the trench insulating film formed in the side space has a substantially planar shape. Therefore, in the subsequent polysilicon filling process and polysilicon removing process, when polysilicon is left in the trench and in the side space, the thickness of the polysilicon in the side space becomes substantially constant. That is, formation of a thin portion in the polysilicon in the side space is suppressed. Therefore, in the subsequent cap insulating film forming step, the cap insulating film can be formed with a uniform thickness on the surface of the polysilicon. It is possible to suppress the cap insulating film from being partially thinned. As described above, according to the manufacturing method of the present invention, it is possible to suppress the formation of the protrusion on the upper surface of the interlayer insulating film and the partial thinning of the cap insulating film. Therefore, after the trench structure is formed, the formation of grooves on the surface of the substrate is suppressed.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, a trench structure can be formed while suppressing the formation of a groove on the surface of the substrate. Accordingly, when metal wiring is subsequently formed on the surface of the substrate, it is possible to prevent metal residues from remaining on the substrate surface.

  A method for manufacturing a semiconductor device according to the embodiment will be described. In the present embodiment, the semiconductor device having the element isolation trench structure shown in FIG. 1 is manufactured. In addition, since the manufacturing method of this embodiment has the characteristics in the formation method of a trench structure, description is abbreviate | omitted about the detail of the other semiconductor element structure.

(Lamination process)
The semiconductor device is manufactured from the substrate 12 made of the silicon layer 14 shown in FIG. First, as shown in FIG. 3, the interlayer insulating film 16 (silicon oxide film), the first mask layer 18 (silicon nitride layer), and the second mask layer 20 (silicon oxide layer) are stacked on the silicon layer 14. Form a structure. That is, first, the interlayer insulating film 16 is formed on the upper surface of the silicon layer 14 by thermal oxidation. Next, a first mask layer 18 is deposited on the interlayer insulating film 16 by CVD. Next, the second mask layer 20 is deposited on the first mask layer 18 by the CVD method.

(Trench formation process)
When the stacking process is completed, an opening 40 is formed in the stacked structure including the interlayer insulating film 16, the first mask layer 18, and the second mask layer 20, as shown in FIG. That is, first, a photoresist having an opening is formed on the second mask layer 20. Then, using the photoresist as a mask, the second mask layer 20 is etched until it reaches the first mask layer 18. Next, using the photoresist as a mask, the first mask layer 18 is etched until it reaches the interlayer insulating film 16. Next, using the photoresist as a mask, the interlayer insulating film 16 is etched until it reaches the silicon layer 14. When the etching of the interlayer insulating film 16 is completed, the photoresist is removed. As a result, an opening 40 reaching the silicon layer 14 is formed as shown in FIG.
After the opening 40 is formed, the silicon layer 14 is etched from the surface exposed in the opening 40 by the RIE method. Thereby, as shown in FIG. 5, a trench 30 reaching from the upper surface of the second mask layer 20 to the inside of the silicon layer 14 is formed. At this time, the second mask layer 20 is also physically etched at a low etching rate. Therefore, in FIG. 5, the second mask layer 20 is thin.

(Wall receding process)
When the trench formation step is completed, the substrate 12 is immersed in an etching solution for silicon oxide, and the second mask layer 20 and the interlayer insulating film 16 are wet-etched (isotropic etching).
Thereby, as shown in FIG. 6, the second mask layer 20 is removed.
The interlayer insulating film 16 is etched from the wall surface 16 a exposed in the trench 30. Therefore, as shown in FIG. 6, the wall surface 16a of the interlayer insulating film 16 recedes. That is, the width of the trench 30 is expanded in a range corresponding to the interlayer insulating film 16.

(Chamfering process)
When the second mask layer removing step is completed, the silicon layer 14 is etched by the CDE method (isotropic etching). Since the etching is isotropic, the corner 34 of the silicon layer 14 (the corner 34 at the boundary between the upper surface of the silicon layer 14 and the trench wall surface: see FIG. 6) is etched from both the upper surface side and the wall surface side. As a result, as shown in FIG. 7, the corner 34 is chamfered into a rounded shape.

(Side space formation process)
When the chamfering process is completed, the interlayer insulating film 16 is etched by the CDE method. That is, the interlayer insulating film 16 is etched from the wall surface 16 a in the trench 30. Thereby, as shown in FIG. 8, the wall surface 16a is further retracted. By retreating the wall surface 16a, a side space 50 extending laterally from the wall surface of the trench 30 is formed.

(Trench insulation film formation process)
When the side space forming step is completed, a trench insulating film 32 (silicon oxide film) is formed on the surface of the silicon layer 14 by thermal oxidation. That is, as shown in FIG. 9, the trench insulating film 32 is formed on the surface of the silicon layer 14 exposed in the trench 30 and the side space 50.
Here, the trench insulating film 32 grows with volume expansion. The volume expansion of the trench insulating film 32 is larger in the plane where the trench insulating film 32 is formed than in the thickness direction of the trench insulating film 32. That is, the trench insulating film 32 grown on the wall surface of the trench 30 is greatly expanded in the depth direction of the trench 30, and the trench insulating film 32 formed on the bottom surface of the side space 50 (upper surface of the silicon layer 14) is the trench 30. The volume expands greatly in the width direction. Here, the wall surface 16 a of the interlayer insulating film 16 has largely receded from the trench 30 due to the formation of the side space 50. Therefore, the interlayer insulating film 16 is not affected by the volume expansion of the trench insulating film 32 grown on the wall surface of the trench 30. Further, the interlayer insulating film 16 is affected by the volume expansion of the trench insulating film 32 grown on the bottom surface of the side space 50, and the direction of the force applied by the volume expansion is the width direction of the trench 30 (that is, in FIG. 9). The horizontal direction) is the main. Therefore, when the trench insulating film 32 is formed, the interlayer insulating film 16 does not rise and a convex portion is not formed on the upper surface thereof. Further, since the side space 50 is formed after the chamfering process, the bottom surface of the side space 50 is flat. Therefore, the trench insulating film 32 grown on the bottom surface of the side space 50 has a planar shape whose surface is substantially parallel to the top surface of the silicon layer 14 (see the flat portion 32a in FIG. 9).

(Polysilicon filling process)
When the trench insulating film forming step is completed, polysilicon is deposited on the upper surface side of the substrate 12 by the CVD method. At this time, the trench 30 and the side space 50 are also filled with polysilicon. As a result, a polysilicon layer 36 is formed as shown in FIG.

(Polysilicon removal process)
When the polysilicon layer 36 is formed, the polysilicon layer 36 is dry-etched from the upper surface side. As a result, the polysilicon above the side space 50 is removed as shown in FIG. More specifically, the upper polysilicon layer 36 in the side space 50 is also removed so that a gap is formed between the polysilicon layer 36 in the side space 50 and the first mask layer 18. That is, the polysilicon layer 36 is left in the lower portion in the side space 50 and the trench 30 below the side space 50. At this time, since the surface of the trench insulating film 32 in the side space 50 is flat, the thickness of the polysilicon layer 36 remaining in the side space 50 becomes substantially uniform.

(Cap insulation film formation process)
When the polysilicon removal step is completed, a cap insulating film 38 (silicon oxide film) is formed on the surface (upper surface) of the polysilicon layer 36 by thermal oxidation as shown in FIG. As described above, the polysilicon layer 36 in the side space 50 has a substantially uniform thickness. Therefore, the cap insulating film 38 grows on the surface of the polysilicon layer 36 with a substantially uniform thickness.

(First mask layer removing step)
When the cap insulating film forming step is completed, the first mask layer 18 is removed by etching. Thereby, the trench structure shown in FIG. 1 is completed.

  By forming the trench structure as described above and forming other necessary structures by a conventionally known method, a semiconductor device having the trench structure is manufactured.

  As described above, in the manufacturing method of the semiconductor device of this embodiment, the side space 50 is formed after the corner portion 34 is chamfered. For this reason, when the trench insulating film 32 is subsequently formed, the interlayer insulating film 16 is prevented from rising and forming a convex portion on the surface thereof. Further, since the side space 50 is formed, the polysilicon layer 36 can be formed in the side space 50 with a substantially uniform thickness. Therefore, the cap insulating film 38 can be formed on the upper surface of the polysilicon layer 36 with a uniform thickness. As described above, since a convex portion is formed in the interlayer insulating film 16 and a thin portion is not formed in the cap insulating film 38, a groove is formed on the upper surface of the substrate 12 after the trench structure is formed. Not. The upper surface of the substrate 12 can be made flatter than in the prior art. Therefore, when the metal wiring is formed on the upper surface of the substrate 12 after the trench structure is formed, the residue of the metal layer on the upper surface of the substrate 12 is suppressed.

In the above-described embodiment, the second mask layer 20 made of silicon oxide is formed. However, if the second mask layer 20 is not required for etching or the like when forming the trench 30, the second mask layer 20 may not be formed. Further, the second mask layer 20 may be formed of other materials.
In the embodiment described above, the first mask layer 18 is formed of silicon nitride. However, the first mask layer 18 may be formed of other materials as long as it has an etching selectivity with respect to the interlayer insulating film 16 (that is, the silicon oxide film).
In the above-described embodiment, the trench structure for element isolation has been described. However, the above manufacturing method may be applied to a trench structure for other uses.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

Sectional drawing of the trench structure formed with the manufacturing method of the Example. Sectional drawing of the board | substrate 12 used for the manufacturing method of an Example. Sectional drawing of the board | substrate 12 after the lamination process in the manufacturing method of an Example. Sectional drawing of the board | substrate 12 after opening 40 formation in the manufacturing method of an Example. Sectional drawing of the board | substrate 12 after trench 30 formation in the manufacturing method of an Example. Sectional drawing of the board | substrate 12 after the wall surface reverse process in the manufacturing method of an Example. Sectional drawing of the board | substrate 12 after the chamfering process in the manufacturing method of an Example. Sectional drawing of the board | substrate 12 after the side space formation process in the manufacturing method of an Example. Sectional drawing of the board | substrate 12 after the trench insulating film formation process in the manufacturing method of an Example. Sectional drawing of the board | substrate 12 after the polysilicon filling process in the manufacturing method of an Example. Sectional drawing of the board | substrate 12 after the polysilicon removal process in the manufacturing method of an Example. Sectional drawing of the board | substrate 12 after the cap insulating film formation process in the manufacturing method of an Example. Sectional drawing of the board | substrate 112 after laminated structure formation in the manufacturing method of a prior art. Sectional drawing of the board | substrate 112 after trench formation in the manufacturing method of a prior art. Sectional drawing of the board | substrate 112 after the silicon oxide etching in the manufacturing method of a prior art. Sectional drawing of the board | substrate 112 after the chamfering of the corner | angular part in the manufacturing method of a prior art. Sectional drawing of the board | substrate 112 after trench insulating film formation in the manufacturing method of a prior art. Sectional drawing of the board | substrate 112 after the polysilicon layer formation in the manufacturing method of a prior art. Sectional drawing of the board | substrate 112 after cap insulating film formation in the manufacturing method of a prior art. Sectional drawing of the trench structure formed by the manufacturing method of a prior art.

Explanation of symbols

12: substrate 14: silicon layer 16: interlayer insulating film 16a: wall surface 18: first mask layer 20: second mask layer 30: trench 32: trench insulating film 32a: flat portion 34: corner 36: polysilicon layer 38: Cap insulating film 40: opening 50: lateral space

Claims (1)

A method of manufacturing a semiconductor device having a structure in which polysilicon is filled in a trench, and an upper portion of the polysilicon in the trench is covered with silicon oxide,
A substrate having a silicon layer, an interlayer insulating film made of silicon oxide and laminated on the silicon layer, and a mask layer made of a material laminated on the interlayer insulating film and having an etching selectivity with respect to silicon oxide Against
A trench formation step of forming a trench reaching the inside of the silicon layer from the surface of the mask layer on the substrate by etching the mask layer, the interlayer insulating film, and the silicon layer, respectively;
After the trench formation process, by etching the interlayer insulating film from the wall surface exposed in the trench, a wall surface receding process for receding the wall surface;
A chamfering step of chamfering a corner portion of the boundary between the upper surface of the silicon layer and the trench wall surface by etching the surface of the silicon layer exposed in the trench after the wall receding step;
After the chamfering step, by etching the interlayer insulating film from the wall surface exposed in the trench, a side space forming step for forming a side space extending laterally from the wall surface of the trench;
After the side space forming step, a trench insulating film made of silicon oxide is formed on the surface of the exposed silicon layer by oxidizing the silicon layer exposed in the trench and in the side space. Forming process;
After the trench insulating film formation step, a polysilicon filling step for filling the trench and the side space with polysilicon,
After the polysilicon filling step, by partially removing the filled polysilicon by etching, a polysilicon removing step for forming a gap between the remaining polysilicon and the mask layer;
Manufacturing a semiconductor device, wherein a cap insulating film forming step of forming a cap insulating film made of silicon oxide on the surface of the polysilicon by oxidizing the surface of the remaining polysilicon after the polysilicon removing step is performed. Method.

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