JPH11126730A - Manufacture of multiple electronic component - Google Patents

Manufacture of multiple electronic component

Info

Publication number
JPH11126730A
JPH11126730A JP9292173A JP29217397A JPH11126730A JP H11126730 A JPH11126730 A JP H11126730A JP 9292173 A JP9292173 A JP 9292173A JP 29217397 A JP29217397 A JP 29217397A JP H11126730 A JPH11126730 A JP H11126730A
Authority
JP
Japan
Prior art keywords
electrode
electronic component
cut groove
multiple electronic
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9292173A
Other languages
Japanese (ja)
Inventor
Yukihito Yamashita
由起人 山下
Takeshi Kimura
猛 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9292173A priority Critical patent/JPH11126730A/en
Publication of JPH11126730A publication Critical patent/JPH11126730A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Abstract

PROBLEM TO BE SOLVED: To secure a favorable electrical connection between electrodes constituting function elements and external electrodes as well as prevent short circuits in solder bridges between assembled external electrodes when a plurality of function elements are installed in one element assembly. SOLUTION: A trench 7, which is narrower than an electrode 3 constituting function element installed in a sintered body and deep enough to reach the electrode 3, is machined on both sides of the sintered body of a multiple electronic component. Part of the edges of the electrode 3 must be exposed inside the trench 7. Then, an external electrode 9 is formed only inside the trench 7 so that the electrode is on the same plane as the upper and lower surface of the sintered body.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は電子部品を単一素体
内に機能素子を複数個形成した多連型電子部品の製造方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multiple-type electronic component in which a plurality of functional elements are formed in a single element body.

【0002】[0002]

【従来の技術】従来の多連型電子部品の製造方法につい
て、多連型積層セラミックコンデンサ(以降、コンデン
サアレイと称する)を例に図を用いて説明する。
2. Description of the Related Art A conventional method for manufacturing a multiple-type electronic component will be described with reference to the drawings, taking a multiple-type multilayer ceramic capacitor (hereinafter referred to as a capacitor array) as an example.

【0003】図7は従来のコンデンサアレイのグリーン
積層体、図8はその展開図、図9は焼結体、図10は完
成品を示す図である。
FIG. 7 is a view showing a conventional green laminate of a capacitor array, FIG. 8 is a development view thereof, FIG. 9 is a view showing a sintered body, and FIG. 10 is a view showing a completed product.

【0004】公知の積層コンデンサの製造方法を用い、
図8に示すように誘電体層22に内部電極23を印刷し
たものを複数枚積層し、上、下に無効層24を設けた積
層体を、図7に示すグリーン積層体21の形状に切断
後、所定温度で焼成を行う。次に得られた焼結体25の
バレル研磨を行い、図9に示すように焼結体25の内部
に形成された内部電極23群を焼結体25の側面に露出
させ、次いで露出した内部電極23群を覆うように外部
電極26を形成し、図10に示すようなコンデンサアレ
イを製造する方法が一般に知られている。
Using a known method for manufacturing a multilayer capacitor,
As shown in FIG. 8, a plurality of layers obtained by printing the internal electrodes 23 on the dielectric layer 22 are laminated, and the laminated body provided with the invalid layer 24 above and below is cut into the shape of the green laminated body 21 shown in FIG. Thereafter, firing is performed at a predetermined temperature. Next, the obtained sintered body 25 is subjected to barrel polishing to expose the group of internal electrodes 23 formed inside the sintered body 25 to the side surface of the sintered body 25 as shown in FIG. A method of manufacturing a capacitor array as shown in FIG. 10 by forming external electrodes 26 so as to cover the group of electrodes 23 is generally known.

【0005】[0005]

【発明が解決しようとする課題】しかしながら従来のコ
ンデンサアレイは、焼結体25内部に形成した内部電極
23端部を、その側面に露出させるため焼結体25のバ
レル研磨を行うが、内部電極23端部を完全に露出させ
るためには、長時間のバレル研磨を必要とし、研磨が十
分でない場合、外部電極26ペーストを焼結体25の内
部電極23の露出面に塗布、焼付けしたとき、内部電極
23端部と外部電極26との間で接続が不十分となり所
謂容量抜け不良が発生したり、またバレル研磨を行うこ
とにより焼結体25の側面に生じた凹凸面に外部電極2
6ペーストを塗布した際に、側面の凹部に気泡が残留
し、その後の焼付で気泡部分が空洞となり、内部電極2
3と外部電極26間の接続を妨げ所謂容量抜け不良が発
生する。更に完成品を基板へ実装した際に、隣合う外部
電極26間で半田ブリッジを形成し、外部電極26間で
短絡するという問題点があった。
However, in the conventional capacitor array, barrel polishing of the sintered body 25 is performed to expose the end of the internal electrode 23 formed inside the sintered body 25 to the side surface. In order to completely expose the 23 end portions, barrel polishing for a long time is required. If the polishing is not sufficient, when the external electrode 26 paste is applied to the exposed surface of the internal electrode 23 of the sintered body 25 and baked, The connection between the end of the internal electrode 23 and the external electrode 26 is insufficient, so-called poor capacity loss occurs, and the external electrode 2 is formed on the uneven surface formed on the side surface of the sintered body 25 by barrel polishing.
When the paste 6 is applied, air bubbles remain in the concave portions on the side surfaces, and the air bubbles become hollow by the subsequent baking.
3 and the external electrode 26 are hindered, and a so-called capacity loss failure occurs. Further, when the finished product is mounted on a substrate, there is a problem that a solder bridge is formed between adjacent external electrodes 26 and a short circuit occurs between the external electrodes 26.

【0006】本発明は、前記従来の問題点を解決し信頼
性の高い多連型電子部品の製造方法を提供することを目
的とするものである。
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to provide a highly reliable method for manufacturing a multiple electronic component.

【0007】[0007]

【課題を解決するための手段】前記目的を達成するため
に本発明は、コンデンサアレイグリーン積層体内部に構
成された各積層コンデンサ内部電極の端部を、焼結体の
両側面に露出させないように設け、焼成後その焼結体側
面から内部電極の端部に向けて、全ての内部電極端部と
交差し、しかも内部電極の幅より狭い切込溝の加工を行
い、焼結体のバレル研磨だけでは十分に露出させること
の出来ない内部電極の端部を、切込溝内面のみに確実に
露出させた後、切込溝内面のみに外部電極ペーストを塗
布、焼付けし露出した内部電極と外部電極間の接続を行
う。この方法により内部電極と外部電極間の接続を完全
なものとすると共に、隣合う外部電極間の絶縁間隔も十
分広く確保し、基板実装の際、隣合う外部電極間の半田
ブリッジによる短絡不良の発生も防止することができ
る。
SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is to prevent the end portions of the internal electrodes of each multilayer capacitor formed inside the capacitor array green laminate from being exposed on both side surfaces of the sintered body. After firing, a cut groove narrower than the width of the internal electrode is made to intersect all internal electrode ends from the side of the sintered body to the end of the internal electrode. After reliably exposing the end of the internal electrode, which cannot be sufficiently exposed only by polishing, to only the inner surface of the cut groove, apply the external electrode paste only to the inner surface of the cut groove, and bake it. Make connections between external electrodes. This method completes the connection between the internal electrode and the external electrode, secures a sufficiently large insulation interval between adjacent external electrodes, and eliminates short-circuit failure due to solder bridges between adjacent external electrodes when mounting on a board. Occurrence can also be prevented.

【0008】[0008]

【発明の実施の形態】本発明の請求項1に記載の発明
は、単一素体内部に並列方向に所定間隔を置いて形成さ
れた、電極を有する複数個の機能素子からなる多連型電
子部品において、前記機能素子個々を構成する電極の端
部が前記素体の両側面に接しないように設け、前記素体
の両側面を、その内部に形成された機能素子の電極の端
部と交差するように切込溝を加工し、この切込溝内面に
前記電極と接続するように外部電極を形成することを特
徴とする多連型電子部品の製造方法であり、素体の側面
から機能素子を構成する電極と接するよう切込溝を加工
し、切込溝内面に各機能素子単位毎に独立した外部電極
ペーストを塗布・焼付けし、外部電極を形成することに
より、各機能素子の電極と外部電極間での接続を確保す
ることができるという作用を有するものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a multi-unit type comprising a plurality of functional elements having electrodes formed at predetermined intervals in a parallel direction inside a single element body. In the electronic component, an end of an electrode constituting each of the functional elements is provided so as not to be in contact with both side surfaces of the element body, and both side surfaces of the element body are connected to an end of an electrode of the functional element formed therein. And forming an external electrode on the inner surface of the groove so as to connect to the electrode. By forming a cut groove so as to be in contact with the electrode constituting the functional element, applying and baking an independent external electrode paste for each functional element unit on the inner surface of the cut groove to form the external electrode, Connection between external electrodes and external electrodes can be secured. It is expected to have an effect.

【0009】請求項2に記載の発明は、各機能素子を構
成する電極の端部にこの電極引出部を素体側面に接する
ように設け、前記電極引出部が接した側面部分のみに切
込溝を加工することを特徴とする請求項1に記載の多連
型電子部品の製造方法であり、機能素子の電極引出部
を、素体側面と接するように形成することにより、切込
溝の位置決めが容易になると共に、切込溝を確実に電極
引出部と交差させることができ、その後の外部電極形成
で内部電極と外部電極の接続がより確実なものとするこ
とができるという作用を有する。
According to a second aspect of the present invention, an electrode lead portion is provided at an end of an electrode constituting each functional element so as to be in contact with a side surface of the element body, and a cut is made only in a side surface portion where the electrode lead portion is in contact. The method for manufacturing a multiple-part electronic component according to claim 1, wherein the groove is machined, wherein the electrode lead-out portion of the functional element is formed so as to be in contact with a side surface of the element body, thereby forming the cut groove. In addition to easy positioning, the notch groove can be reliably crossed with the electrode lead-out portion, and the subsequent formation of the external electrode has the effect that the connection between the internal electrode and the external electrode can be made more reliable. .

【0010】請求項3に記載の発明は、切込溝の幅を、
機能素子を構成する電極の幅よりも狭く加工することを
特徴とした請求項1または請求項2に記載の多連型電子
部品の製造方法であり、これにより切込溝内のみに形成
される外部電極の幅が機能素子を構成する電極幅よりも
狭くなり、隣合う外部電極間の距離が十分広く確保で
き、多連型電子部品を基板実装した際に隣合う外部電極
同士の半田ブリッジによる短絡を防止することが出来る
という作用を有する。
[0010] According to a third aspect of the present invention, the width of the cut groove is set as follows.
3. The method of manufacturing a multiple electronic component according to claim 1, wherein the width of the electrode constituting the functional element is smaller than that of the electrode. The width of the external electrodes is narrower than the electrode width of the functional element, and the distance between adjacent external electrodes can be secured sufficiently large. It has the effect that a short circuit can be prevented.

【0011】請求項4に記載の発明は、切込溝の幅を、
隣合う切込溝との間隔より狭く加工することを特徴とし
た請求項1から請求項3の何れか一つに記載の多連型電
子部品の製造方法であり、これにより切込溝内のみに外
部電極を形成した場合、隣合う外部電極間の距離を十分
広く確保でき多連型電子部品を基板実装した際、隣合う
外部電極間の半田ブリッジによる短絡を防止することが
出来るという作用を有する。
[0011] According to a fourth aspect of the present invention, the width of the cut groove is set as follows.
4. The method for manufacturing a multiple electronic component according to claim 1, wherein the processing is performed to be narrower than an interval between adjacent cut grooves. In the case where external electrodes are formed, the distance between adjacent external electrodes can be sufficiently widened, and when multiple electronic components are mounted on a board, short-circuiting due to solder bridges between adjacent external electrodes can be prevented. Have.

【0012】請求項5に記載の発明は、切込溝底部のコ
ーナ部分を、曲面状に加工することを特徴とした請求項
1から請求項4のいずれか一つに記載の多連型電子部品
の製造方法であり、これにより切込溝底部のコーナ部分
に確実に外部電極用ペーストを塗布することができると
共に、コーナ部分に外部電極用ペーストを塗布した際に
生じやすい気泡を除去することができるという作用を有
する。
The invention according to claim 5 is characterized in that the corner portion at the bottom of the cut groove is machined into a curved surface. This is a method for manufacturing a component, whereby the external electrode paste can be reliably applied to the corner portion at the bottom of the cut groove, and air bubbles that are likely to be generated when the external electrode paste is applied to the corner portion are removed. It has the effect of being able to.

【0013】請求項6に記載の発明は、切込溝の底面
を、内方に向け曲面状に加工することを特徴とした請求
項1から請求項5の何れか一つに記載の多連型電子部品
の製造方法であり、これにより切込溝の底面に確実に外
部電極用ペーストを塗布することができるという作用を
有する。
The invention according to claim 6 is characterized in that the bottom surface of the cut groove is machined inwardly into a curved surface. This is a method for manufacturing a molded electronic component, which has an effect that the external electrode paste can be surely applied to the bottom surface of the cut groove.

【0014】請求項7に記載の発明は、外部電極を素体
の上、下平面と同一平面となるように形成することを特
徴とした請求項1から請求項6の何れか一つに記載の多
連型電子部品の製造方法であり、これにより切込溝を設
けたために低下する素体の抗折強度を、切込溝内面に外
部電極を形成することで補強できると共に、外部電極を
素体上、下平面と同一平面となるように設けるため、実
装基板の半田付けランドの設計が容易となるという作用
を有する。
The invention according to claim 7 is characterized in that the external electrodes are formed so as to be flush with the upper and lower planes of the element body. This is a method of manufacturing a multiple-type electronic component, whereby the bending strength of the element body, which is reduced due to the provision of the cut groove, can be reinforced by forming an external electrode on the inner surface of the cut groove, and the external electrode is formed. Since it is provided so as to be flush with the lower and upper surfaces of the element body, it has an effect that the design of the soldering lands of the mounting board becomes easy.

【0015】請求項8に記載の発明は、機能素子が、
上、下方向に誘電体層を介し所定間隔をおいて複数層形
成された内部電極を有する積層コンデンサ素子であり、
この積層コンデンサ素子の内部電極を一層毎交互に対向
する異なる側面の切込溝内面に形成した外部電極と接続
させたことを特徴とした請求項1から請求項7の何れか
一つに記載の多連型電子部品の製造方法であり、これに
より素体内に形成された、個々の積層セラミックコンデ
ンサの内部電極と切込溝内面に形成した外部電極を確実
に接続できるという作用を有する。
According to an eighth aspect of the present invention, the functional element comprises:
A multilayer capacitor element having internal electrodes formed in a plurality of layers at predetermined intervals via a dielectric layer in an upward and downward direction,
8. The multilayer capacitor element according to claim 1, wherein the internal electrodes of the multilayer capacitor element are connected to external electrodes formed on the inner surfaces of the cut grooves on different side surfaces facing each other alternately. This is a method of manufacturing a multiple-type electronic component, and has an effect that an internal electrode of each multilayer ceramic capacitor formed in a body and an external electrode formed on an inner surface of a cut groove can be reliably connected.

【0016】請求項9に記載の発明は、機能素子が、素
体の上面に抵抗膜を形成した抵抗体素子であり、この抵
抗体素子の電極部を素体側面の切込溝に形成した外部電
極と接続させたことを特徴とした請求項1から請求項7
の何れか一つに記載の多連型電子部品の製造方法であ
り、これにより素体内に形成された、個々の抵抗体素子
の電極と切込溝内面に形成した外部電極を確実に接続で
きるという作用を有する。
According to a ninth aspect of the present invention, the functional element is a resistive element having a resistive film formed on an upper surface of the element body, and the electrode portion of the resistive element is formed in a cut groove on a side surface of the element body. 8. The device according to claim 1, wherein the device is connected to an external electrode.
The method of manufacturing a multiple-type electronic component according to any one of the above, whereby the electrodes of the individual resistor elements formed in the element body and the external electrodes formed on the inner surfaces of the cut grooves can be reliably connected. It has the action of:

【0017】以下、本発明の一実施形態の多連型電子部
品の製造方法について、コンデンサアレイを用い説明す
る。
Hereinafter, a method for manufacturing a multiple electronic component according to an embodiment of the present invention will be described using a capacitor array.

【0018】(実施の形態)図1から図6に本発明のコ
ンデンサアレイを示した。図1はグリーン積層体の斜視
図、図2はグリーン積層体の分解斜視図、図3は焼結体
の斜視図、図4は切込溝を加工した焼結体の斜視図、図
5は完成品の斜視図、図6は完成品の断面図である。図
において、1はグリーン積層体、2は誘電体層、3は内
部電極、4は内部電極3の引出部、5は無効層、6は焼
結体、7は切込溝、8は切込溝底部のコーナ部、9は外
部電極である。
(Embodiment) FIGS. 1 to 6 show a capacitor array according to the present invention. 1 is a perspective view of a green laminate, FIG. 2 is an exploded perspective view of the green laminate, FIG. 3 is a perspective view of a sintered body, FIG. 4 is a perspective view of a sintered body having cut grooves, and FIG. FIG. 6 is a perspective view of the finished product, and FIG. 6 is a sectional view of the finished product. In the figure, 1 is a green laminate, 2 is a dielectric layer, 3 is an internal electrode, 4 is a lead portion of the internal electrode 3, 5 is an ineffective layer, 6 is a sintered body, 7 is a cut groove, and 8 is a cut. A corner portion 9 at the bottom of the groove is an external electrode.

【0019】公知の積層コンデンサ製造方法を用い、誘
電体層2用のグリーンシートを作製する。
A green sheet for the dielectric layer 2 is manufactured by using a known multilayer capacitor manufacturing method.

【0020】次に作製したグリーンシート面に、図2に
示す引出部4を設けた内部電極3の印刷を行った後、前
記グリーンシートを複数枚積層し、更にその上、下部に
無効層5を重ね積層体ブロックを作製する。
Next, after printing the internal electrode 3 provided with the lead portion 4 shown in FIG. 2 on the surface of the prepared green sheet, a plurality of the green sheets are laminated. To form a laminate block.

【0021】次いで、積層体ブロックを図1に示す、グ
リーン積層体1の形状に切断後、所定温度で焼成し、図
3に示す焼結体6を作製する。
Next, the laminate block is cut into the shape of the green laminate 1 shown in FIG. 1 and fired at a predetermined temperature to produce a sintered body 6 shown in FIG.

【0022】その後、焼結体6の両側面に露出した、引
出部4の位置に図4に示すように、コンデンサアレイを
構成する各積層コンデンサ単位毎に、切込溝7の加工を
行う。切込溝7の位置は引出部4を焼結体6側面に露出
させているため容易に決めることができ、切込溝7の幅
は図6に示すように、内部電極3の幅より狭く、また隣
合う積層コンデンサの間隔、すなわち内部電極3の非形
成部の幅より狭く、深さは全ての内部電極3端部と交差
し、しかも対向する異なる側面に一層毎交互に露出させ
た反対側の内部電極3端部に接しないように、更に切込
溝7の底面、及びコーナ部8を曲面状に加工する。これ
により全ての内部電極3は切込溝7の内面にのみ、その
一部を確実に露出させることができると共に、次工程で
外部電極9ペーストを塗布する際、切込溝7の底面、及
びコーナ部8を曲面を持たせて加工したことにより、電
極ペーストを切込溝7の内面に一様に塗布することがで
き、切込溝7底面の立上がり部分が角張っている場合、
その隅に取り残されやすい気泡の発生を防止し、内部電
極3と外部電極9間で良好な接続状態を確保することが
できる。
Thereafter, as shown in FIG. 4, the cut grooves 7 are formed at the positions of the lead-out portions 4 exposed on both side surfaces of the sintered body 6 for each multilayer capacitor unit constituting the capacitor array. The position of the cut groove 7 can be easily determined because the extraction portion 4 is exposed on the side surface of the sintered body 6, and the width of the cut groove 7 is smaller than the width of the internal electrode 3 as shown in FIG. The distance between adjacent multilayer capacitors, that is, the width is smaller than the width of the portion where the internal electrode 3 is not formed, and the depth intersects all the end portions of the internal electrode 3 and is alternately exposed on different side surfaces facing each other. The bottom surface of the cut groove 7 and the corner portion 8 are further processed into a curved surface so as not to contact the end of the internal electrode 3 on the side. Thereby, all the internal electrodes 3 can be reliably exposed only on the inner surface of the cut groove 7 and a part thereof, and when applying the external electrode 9 paste in the next step, the bottom surface of the cut groove 7 and By processing the corner portion 8 to have a curved surface, the electrode paste can be uniformly applied to the inner surface of the cut groove 7, and when the rising portion of the bottom surface of the cut groove 7 is square,
The generation of air bubbles that are easily left behind at the corners can be prevented, and a good connection between the internal electrode 3 and the external electrode 9 can be ensured.

【0023】その後更に、加工した切込溝7内面に、図
5,図6に示すように外部電極9を設けるが、外部電極
9を焼結体6の上、下平面と同一平面となるように形成
する。外部電極9面が平らであるためコンデンサアレイ
を実装する、基板の半田付けランド寸法の設計が容易と
なり、更に形成した外部電極9の幅を内部電極3の幅よ
り狭く、また隣合う外部電極9との間隔より狭く、しか
も切込溝7の内部にのみ設けるため、隣合う外部電極9
との絶縁距離を十分広く確保出来ると共に、コンデンサ
アレイを基板に実装した際、隣合う外部電極9間の半田
ブリッジによる短絡を防止することが出来るという効果
も有している。
Thereafter, an external electrode 9 is further provided on the inner surface of the cut groove 7 as shown in FIGS. 5 and 6 so that the external electrode 9 is flush with the upper and lower surfaces of the sintered body 6. Formed. Since the surface of the external electrode 9 is flat, it is easy to design the size of the soldering land on the substrate on which the capacitor array is mounted. Further, the width of the formed external electrode 9 is smaller than the width of the internal electrode 3 and the width of the adjacent external electrode 9 And is provided only inside the cut groove 7, so that the adjacent external electrodes 9
In addition to this, there is an effect that an insulation distance between the external electrodes 9 can be sufficiently widened and a short circuit due to a solder bridge between the adjacent external electrodes 9 can be prevented when the capacitor array is mounted on the substrate.

【0024】尚、本実施形態では、内部電極3端部に引
出部4を設けたが、焼結体6の内部に形成した内部電極
3の位置が外部から判定できる表示を行うことで引出部
4を除くことは可能であり、またコンデンサアレイを用
いて説明したが、多連型抵抗体などの多連型電子部品に
おいても同様な方法を用いることができる。
In the present embodiment, the extraction portion 4 is provided at the end of the internal electrode 3. However, the position of the internal electrode 3 formed inside the sintered body 6 is displayed by displaying an externally-determinable display. Although it is possible to omit step 4 and the description has been made using the capacitor array, a similar method can be used for a multiple-type electronic component such as a multiple-type resistor.

【0025】[0025]

【発明の効果】以上、本発明によれば、機能素子を内部
に複数個形成した多連型電子部品焼結体の両側面に、各
機能素子を構成する電極に達する深さで、しかも電極の
幅よりも狭く、また隣合う機能素子の間隔より狭く切込
溝を加工し、更に切込溝の底面、及びコーナ部を曲面状
となるように形成する。次にその切込溝の内面に機能素
子の電極と接続するように、外部電極ペーストを塗布、
形成する際、切込溝コーナ部に取り残されやすい気泡が
除かれ、機能素子の電極と外部電極との電気的接続を確
保することができる。しかも外部電極を焼結体上、下面
と同一平面となるように形成するため、隣合う外部電極
間で十分な広さの絶縁距離を確保できると共に、多連型
電子部品を基板実装した際、隣合う外部電極間の半田ブ
リッジによる短絡を防止することが出来る。
As described above, according to the present invention, both sides of a multiple-piece electronic component sintered body having a plurality of functional elements formed therein are provided at a depth reaching the electrodes constituting each functional element, and The cut groove is machined so as to be narrower than the width of the groove and smaller than the interval between adjacent functional elements, and the bottom surface and the corner portion of the cut groove are formed so as to be curved. Next, an external electrode paste is applied to the inner surface of the cut groove so as to connect to the electrode of the functional element,
At the time of formation, air bubbles that are easily left behind in the cut groove corners are removed, and electrical connection between the electrode of the functional element and the external electrode can be ensured. In addition, since the external electrodes are formed so as to be flush with the upper and lower surfaces of the sintered body, a sufficiently large insulation distance can be secured between adjacent external electrodes, and when mounting multiple electronic components on a substrate, A short circuit due to a solder bridge between adjacent external electrodes can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の多連型積層セラミックコ
ンデンサのグリーン積層体斜視図
FIG. 1 is a perspective view of a green laminate of a multiple-layer ceramic capacitor of one embodiment of the present invention.

【図2】同、グリーン積層体の分解斜視図FIG. 2 is an exploded perspective view of the same green laminate.

【図3】同、焼結体斜視図FIG. 3 is a perspective view of the same sintered body.

【図4】同、切込溝を加工した焼結体斜視図FIG. 4 is a perspective view of a sintered body in which a cut groove is processed.

【図5】同、完成品斜視図FIG. 5 is a perspective view of the same finished product.

【図6】同、完成品の平断面図FIG. 6 is a plan sectional view of the same finished product.

【図7】従来品の多連型積層セラミックコンデンサのグ
リーン積層体斜視図
FIG. 7 is a perspective view of a green laminate of a conventional multi-layered multilayer ceramic capacitor.

【図8】同、グリーン積層体の分解斜視図FIG. 8 is an exploded perspective view of the green laminate.

【図9】同、焼結体斜視図FIG. 9 is a perspective view of the same sintered body.

【図10】同、完成品斜視図FIG. 10 is a perspective view of the same finished product.

【符号の説明】[Explanation of symbols]

1 グリーン積層体 2 誘電体層 3 内部電極 4 引出部 5 無効層 6 焼結体 7 切込溝 8 コーナ部 9 外部電極 21 グリーン積層体 22 誘電体層 23 内部電極 24 無効層 25 焼結体 26 外部電極 DESCRIPTION OF SYMBOLS 1 Green laminated body 2 Dielectric layer 3 Internal electrode 4 Lead-out part 5 Invalid layer 6 Sintered body 7 Cut groove 8 Corner part 9 External electrode 21 Green laminated body 22 Dielectric layer 23 Internal electrode 24 Invalid layer 25 Sintered body 26 External electrode

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 単一素体内部に並列方向に所定間隔を置
いて形成された、電極を有する複数個の機能素子からな
る多連型電子部品において、前記機能素子個々を構成す
る電極の端部を前記素体の両側面に接しないように設
け、次に前記素体の両側面をその内部に形成された機能
素子の電極の端部と交差するように切込溝を加工し、次
いでこの切込溝内面に前記電極と接続するように外部電
極を形成することを特徴とする多連型電子部品の製造方
法。
1. A multiple electronic component comprising a plurality of functional elements each having an electrode and formed at predetermined intervals in a parallel direction inside a single element body, wherein an end of an electrode constituting each of the functional elements is provided. Parts are provided so as not to be in contact with both side surfaces of the element body, and then cut grooves are formed so that both side surfaces of the element body intersect with the ends of the electrodes of the functional elements formed therein, An external electrode is formed on the inner surface of the cut groove so as to be connected to the electrode.
【請求項2】 各機能素子を構成する電極の端部にこの
電極引出部を素体側面に接するように設け、前記電極引
出部が接した側面部分のみに切込溝を加工することを特
徴とする請求項1に記載の多連型電子部品の製造方法。
2. An electrode lead portion is provided at an end portion of an electrode constituting each functional element so as to be in contact with a side surface of a body, and a cut groove is formed only in a side surface portion contacted by the electrode lead portion. 2. The method of manufacturing a multiple electronic component according to claim 1, wherein:
【請求項3】 切込溝の幅を、機能素子を構成する電極
の幅よりも狭く加工することを特徴とした請求項1また
は請求項2に記載の多連型電子部品の製造方法。
3. The method for manufacturing a multiple electronic component according to claim 1, wherein the width of the cut groove is processed to be smaller than the width of the electrode constituting the functional element.
【請求項4】 切込溝の幅を、隣合う切込溝との間隔よ
り狭く加工することを特徴とした請求項1から請求項3
の何れか一つに記載の多連型電子部品の製造方法。
4. The process according to claim 1, wherein the width of the cut groove is smaller than the interval between adjacent cut grooves.
The method for manufacturing a multiple-type electronic component according to any one of the above.
【請求項5】 切込溝底部のコーナ部分を、曲面状に加
工することを特徴とした請求項1から請求項4のいずれ
か一つに記載の多連型電子部品の製造方法。
5. The method for manufacturing a multiple electronic component according to claim 1, wherein a corner portion at a bottom of the cut groove is processed into a curved surface.
【請求項6】 切込溝の底面を、内方に向け曲面状に加
工することを特徴とした請求項1から請求項5の何れか
一つに記載の多連型電子部品の製造方法。
6. The method for manufacturing a multiple electronic component according to claim 1, wherein the bottom surface of the cut groove is formed into a curved surface inward.
【請求項7】 外部電極を素体の上、下平面と同一平面
となるように形成することを特徴とした請求項1から請
求項6の何れか一つに記載の多連型電子部品の製造方
法。
7. The multiple electronic component according to claim 1, wherein the external electrodes are formed so as to be flush with the upper and lower surfaces of the element body. Production method.
【請求項8】 機能素子が、上、下方向に誘電体層を介
し所定間隔をおいて複数層形成された内部電極を有する
積層コンデンサ素子であり、この積層コンデンサ素子の
内部電極を一層毎交互に対向する異なる側面の切込溝内
面に形成した外部電極と接続させたことを特徴とした請
求項1から請求項7の何れか一つに記載の多連型電子部
品の製造方法。
8. A multi-layer capacitor element having a plurality of internal electrodes formed at predetermined intervals with a dielectric layer interposed therebetween in an upward and downward direction, wherein the internal electrodes of the multi-layer capacitor element are alternately layered. The method for manufacturing a multiple electronic component according to any one of claims 1 to 7, wherein the multiple electronic components are connected to an external electrode formed on an inner surface of the cut groove on a different side surface facing the side surface.
【請求項9】 機能素子が、素体の上面に抵抗膜を形成
した抵抗体素子であり、この抵抗体素子の電極部を素体
側面の切込溝に形成した外部電極と接続させたことを特
徴とした請求項1から請求項7の何れか一つに記載の多
連型電子部品の製造方法。
9. The functional element is a resistive element having a resistive film formed on an upper surface of the element body, and an electrode portion of the resistive element is connected to an external electrode formed in a cut groove on a side surface of the element body. The method for manufacturing a multiple electronic component according to any one of claims 1 to 7, wherein:
JP9292173A 1997-10-24 1997-10-24 Manufacture of multiple electronic component Pending JPH11126730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9292173A JPH11126730A (en) 1997-10-24 1997-10-24 Manufacture of multiple electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9292173A JPH11126730A (en) 1997-10-24 1997-10-24 Manufacture of multiple electronic component

Publications (1)

Publication Number Publication Date
JPH11126730A true JPH11126730A (en) 1999-05-11

Family

ID=17778513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9292173A Pending JPH11126730A (en) 1997-10-24 1997-10-24 Manufacture of multiple electronic component

Country Status (1)

Country Link
JP (1) JPH11126730A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018014482A (en) * 2016-07-21 2018-01-25 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multi-layer capacitor and mounting board thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164516A (en) * 1980-05-23 1981-12-17 Tdk Electronics Co Ltd Composite part
JPH03280412A (en) * 1990-03-29 1991-12-11 Mitsubishi Materials Corp Capacitor network structure and manufacture thereof
JPH0617226U (en) * 1992-08-04 1994-03-04 株式会社村田製作所 CR composite array

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164516A (en) * 1980-05-23 1981-12-17 Tdk Electronics Co Ltd Composite part
JPH03280412A (en) * 1990-03-29 1991-12-11 Mitsubishi Materials Corp Capacitor network structure and manufacture thereof
JPH0617226U (en) * 1992-08-04 1994-03-04 株式会社村田製作所 CR composite array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018014482A (en) * 2016-07-21 2018-01-25 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multi-layer capacitor and mounting board thereof

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