JPH11121634A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control shifting of a threshold of a MOS semiconductor device in a radiation environment, by forming a two-layered gate insulating film consisting of a gate oxide film, i.e., a silicon dioxide film and a gate silicon nitride film. SOLUTION: In a complementary MOS semiconductor device, each of gate insulating films 62 of an NMOS semiconductor device 11 and a PMOS semiconductor device 12 is formed of a two-layered film consisting of a gate oxide film 2, which is made of a silicon dioxide film, and a gate silicon nitride film 61. As a result, from the problem of matching the interface between the films 2 and 61, an interface level having charges at the interface occurs. In order to match the interface level, the concentration of a well is controlled so as to control the threshold. Therefore, when the semiconductor device is used in a radiation environment, positive charges generated by a radiation of gamma rays are reduced by the interface level. Hence, changes in the threshold can be controlled and consequently a stable characteristic can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an N-channel MOS type semiconductor device and a P-type semiconductor device on a common semiconductor substrate or SOI substrate.
Channel type MOS semiconductor device, or even MONO
The present invention relates to a structure of a semiconductor device including an S-type semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art MOS (Metal-Oxide-Semiconductor)
As a type semiconductor device, a semiconductor substrate made of silicon and a semiconductor substrate having a semiconductor layer on an insulating film formed on a supporting substrate, so-called SOI (Silicon on Ins) are used.
ulator) using a substrate.

First, a structure example of a conventional MOS type semiconductor device using a semiconductor substrate made of silicon is shown in FIG.
This will be described with reference to the schematic sectional view of FIG. In the MOS semiconductor device shown in FIG. 69, an N-channel MOS semiconductor device 11 and a P-channel MOS semiconductor device 12 are formed using a semiconductor substrate 1 made of silicon, and constitute a complementary MOS semiconductor device. .

In an N-channel MOS semiconductor device 11, a gate oxide film 2 and a gate electrode 3 are provided on a surface of a semiconductor substrate 1 on a P well 4 provided by a P-type impurity layer in the semiconductor substrate 1, and a gate electrode 3 is formed. On the surface of the semiconductor substrate 1 aligned with the semiconductor substrate 3, a source 6 formed of an N-type high-concentration impurity layer is formed.
And a drain 7.

In a P-channel type MOS semiconductor device 12, a gate oxide film 2 and a gate electrode 3 are provided on a surface of a semiconductor substrate 1 on an N well 5 provided by an N type impurity layer in the semiconductor substrate 1, and a gate electrode 3 is provided. The source 1 formed by a P-type high concentration impurity layer
6 and a drain 17 are provided.

The N channel type MOS semiconductor device 11 and the P channel type MOS semiconductor device 12
Are separated by a field oxide film 13 formed on the surface of the element.

Then, an interlayer insulating film 8 is formed on the entire surface of the semiconductor substrate 1, and the gate electrode 3, the source 6 and the source 6 of the N-channel type MOS semiconductor device 11 are respectively formed through contact holes 9 formed in the interlayer insulating film 8. , And the drain 7, the wiring 10 having one end connected to the gate electrode 3, the source 17, and the drain 17 of the P-channel type MOS semiconductor device 12 (the wiring 10 connected to the gate electrodes 3, 3 has a cross section shown in FIG. 69). Are provided at different cross-sectional positions), thereby being connected to another MOS type semiconductor device provided on the semiconductor substrate 1.

Next, a conventional MO using an SOI substrate is used.
An example of the structure of the S-type semiconductor device will be described with reference to a schematic sectional view of FIG. The MOS type semiconductor device shown in FIG. 70 uses an SOI substrate 23 including a support substrate 20, an insulating film 21, and a plurality of island-shaped semiconductor layers 22a and 22b. Then, a gate oxide film 2 and a gate electrode 3 are provided on each of the semiconductor layers 22a and 22b of the SOI substrate to constitute a semiconductor device including an N-channel MOS semiconductor device 11 and a P-channel MOS semiconductor device 12. ing.

The N-channel type MOS semiconductor device 11
Is located in a region of the semiconductor layer 22a aligned with the gate electrode 3.
A source 6 and a drain 7 made of an N-type high concentration impurity layer are provided. Similarly, the P-channel type MOS semiconductor device 12 has a source 16 and a drain 17 made of a P-type high-concentration impurity layer in a region of the semiconductor layer 22b that matches the gate electrode 3.

The N-channel MOS semiconductor device 11 and the P-channel MOS semiconductor device 12 are
And the insulating film 21 are completely insulated and separated. Then, through each contact hole 9 formed in the interlayer insulating film 8, the gate electrode 3, the source 6, the drain 7, and the P
Wiring 10 having one end connected to gate electrode 3, source 17, and drain 17 of channel type MOS semiconductor device 12.
(The wiring 10 connected to the gate electrodes 3, 3 is provided at a cross-sectional position different from the cross-section shown in FIG. 70), and is connected to another MOS type semiconductor device provided on the SOI substrate 23. .

Next, the semiconductor device shown in FIG.
An example of the structure of a conventional semiconductor device provided with a NOS type semiconductor device will be described with reference to FIG. The semiconductor device shown in FIG. 71 is provided on a common semiconductor substrate 1 made of silicon.
N-channel type MOS semiconductor device 11 and P-channel type MO
The S semiconductor device 12 and the MONOS type semiconductor device 35 are formed.

In an N-channel MOS semiconductor device 11, a gate oxide film 2 and a gate electrode 3 are provided on a surface of a semiconductor substrate 1 on a P well 4 provided by a P-type impurity layer in the semiconductor substrate 1; On the surface of the semiconductor substrate 1 aligned with the semiconductor substrate 3, a source 6 formed of an N-type high-concentration impurity layer is formed.
And a drain 7.

In a P-channel type MOS semiconductor device 12, a gate oxide film 2 and a gate electrode 3 are provided on a surface of a semiconductor substrate 1 on an N well 5 provided by an N-type impurity layer in the semiconductor substrate 1. The source 1 formed by a P-type high concentration impurity layer
6 and a drain 17 are provided.

The MONOS type semiconductor device 35 includes a memory oxide film 31 and a memory nitride film 3 on a surface of the semiconductor substrate 1 on a P well 4 provided by a P type impurity layer in the semiconductor substrate 1.
A memory insulating film 34 composed of a second oxide film 2 and a top oxide film 33;
A memory gate electrode 50;
A source 7 (common with the drain 7 of the N-channel type MOS semiconductor device 11) and a drain 18 formed of an N-type high-concentration impurity layer are provided on the surface of the semiconductor substrate 1 matched with the semiconductor substrate 1.

This P-channel type MOS semiconductor device 12
And N-channel type MOS semiconductor device 11 and MONO
The element is separated from the S-type semiconductor device 35 by the field oxide film 13 formed on the surface of the semiconductor substrate 1. Then, an interlayer insulating film 8 is formed on the entire surface of the semiconductor substrate 1, and each gate electrode 3, source 6, and source 6 of each of the semiconductor devices 11, 12, 35 are respectively formed through contact holes 9 formed in the interlayer insulating film 8. 16, and drains 7, 17, 1
A wiring 10 having one end connected to 8 connects to another semiconductor device provided on the semiconductor substrate 1.

A method of manufacturing the semiconductor device shown in FIG. 71 will be described with reference to cross-sectional views showing respective steps of FIGS. 72 to 76. The first half of the manufacturing process of the semiconductor device is the same as each process described with reference to FIGS. 29 to 34 in the description of the third embodiment of the method of manufacturing a semiconductor device according to the present invention. The illustration is omitted, and description will be made only with reference to FIG.

First, an oxide film is formed on the surface by oxidizing a semiconductor substrate 1 made of silicon in an oxidizing atmosphere. Next, a photoresist, which is a photosensitive resin, is formed on the entire surface of the oxide film by a spin coating method.
A photoresist is patterned by exposing and developing using a predetermined mask so as to open an N-channel region which is a region for forming the OS semiconductor device and the MONOS type semiconductor device. Thereafter, the oxide film is etched using the photoresist as an etching mask.

Then, the semiconductor substrate 1 is oxidized in an oxidizing atmosphere to form a first buffer oxide film. After that, boron, which is a P-type impurity for forming a P-well, is ion-implanted. As a result, boron is implanted into the surface region of the semiconductor substrate 1 in the N-channel region 42 having the first buffer oxide film having a small oxide film thickness.

Next, after removing the oxide film and the first buffer oxide film, the substrate is oxidized in an oxidizing atmosphere to form a second buffer oxide film over the entire surface, and a region for forming a P-channel type MOS semiconductor device is formed. A photoresist is formed so as to open the P channel region 43, which is the above. Using this photoresist as an ion implantation mask, phosphorus, which is an N-type impurity, is ion-implanted into the P-channel region 43. Then the second
Of the buffer oxide film is removed.

Then, by performing oxidation and heat treatment in a minute oxidation atmosphere, the ion-implanted impurities are activated,
A P well 4 and an N well 5 are formed, and a pad oxide film is formed on the surface of the semiconductor substrate 1.

Next, a nitride film made of a silicon nitride film is formed on the entire surface by a chemical vapor deposition method, and is formed in an element formation region of an N-channel type MOS semiconductor device, a P-channel type MOS semiconductor device, and a MONOS type semiconductor device. A photoresist is formed. Using the photoresist as an etching mask, the nitride film is etched.

Thereafter, by performing selective oxidation in an oxidizing atmosphere, a field oxide film 13 shown in FIG. 72 is formed.
The nitride film and the pad oxide film are removed. Next, oxidation is performed in an oxidizing atmosphere to form a gate oxide film 2 as shown in FIG. 72, and a first gate electrode material 48 is formed on the gate oxide film 2.

Then, a photoresist 113 is formed in a region where a gate electrode is to be formed. This photoresist 11
3 as an etching mask, the first gate electrode material 4
8 is etched to form a gate electrode 3 as shown in FIG. Further, the gate oxide film 2 other than the portion under the gate electrode 3 is removed.

Thereafter, oxidation is performed in an oxidizing atmosphere to form a memory oxide film 31 shown in FIG. Next, heat treatment is performed in an ammonia atmosphere to turn the memory oxide film 31 into a nitrided oxide film.

In this heat treatment in an ammonia atmosphere, ammonia and hydrogen diffuse into the gate oxide film 2 constituting the already formed MOS type semiconductor device, so that the gate oxide film 2, the gate oxide film 2 and the semiconductor substrate 1 The problem arises that a positive charge is induced at the interface with the substrate. Since this positive charge remains without recovering until the end of the process, the MOS
There is a problem that the threshold voltage of the semiconductor device is changed.

Next, a memory nitride film 32, a top oxide film 33, and a second gate electrode material 49 are sequentially formed on the entire surface of the memory oxide film 31. Thereafter, a photoresist 114 is formed in a region for forming a memory gate electrode of the MONOS type semiconductor device.
To form

Using this photoresist 114 as an etching mask, the second gate electrode material 49, the top oxide film 33, the memory nitride film 32 and the memory oxide film 31 are etched, and as shown in FIG. Electrode 50
To form Thereafter, arsenic, which is an N-type impurity, is ion-implanted into the surface of the semiconductor substrate 1 in the N-channel region 42 so as to match the gate electrode 3 and the memory gate electrode 50.
A source 6 and a drain 7 which are high concentration impurity layers shown in FIG.

Next, the P channel region 4 in FIG.
On the surface of the semiconductor substrate 1, boron as a P-type impurity is ion-implanted in alignment with the gate electrode 3 to form a source 16 and a drain 17 as high-concentration impurity layers shown in FIG. A heat treatment for activating the impurities is performed.

Further, as shown in FIG. 76, an interlayer insulating film 8 is formed on the entire surface, a contact hole 9 shown in FIG. 71 is opened in the interlayer insulating film 8, and a wiring 10 is formed. Thus, the N-channel type MOS semiconductor device 11 using the semiconductor substrate 1 made of silicon and the P-channel type
A semiconductor device in which the S semiconductor device 12 and the MONOS type semiconductor device 35 are formed on the same semiconductor substrate 1 is manufactured.

[0030]

In some cases, the MOS type semiconductor device having the above-described structure is used as a control device for an artificial satellite or a nuclear reactor which is launched into outer space. However, when the above-described conventional semiconductor device is used in an environment where such gamma rays are irradiated, positive charges are generated in the gate oxide film or at the interface between the semiconductor substrate and the gate oxide film. , The threshold voltage of the N-channel MOS semiconductor device decreases, and a leak current occurs. On the other hand, the threshold voltage of the P-channel type MOS semiconductor device rises and becomes inoperable.

In addition, N on a semiconductor substrate made of silicon
When manufacturing a semiconductor device provided with a channel type MOS semiconductor device, a P-channel type MOS semiconductor device and a MONOS type semiconductor device, in order to improve the write / erase characteristics of the MONOS type semiconductor device, the memory oxide film is formed in an ammonia atmosphere. Heat treatment is performed to form a nitrided oxide film. At that time, as described above, a positive charge is induced in the gate oxide film and at the interface between the gate oxide film and the semiconductor substrate due to the reaction of ammonia and hydrogen, and a failure due to a shift in threshold voltage has occurred.

The present invention solves these problems and suppresses the shift of the threshold value of a MOS type semiconductor device under a radiation environment. Further, the present invention provides a MOS type semiconductor device and a MONOS type semiconductor device on the same semiconductor substrate. It is an object of the present invention to suppress a shift in the threshold value of a MOS type semiconductor device which occurs during a heat treatment in an ammonia atmosphere in a manufacturing process of a semiconductor device provided with the above.

[0033]

A semiconductor device according to the present invention has the following configuration to achieve the above object. An N-channel MOS semiconductor device and a P-channel MOS semiconductor device each having a gate insulating film provided on a semiconductor substrate and a gate electrode provided on the gate insulating film are provided. A gate oxide film made of a silicon film and a gate silicon nitride film
It was composed of a layer film.

Alternatively, the gate insulating film of the N-channel type MOS semiconductor device is constituted by a gate oxide film composed of a silicon dioxide film, and the gate insulating film of the P-channel type MOS semiconductor device is constituted by a gate oxide film composed of a silicon dioxide film. A two-layer film of a film and a gate silicon nitride film may be used.

These semiconductor devices further include a memory insulating film comprising a memory oxide film, a memory nitride film, and a top oxide film provided on the semiconductor substrate, and a memory gate electrode provided on the memory insulating film. A MONOS type semiconductor device can be provided.

An N-channel type having an SOI substrate comprising a supporting substrate, an insulating film and an island-shaped semiconductor layer, a gate insulating film provided on the semiconductor layer, and a gate electrode provided on the gate insulating film, respectively. Even in a semiconductor device including a MOS semiconductor device and a P-channel type MOS semiconductor device, it is preferable that the gate insulating film is formed of a two-layer film of a gate oxide film made of a silicon dioxide film and a gate silicon nitride film.

Also in this case, the gate insulating film of the N-channel type MOS semiconductor device is constituted by a gate oxide film made of a silicon dioxide film, and the gate insulating film of the P-channel type MOS semiconductor device is made of a gate oxide film made of a silicon dioxide film. A two-layer film of a film and a gate silicon nitride film may be used.

In these semiconductor devices, a memory insulating film comprising a memory oxide film, a memory nitride film and a top oxide film provided on the semiconductor layer and a memory gate electrode provided on the memory insulating film are further provided. MONOS-type semiconductor device can be provided.

The method for manufacturing a semiconductor device according to the present invention comprises:
In order to achieve the above object, the method includes the following steps (1) to (17). (1) a step of oxidizing the semiconductor substrate in an oxidizing atmosphere to form an oxide film on the entire surface of the semiconductor substrate;
Etching the oxide film in the N-channel region forming the channel type MOS semiconductor device;

(3) forming a first buffer oxide film for introducing a P-type impurity into the N-channel region;
(4) a step of introducing a P-type impurity into the N-channel region of the semiconductor substrate; and (5) forming a second buffer oxide film on the entire surface of the semiconductor substrate after etching the oxide film on the entire surface of the semiconductor substrate. Process,

(6) P-channel type MO on the semiconductor substrate
A step of introducing an N-type impurity into the P-channel region forming the S semiconductor device using a photosensitive resin as a mask; and (7) etching the second buffer oxide film to activate each of the introduced impurities. After performing in an oxidizing atmosphere, forming a pad oxide film on the entire surface of the semiconductor substrate, (8) forming a nitride film made of a silicon nitride film on the pad oxide film,

(9) etching the nitride film in the region of the semiconductor substrate where the field oxide film is to be formed;
(10) forming a field oxide film on the semiconductor substrate by selective oxidation, performing element isolation of the N-channel region and the P-channel region, and then removing the nitride film and the pad oxide film;

(11) The N channel region of the semiconductor substrate and P
Forming a gate oxide film in an oxidizing atmosphere on the entire surface of the channel region, forming a gate silicon nitride film on the entire surface of the gate oxide film, and forming a gate electrode material on the entire surface of the gate silicon nitride film; A) forming the gate electrode by etching the gate electrode material and the gate silicon nitride film;

(13) a step of forming an N-type high-concentration impurity layer in the source and drain formation regions in the N-channel region of the semiconductor substrate using the photosensitive resin as an ion implantation mask; Forming a P-type high-concentration impurity layer in the source and drain formation regions in the P-channel region of the semiconductor substrate by using as an ion implantation mask;

(15) a step of forming an interlayer insulating film mainly composed of a silicon dioxide film on the entire surface of the semiconductor substrate; (16) a step of activating the N-type and P-type high concentration impurity layers by heat treatment; Forming a plurality of contact holes in the interlayer insulating film by photoetching, (17) via the contact holes to the respective gate electrodes, sources, and drains of the N-channel MOS semiconductor device and the P-channel MOS semiconductor device; A step of forming wiring to be connected to each;

Further, instead of the above steps (11) and (12),
The following steps may be provided. Forming a gate oxide film in an oxidizing atmosphere over the entire surface of the N-channel region and the P-channel region of the semiconductor substrate, and forming a gate silicon nitride film over the entire surface of the gate oxide film; Removing the gate silicon nitride film so as to leave the gate silicon nitride film in the region, forming a gate electrode material over the entire semiconductor substrate, and forming the gate electrode by etching the gate electrode material ,

Further, when manufacturing a semiconductor device also provided with a MONOS type semiconductor device, the following steps are performed instead of the steps (11) and (12). Forming a gate oxide film in an oxidizing atmosphere on the entire surface of the N-channel region and the P-channel region of the semiconductor substrate, forming a gate silicon nitride film on the entire surface of the gate oxide film; Forming a first gate electrode material and forming a gate electrode by photoetching;

A step of forming a memory oxide film by oxidizing the entire surface of the semiconductor substrate in an oxidizing atmosphere, and performing a heat treatment in an ammonia atmosphere to turn the memory oxide film into a nitrided oxide film; Forming a nitride film, oxidizing the memory nitride film in an oxidizing atmosphere to form a top oxide film, and forming a second gate electrode material on the entire surface of the top oxide film;

In the step of etching the second gate electrode material, the top oxide film, the memory nitride film and the memory oxide film by photoetching to form a memory gate electrode, and in the step (17), a contact hole is formed. Through an N-channel type MOS semiconductor device and a P-channel type
Wirings respectively connected to the gate electrodes, the source, and the drain of the OS semiconductor device and the MONOS type semiconductor device are formed.

When an SOI substrate composed of a support substrate, an insulating film and a semiconductor layer is used, the following steps (1) to (14) are included. (1) A photosensitive resin is formed on a semiconductor layer of an SOI substrate, and the semiconductor layer is etched using the photosensitive resin as an etching mask to form an island-shaped first semiconductor device for forming an N-channel MOS semiconductor device. Forming a semiconductor layer and an island-shaped second semiconductor layer forming a P-channel MOS semiconductor device;

(2) a step of oxidizing each of the first and second semiconductor layers in an oxidizing atmosphere to form a gate oxide film on the surface of each semiconductor layer; and (3) using a photosensitive resin as an ion implantation mask. Forming a P-type channel impurity layer in the region of the first semiconductor layer using (4) using a photosensitive resin as an ion implantation mask and forming an N-type channel impurity layer in the region of the second semiconductor layer; Forming a,

(5) a step of forming a P-type inversion preventing impurity layer in the boundary region of the first semiconductor layer by using a photosensitive resin as an ion implantation mask; and (6) a step of using the photosensitive resin as an ion implantation mask. , N in the boundary region of the second semiconductor layer
(7) forming a gate silicon nitride film on the gate oxide film on the surface of each semiconductor layer, and forming a gate electrode material on the gate silicon nitride film; (8) etching the gate electrode material and the gate silicon nitride film to form a gate electrode;

(9) forming an N-type high-concentration impurity layer in the source and drain formation regions of the first semiconductor layer using a photosensitive resin as an ion implantation mask;
(10) a step of forming a P-type high-concentration impurity layer in the source and drain formation regions of the second semiconductor layer using a photosensitive resin as an ion implantation mask; Forming an interlayer insulating film mainly composed of a silicon film;

(12) a step of activating the N-type and P-type high-concentration impurity layers by heat treatment, (13) a step of forming a plurality of contact holes in the interlayer insulating film by photoetching, and (14) a contact hole. Forming wirings respectively connected to the gate electrode, source and drain of the N-channel MOS semiconductor device and the P-channel MOS semiconductor device through

Further, the following steps may be provided instead of the steps (7) and (8). Forming a gate silicon nitride film on the gate oxide film on the surface of each of the semiconductor layers, and leaving the gate silicon nitride film in the region of the first semiconductor layer by photoetching, and leaving the gate silicon nitride film in the other region Removing the nitride film, forming a gate electrode material on the entire surface of the semiconductor layer, etching the gate electrode material to form a gate electrode,

Further, a MOS semiconductor device and a MONO device are formed by using an SOI substrate comprising a support substrate, an insulating film and a semiconductor layer.
When a semiconductor device including the S-type semiconductor device is manufactured, each of the following steps (1) to (16) is performed. (1) A photosensitive resin is formed on a semiconductor layer of an SOI substrate, and the semiconductor layer is etched using the photosensitive resin as an etching mask to form an island-shaped first semiconductor device for forming an N-channel MOS semiconductor device. A semiconductor layer, a second island-shaped semiconductor layer forming a P-channel type MOS semiconductor device,
Forming an island-shaped third semiconductor layer forming an S-type semiconductor device;

(2) a step of oxidizing each of the first to third semiconductor layers in an oxidizing atmosphere to form a gate oxide film on the surface of each semiconductor layer; and (3) using a photosensitive resin as an ion implantation mask. Forming a P-type channel impurity layer in a region of the first semiconductor layer and the third semiconductor layer by using (4) using a photosensitive resin as an ion implantation mask; Forming an N-type channel impurity layer;

(5) forming a P-type inversion preventing impurity layer in a boundary region between the first semiconductor layer and the third semiconductor layer using a photosensitive resin as an ion implantation mask; (6)
Forming an N-type inversion prevention impurity layer in the boundary region of the second semiconductor layer using a photosensitive resin as an ion implantation mask; and (7) forming a gate silicon nitride film on the entire surface of the semiconductor substrate. (8) forming a first gate electrode material on the entire surface of the gate silicon nitride film and forming a gate electrode by photoetching;

(9) A step of forming a memory oxide film by oxidizing the entire surface of the semiconductor substrate in an oxidizing atmosphere and then performing a heat treatment in an ammonia atmosphere to turn the memory oxide film into a nitrided oxide film; (10) Forming a memory nitride film on the memory oxide film,
Oxidizing the memory nitride film in an oxidizing atmosphere to form a top oxide film, and forming a second gate electrode material on the top oxide film; (11) photoetching the second gate electrode material Forming a memory gate electrode by etching the top oxide film, the memory nitride film, and the memory oxide film,

(12) forming an N-type high-concentration impurity layer in the source and drain formation regions of the first and third semiconductor layers using a photosensitive resin as an ion implantation mask; Forming a P-type high-concentration impurity layer in the source and drain formation regions of the second semiconductor layer using a conductive resin as an ion implantation mask; (13) forming a silicon dioxide film on the entire surface of the semiconductor layer; Forming an interlayer insulating film as a main component,

(14) a step of activating the N-type and P-type high-concentration impurity layers by a heat treatment; (15) a step of forming a plurality of contact holes in the interlayer insulating film by photoetching; Forming wirings connected to the respective gate electrodes, sources, and drains of the N-channel type MOS semiconductor device, the P-channel type MOS semiconductor device, and the MONOS type semiconductor device through the holes;

As described above, in the semiconductor device and the method of manufacturing the same according to the present invention, the gate insulating film between the N-channel type MOS semiconductor device and the P-channel type MOS semiconductor device,
Alternatively, only the gate insulating film of the P-channel type MOS semiconductor device is formed as a two-layer film of a gate oxide film made of a silicon dioxide film and a gate silicon nitride film.

Therefore, in the processing during the manufacturing process such as the heat treatment in an ammonia atmosphere, the diffusion of the reaction gas such as ammonia and hydrogen is suppressed by the gate silicon nitride film which is a dense film constituting the gate insulating film. Therefore, a reaction between the gate oxide film and the gate oxide film and the semiconductor substrate can be suppressed, an action of preventing generation of positive charges in this region can be obtained, and a change in threshold voltage can be suppressed.

Further, since the gate insulating film is composed of a two-layer film of a silicon dioxide film and a gate oxide film and a gate silicon nitride film, there is a problem of matching at the interface between the gate oxide film and the gate silicon nitride film. Therefore, an interface state having a charge is generated at this interface.

In the MOS type semiconductor device according to the present invention,
In order to respond to this interface state, the well concentration is controlled,
Controls the threshold voltage. Therefore, when this semiconductor device is used in a radiation irradiation environment, the positive charge generated by irradiation with gamma rays or the like is reduced by the interface state, and a change in threshold voltage is suppressed.

[0066]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, a structure of a semiconductor device according to the present invention and an optimum mode for carrying out a method of manufacturing the same will be described in detail. First, first to sixth embodiments of the semiconductor device according to the present invention will be described with reference to FIGS. 1 to 6, respectively.

[First Embodiment of Semiconductor Device: FIG. 1]
The structure of the first embodiment of the semiconductor device according to the present invention
This will be described with reference to the schematic sectional view of FIG. The semiconductor device of FIG. 1 uses a semiconductor substrate made of silicon, and an N-channel MOS semiconductor device 11 and a P-type
The channel type MOS semiconductor device 12 is formed to constitute a complementary MOS type semiconductor device.

In the N-channel type MOS semiconductor device 11, a gate insulating film 62 and a gate electrode 3 are provided on the surface of the semiconductor substrate 1 on a P well 4 provided by a P-type impurity layer in the semiconductor substrate 1, On the surface of the semiconductor substrate 1 aligned with 3, a source 6 and a drain 7 formed of an N-type high concentration impurity layer are provided. The gate insulating film 62
Is composed of a two-layer film of a gate oxide film 2 made of a silicon dioxide film and a gate silicon nitride film 61.

In the P-channel type MOS semiconductor device 12, a gate insulating film 62 and a gate electrode 3 are provided on the surface of the semiconductor substrate 1 on an N well 5 provided by an N-type impurity layer in the semiconductor substrate 1, The source 16 and the drain 17 formed of a P-type high-concentration impurity layer are provided on the surface of the semiconductor substrate 1 aligned with the semiconductor substrate 3.

The gate insulating film 62 is also formed of a gate oxide film 2 made of a silicon dioxide film and a gate silicon nitride film 61.
And a two-layer film. The N-channel type MOS semiconductor device 11 and the P-channel type MOS semiconductor device 12 are composed of a field oxide film 1 formed on a surface of a semiconductor substrate 1.
3 separates elements.

Then, an interlayer insulating film 8 is formed on the entire surface of the semiconductor substrate 1, and the gate electrodes 3, 3 and the source 6 of each of the semiconductor devices 11 and 12 are formed through the contact holes 9 formed in the interlayer insulating film 8. , 16 and drains 7, 17
The other MOS provided on the semiconductor substrate 1 by the wiring 10 having one end connected thereto (the wiring 10 connected to the gate electrodes 3 and 3 is provided at a position different from the cross section shown in FIG. 1). Connected to the semiconductor device.

In this semiconductor device, the gate insulating film 62 of the N-channel type MOS semiconductor device 11 and the P-channel type MOS semiconductor device 12 is replaced with a two-layer film of a gate oxide film 2 made of a silicon dioxide film and a gate silicon nitride film 61. Therefore, due to the problem of matching at the interface between the gate oxide film and the gate silicon nitride film, an interface state having charges is generated at this interface.

To cope with this interface state, the threshold voltage is controlled by controlling the concentration of the well. Therefore, when this semiconductor device is used in a radiation irradiation environment, positive charges generated by irradiation with gamma rays or the like are reduced by the interface states. Thereby, a change in the threshold voltage can be suppressed.

[Second Embodiment of Semiconductor Device: FIG. 2] Next, the structure of a semiconductor device according to a second embodiment of the present invention will be described.
This will be described with reference to the schematic sectional view of FIG. The semiconductor device shown in FIG. 2 has an SOI substrate 23 including a support substrate 20, an insulating film 21, and a plurality of island-shaped semiconductor layers 22a and 22b.
Is used.

Then, a gate insulating film 62 and a gate electrode 3 are formed on each of the semiconductor layers 22a and 22b of the SOI substrate 23.
Are provided to constitute a semiconductor device including an N-channel MOS semiconductor device 11 and a P-channel MOS semiconductor device 12. The gate insulating film 62 is composed of a two-layer film of a gate oxide film 2 made of a silicon dioxide film and a gate silicon nitride film 61.

This N-channel type MOS semiconductor device 11
Is applied to the semiconductor layer 22a in a region aligned with the gate electrode 3.
A source 6 and a drain 7 made of an N-type high concentration impurity layer are provided. Similarly, the P-channel type MOS semiconductor device 12 includes a P-type MOS semiconductor device
16 and drain 17 composed of high-concentration impurity layers
Are provided.

The N channel type MOS semiconductor device 11 and the P channel type MOS semiconductor device 12 are
And the insulating film 21 are completely insulated and separated. Then, a wiring 10 for connecting one end to each of the gate electrodes 3 and 3, the sources 6 and 16, and the drains 7 and 17 of each of the semiconductor devices 11 and 12 via the contact holes 9 formed in the interlayer insulating film 8. (Gate electrodes 3 and 3
The wiring 10 connected to the wiring is provided at a position different from the cross section shown in FIG. 2).

Also in this semiconductor device, the gate insulating film 62 of the N-channel type MOS semiconductor device 11 and the P-channel type MOS semiconductor device 12 is replaced with a two-layer film of a gate oxide film 2 made of a silicon dioxide film and a gate silicon nitride film 61. Therefore, an interface state having electric charge is generated at the interface between the gate oxide film and the gate silicon nitride film. Therefore, when this semiconductor device is used in a radiation irradiation environment, positive charges generated by irradiation with gamma rays or the like are reduced by the interface states. Thereby, a change in the threshold voltage can be suppressed.

[Third Embodiment of Semiconductor Device: FIG. 3] Next, the structure of a third embodiment of the semiconductor device according to the present invention will be described with reference to a schematic sectional view of FIG.

FIG. 3 shows an N channel type MOS semiconductor device 11, a P channel type MOS semiconductor device 12, and a MONOS type semiconductor device 35 using a semiconductor substrate made of silicon.
1 shows the structure of a semiconductor device formed on the same semiconductor substrate 1. The structures of the N-channel MOS semiconductor device 11 and the P-channel MOS semiconductor device 12 are the same as in the first embodiment described with reference to FIG.

In the MONOS type semiconductor device 35, the memory oxide film 31 and the memory nitride film 3 are formed on the surface of the semiconductor substrate 1 on the P well 4 provided by the P type impurity layer in the semiconductor substrate 1.
2 and a top oxide film 33 are provided, and a memory gate electrode 50 is provided on the top oxide film 33. Then, on the surface of the semiconductor substrate 1 aligned with the memory gate electrode 50, a source 7 (an N-channel MOS semiconductor device 1) formed of an N-type high-concentration impurity layer is formed.
1 and a drain 18).

This P-channel type MOS semiconductor device 12
And N-channel type MOS semiconductor device 11 and MONO
The element is separated from the S-type semiconductor device 35 by the field oxide film 13 formed on the surface of the semiconductor substrate 1.

As described above, also in the semiconductor device provided with the MONOS type semiconductor device, the gate insulating films of the N-channel type MOS semiconductor device and the P-channel type MOS semiconductor device are replaced with a gate oxide film made of a silicon dioxide film and a gate silicon film. By forming a two-layered film with a nitride film, an interface state having charges is generated at the interface between the gate oxide film and the gate silicon nitride film. Accordingly, when the semiconductor device is used in a radiation irradiation environment, positive charges generated by irradiation with gamma rays or the like are reduced by the interface states.

In a process during a manufacturing process such as a heat treatment in an ammonia atmosphere, the diffusion of a reaction gas such as ammonia or hydrogen is suppressed by the gate silicon nitride film, which is a dense film constituting the gate insulating film. Therefore,
The gate oxide film and the reaction between the gate oxide film and the semiconductor substrate can be suppressed, and the generation of positive charges in this region is prevented. Thus, a change in threshold voltage can be suppressed.

[Fourth Embodiment of Semiconductor Device: FIG. 4] Next, the structure of a semiconductor device according to a fourth embodiment of the present invention will be described with reference to a schematic sectional view of FIG. This figure 4
The semiconductor device shown in FIG. 1 includes a support substrate 20, an insulating film 21, and a plurality of island-shaped semiconductor layers 22a, 22b, and 22c.
An OI substrate 23 is used.

The N-channel MOS semiconductor device 11, the P-channel MOS semiconductor device 12, and the MONOS semiconductor device 35 are provided on the respective semiconductor layers 22a, 22b, 22c of the SOI substrate 23. The structures of the N-channel MOS semiconductor device 11 and the P-channel MOS semiconductor device 12 are the same as in the second embodiment described with reference to FIG.

In the MONOS type semiconductor device 35, the memory oxide film 31 and the memory nitride film 32 are formed on the surface of the semiconductor layer 22c.
A memory insulating film 34 consisting of a top oxide film 33 and a memory gate electrode 50; and a source 26 and a drain 27 formed of an N-type high concentration impurity layer in the semiconductor layer 22c in alignment with the memory gate electrode 50. Is provided.

The N-channel type MOS semiconductor device 11, the P-channel type MOS semiconductor device 12, and the MONOS type semiconductor device 35 are completely insulated and separated by the interlayer insulating film 8 and the insulating film 21.

Then, a contact hole 9 is formed in the interlayer insulating film 8, and the gate electrode 3 of each of the semiconductor devices 11, 12 and 35 is formed through the contact hole 9.
3,50, source 6,16,26, drain 7,17,
27 (the wirings 10 connected to the gate electrodes 3, 3, and 50 are provided at positions different from the cross section shown in FIG. 4).
It is connected to another semiconductor device provided on the OI substrate 23. The operation and effects of the fourth embodiment are the same as those of the third embodiment.

[Fifth Embodiment of Semiconductor Device: FIG. 5] The structure of a fifth embodiment of the semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG. The semiconductor device shown in FIG. 5 uses a semiconductor substrate 1 made of silicon,
An N-channel MOS semiconductor device 1 is provided on the semiconductor substrate 1.
1 and a P-channel type MOS semiconductor device 12 to form a complementary MOS type semiconductor device.

This semiconductor device is similar to the first embodiment shown in FIG. 1 except that the gate insulating film of the N-channel type MOS semiconductor device 11 is constituted only by the gate oxide film 2 made of a silicon dioxide film. The configuration is the same as that of the embodiment.

In the fifth embodiment, the N-channel type M
The gate insulating film of the OS semiconductor device 11 is a gate oxide film 2
The gate insulating film 62 of the P-channel type MOS semiconductor device 12 is formed of a two-layer film of the gate oxide film 2 and the gate silicon nitride film 61. Even with such a configuration, a change in threshold voltage when the semiconductor device is used in a radiation irradiation environment can be suppressed.

The N-channel MOS semiconductor device 11 and the P-channel MOS semiconductor device 12 of this semiconductor device are:
Elements are separated by a field oxide film 13 formed on the surface of the semiconductor substrate 1. Then, an interlayer insulating film 8 is formed on the entire surface of the semiconductor substrate 1, and each of the semiconductor devices 11, 1 is connected through a contact hole 8 formed in the interlayer insulating film 8.
2 is connected to another MOS type semiconductor device provided on the semiconductor substrate 1 by a wiring 10 having one end connected to each electrode.

[Sixth Embodiment of Semiconductor Device: FIG. 6] Next, the structure of a sixth embodiment of the semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG. This figure 6
Is an N-channel MOS semiconductor device 1
The configuration is the same as that of the second embodiment shown in FIG. 2 except that one gate insulating film 62 is composed only of the gate oxide film 2 made of a silicon dioxide film.

In the sixth embodiment, the gate insulating film of the N-channel type MOS semiconductor device 11 is constituted only by the gate oxide film 2, and the gate insulating film 62 of the P-channel type MOS semiconductor device 12 is formed by the gate oxide film. It is composed of a two-layer film of a film 2 and a gate silicon nitride film 61. Even with such a configuration, a change in threshold voltage when the semiconductor device is used in a radiation irradiation environment can be suppressed.

The N-channel type MOS semiconductor device 11 and the P-channel type MOS semiconductor device 12 are
And the insulating film 21 are completely insulated and separated. Then, a wiring 10 having one end connected to each electrode of each of the semiconductor devices 11 and 12 is provided through each contact hole 9 formed in the interlayer insulating film 8.

[First Embodiment of Manufacturing Method: FIGS. 7 to 1]
8 and FIG. 1] Next, a method of manufacturing the semiconductor device (first embodiment) according to the present invention described with reference to FIG. 1 will be described as a first embodiment of the manufacturing method. 7 to 14
FIG. 2 is a schematic cross-sectional view showing a semiconductor device or its material in each step of the manufacturing method. The first embodiment of the method for manufacturing a semiconductor device will be described with reference to these drawings and FIG. 1 showing a completed state.

First, as shown in FIG. 7, an oxidation process is performed on a semiconductor substrate 1 of N-type conductivity in a steam oxidation atmosphere to form an oxide film 41 of a 550 nm thick silicon dioxide film on the entire surface.

Next, a photoresist, which is a photosensitive resin, is formed on the entire surface of the oxide film 41, and exposure and development are performed using a predetermined photomask to form an N-channel type MO.
N channel region 42 which is a region for forming an S semiconductor device
The photoresist 91 is patterned so as to open the openings. Then, using this photoresist 91 as an etching mask, the oxide film 41 is etched with a hydrofluoric acid buffer. After that, the photoresist 91 used as the etching mask is removed.

Next, an oxidation process is performed in a mixed gas of oxygen and nitrogen to form a first buffer oxide film 44 of a silicon dioxide film having a thickness of 80 nm as shown in FIG. As a result, a thick oxide film 41 is formed on the surface of the semiconductor substrate 1 in the P channel region 43 which is a region for forming the P channel type MOS semiconductor device, and an oxide film thinner than the oxide film 41 is formed in the N channel region 42. Is formed on the surface of the semiconductor substrate 1.

Thereafter, boron, which is a P-type impurity, is subjected to an acceleration energy of 60 KeV and an ion implantation amount of 2.0 × 10 ¹³ at.
Ions are implanted at about oms / cm ² . This ion implantation is performed only in the semiconductor substrate 1 in the N-channel region 42 where the thickness of the oxide film is small. Thereafter, the oxide film 41 and the first buffer oxide film 44 are removed by etching the entire surface with a hydrofluoric acid buffer.

Then, an oxidation process is performed in a mixed gas of oxygen and nitrogen to form a second buffer oxide film 45 made of a silicon dioxide film having a thickness of 40 nm on the entire surface of the semiconductor substrate 1 as shown in FIG. I do. Thereafter, a photoresist is formed on the entire surface, and exposure and development are performed using a predetermined photomask, so that the P channel region 43 is opened.
A photoresist 92 is patterned.

Then, using this photoresist 92 as an ion implantation mask, phosphorus, which is an N-type impurity, is implanted at an acceleration energy of 100 KeV and an ion implantation amount of about 8.0 × 10 ¹² atoms / cm ^2. Under the conditions described above, ions are implanted into the semiconductor substrate 1 in the P-channel region 43. Thereafter, the photoresist 92 is removed, and the entire surface of the second buffer oxide film 45 is etched with a hydrofluoric acid buffer.

Next, the semiconductor substrate 1 is heat-treated in a mixed gas of oxygen and nitrogen. This heat treatment activates the ion-implanted impurities. As shown in FIG. 10, the P well 4 is formed in the N channel region 42 and the P channel region 43 is formed.
An N well 5 is formed. Further, a pad oxide film 46 made of a silicon dioxide film having a thickness of 20 nm is formed on the entire surface of the semiconductor substrate 1 by this heat treatment.

Then, dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (N
Using a gas of H ₃ ), a nitride film 47 made of a silicon nitride film is formed to a thickness of about 120 nm by a chemical vapor deposition method (hereinafter referred to as “CVD method”) at a temperature of 740 ° C.

Thereafter, a photoresist, which is a photosensitive resin, is formed on the entire surface of the nitride film 47, and is exposed and developed using a predetermined photomask, and as shown in FIG. A photoresist 93 is formed so as to open the field region.

Then, using the photoresist 93 as an etching mask, the nitride film 47 is removed by etching. The etching of the nitride film 47 is performed by a dry etching method using a mixed gas of SF ₆ , CHF ₃ and He.

Then, as shown in FIG. 12, a field region around the element region is oxidized using the oxidation-resistant film of the nitride film 47 as a mask. It is formed with. This selective oxidation treatment is performed by performing oxidation treatment at a temperature of 1000 ° C. in a steam oxidation atmosphere.

Next, hot phosphoric acid (H ₃ H) heated to 180 ° C.
Using PO ₄ ), the nitride film 47 is removed, and the pad oxide film 46 is removed by etching with a hydrofluoric acid buffer. FIG. 12 shows the state after the removal.

Thereafter, an oxidation process is performed in a mixed gas of oxygen and nitrogen to form a gate oxide film 2 made of a silicon dioxide film having a thickness of about 10 nm on the N channel region of the semiconductor substrate 1 as shown in FIG. 42 and P channel region 43
Formed over the entire surface of the substrate. Then, a gate silicon nitride film 61 made of a silicon nitride film is formed on the entire surface of the semiconductor substrate 1 including the gate oxide film 2 by a CVD method to a thickness of about 5 nm.

The gate silicon nitride film 61 is formed by a CVD method at a temperature of 700 ° C. using a gas of dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). The two-layer film of the gate silicon nitride film 61 and the gate oxide film 2 forms a gate insulating film 62. Thereafter, using a gas of monosilane (SiH ₄ ), a temperature of 600
A gate electrode material 48 made of a polycrystalline silicon film is formed on the entire surface by CVD at a temperature of about 450 nm.

Next, a photoresist is formed on the entire surface,
Exposure and development are performed using a predetermined photomask, and a photoresist 94 is patterned in a region where a gate electrode is to be formed. Then, using the photoresist 94 as an etching mask, the gate electrode material 48 and the gate silicon nitride film 61 are etched by a dry etching method using a mixed gas of SF ₆ and O ₂ as an etching gas to form a pair of gate electrodes 3. To form afterwards,
The photoresist 94 is removed.

As a result, as shown in FIG. 13, a gate insulating film 62 composed of a two-layer film of a gate oxide film 2 and a gate silicon nitride film 61 formed on the semiconductor substrate 1, and a gate insulating film 62 Gate electrode material 48 formed in
Is the MO on the N channel region 42 and the P channel region 43
It is removed leaving only the part (the part with the gate electrode 3) constituting the S-type semiconductor device.

Next, a photoresist, which is a photosensitive resin, is formed on the entire surface of the semiconductor substrate 1, and is exposed and developed using a predetermined photomask, thereby forming an N-channel region 42 as shown in FIG. A photoresist 95 is patterned so as to open. Then, using this photoresist 95 as a mask for ion implantation, arsenic as an N-type impurity is ion-implanted at an acceleration energy of 60 KeV and an ion implantation amount of about 3.0 × 10 ¹⁵ atoms / cm ² . After that, the photoresist 95 used as a mask for ion implantation is removed.

Thereafter, a photoresist, which is a photosensitive resin, is formed again on the entire surface of the semiconductor substrate 1, exposed and developed using a predetermined photomask, and the P channel region 43 is opened as shown in FIG. The photoresist 97 is patterned in such a manner as to be performed. This photoresist 97
Is used as a mask for ion implantation, boron as a P-type impurity is ion-implanted at an acceleration energy of 40 KeV and an ion implantation amount of about 3.0 × 10 ¹⁵ atoms / cm ² . After that, the photoresist is removed.

Next, as shown in FIG. 17, an interlayer insulating film 8 mainly composed of a silicon dioxide film is formed on the entire surface. Then, a heat treatment at a temperature of 900 ° C. is performed in a nitrogen atmosphere to activate the implanted impurities and reflow the interlayer insulating film 8. As a result, the source 6 and the drain 7 composed of the N-type high-concentration impurity layer of the N-channel type MOS semiconductor device 11 and the source 16 and the drain 17 composed of the P-type high-concentration impurity layer of the P-channel type MOS semiconductor device 12 are formed. Is formed.

Thereafter, a photoresist 96 is formed on the entire surface of the interlayer insulating film 8, and is exposed and developed using a predetermined photomask to form a contact hole as a connection hole as shown in FIG. Opening 96a
To form

Then, the interlayer insulating film 8 is etched using the photoresist 96 as an etching mask.
A contact hole 9 is formed as shown in FIG. Etching for forming the contact hole 9 is performed by C ₂ F ₆
It is performed by a dry etching method using a mixed gas of He, CH and CHF ₃ as an etching gas. After that, the photoresist 96 used as the etching mask is removed.

Next, a wiring material mainly composed of aluminum is formed on the entire surface of the interlayer insulating film 8 (including the inside of the contact hole 9), and a photoresist for forming wiring is formed thereon. Then, using the photoresist as an etching mask, the wiring material is etched to provide the wiring 10 shown in FIG.

The etching of the wiring material is performed by a dry etching method using a mixed gas of BCl ₃ , CHCl ₃ , Cl ₂ and N ₂ as an etching gas. Thus, a semiconductor device including the N-channel MOS semiconductor device 11 and the P-channel MOS semiconductor device 12 shown in FIG. 1 is completed.

[Second Embodiment of Manufacturing Method: FIGS.
FIG. 28 and FIG. 2] Next, a method of manufacturing the semiconductor device (second embodiment) according to the present invention described with reference to FIG.
The manufacturing method will be described as a second embodiment. 19 to 28 are schematic sectional views showing a semiconductor device or its material in each step of the manufacturing method. The second embodiment of the method for manufacturing a semiconductor device will be described with reference to these drawings and FIG. 2 showing a completed state.

In this embodiment, as shown in FIG.
S composed of a supporting substrate 20, an insulating film 21, and a semiconductor layer 22
An OI substrate 23 is used. A photoresist is formed on the entire surface of the SOI substrate 23. Then, exposure and development are performed using a predetermined photomask, and an N-channel MO
N channel region 42 which is a region for forming an S semiconductor device
A photoresist 101 is pattern-formed on the upper portion and on a P-channel region 43 which is a region for forming a P-channel type MOS semiconductor device.

Then, using the photoresist 101 as an etching mask, the semiconductor layer 22 is etched. The etching of the semiconductor layer 22 is performed by a dry etching method using a mixed gas of SF ₆ and O ₂ as an etching gas. After that, the photoresist 101 used as the etching mask is removed.

As a result, as shown in FIG.
The semiconductor layer 22 of the I-substrate 23 becomes an island-shaped first semiconductor layer 22 a on the N-channel region 42 and an island-shaped second semiconductor layer 22 b on the P-channel region 43. Next, the SOI substrate is oxidized in a mixed gas of oxygen and nitrogen to form a gate oxide film 2 made of a silicon dioxide film having a thickness of about 10 nm as shown in FIG.
It is formed over the entire surface of the second semiconductor layers 22a and 22b.

Thereafter, a photoresist is formed on the entire surface of the SOI substrate, and exposure and development are performed using a predetermined photomask to pattern the photoresist 102 so as to open the N-channel region 42.

Using this photoresist 102 as a mask for ion implantation, boron, which is a P-type impurity, is implanted with an acceleration energy of 25 KeV and an ion implantation amount of about 2.0 × 10 ¹³ atoms / cm ² . Under the conditions, ions are implanted into the semiconductor layer 22a of the N channel region 42. Thereafter, the photoresist 10 used as an ion implantation mask
Remove 2.

Next, a photoresist is formed again on the entire surface of the SOI substrate, and exposure processing and development processing are performed using a predetermined photomask, and as shown in FIG. , Photoresist 10
3 is patterned. And this photoresist 1
03 is used as an ion implantation mask, phosphorus as an N-type impurity is implanted at an acceleration energy of 30 KeV and an ion implantation amount of 8.0.
At about × 10 ¹² atoms / cm ² , ions are implanted into the semiconductor layer 22b of the P channel region 43. After that, the photoresist 103 used as the ion implantation mask is removed.

Next, a photoresist is formed on the entire surface of the SOI substrate, and exposure and development are performed using a predetermined photomask to form an N-channel MOS semiconductor device as shown in FIG. A photoresist 104 is formed so as to open both ends of the semiconductor layer 22a in the N channel region 42.

Using this photoresist 104 as a mask, boron, which is a P-type impurity, is implanted with an acceleration energy of 25 KeV and an ion implantation amount of 6.0 × 10 ¹³ atoms.
The semiconductor layer 22a of the N channel region 42 is about s / cm ^2.
Ions are implanted into both ends of the. After that, the photoresist 104 used as the mask is removed.

Next, a photoresist is formed again on the entire surface of the SOI substrate, and exposure and development are performed using a predetermined photomask. As shown in FIG. 24, in a region where a P-channel MOS semiconductor device is to be formed. The photoresist 105 is patterned so as to open both ends of the semiconductor layer 22b in a certain P channel region 43.

Using the photoresist 105 as an ion implantation mask, phosphorus, which is an N-type impurity, is accelerated at an energy of 30 KeV and an ion implantation amount is 2.0 × 10 ¹³ atoms.
s / cm ² , the semiconductor layer 22 b of the P-channel region 43.
Ions are implanted into both ends of the. Then, photoresist 1
05 is removed. By implanting ions into the ends of the semiconductor layers 22a and 22b, an inversion preventing impurity layer is formed, the threshold voltage of the parasitic MOS formed in this portion is increased, and the involvement of the parasitic MOS can be prevented.

Next, as shown in FIG.
A gate silicon nitride film 61 made of a silicon nitride film is formed on the entire surface of the gate oxide film 2 formed on the entire surfaces of the gate oxide films 2a and 22b by a CVD method to a thickness of about 5 nm. The gate silicon nitride film 61 is formed by a CVD method at a temperature of 700 ° C. using a gas of dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). A gate insulating film 62 is constituted by a two-layer film of the gate silicon nitride film 61 and the gate oxide film 2.

Thereafter, a gate electrode material 48 made of a polycrystalline silicon film is formed on the entire surface of the gate insulating film 62 to a thickness of about 450 nm by a CVD method at a temperature of 600 ° C. using a gas of monosilane (SiH ₄ ). I do. Next, a photoresist is formed on the entire surface of the gate electrode material 48, exposure processing and development processing are performed using a predetermined photomask, and the photoresist 106 is pattern-formed only on the region where the gate electrode is to be formed.

Then, using the photoresist 106 as an etching mask, the gate electrode material 48 and the gate silicon nitride film 61 are etched by a dry etching method using a mixed gas of SF ₆ and O ₂ as an etching gas. Thereafter, the photoresist 106 used as the etching mask is removed.

As a result, as shown in FIG. 26, the gate oxide film 2 and the gate silicon nitride film 61 are formed on the semiconductor layer 22a on the N channel region 42 and the semiconductor layer 22b on the P channel region 43, respectively. A gate insulating film 62 composed of a two-layer film and the gate electrode 3 formed on the gate insulating film 62 constitute two MOS type semiconductor devices.

Next, a photoresist 107 is formed on the entire surface, and exposure and development are performed using a predetermined photomask. As shown in FIG. 27, the photoresist 107 is formed so as to open the N-channel region 42. I do. Using this photoresist 107 as a mask for ion implantation, arsenic, which is an N-type impurity, is implanted with an acceleration energy of 40 KeV and an ion implantation amount of 3.0 × 10 ¹⁵ atoms / c.
Ions are implanted into the exposed portion of the semiconductor layer 22a at about m ² . After that, the photoresist 107 is removed.

Thereafter, although not shown, a photoresist is formed again on the entire surface, and exposure and development are performed using a predetermined photomask to form a photoresist so as to open the P-channel region 43. Using this photoresist as a mask for ion implantation, boron, which is a P-type impurity, is ion-implanted into the exposed portion of the semiconductor layer 22b at an acceleration energy of 30 KeV and an ion implantation amount of about 3.0 × 10 ¹⁵ atoms / cm ^2. . After that, the photoresist is removed.

Next, as shown in FIG. 28, an interlayer insulating film 8 mainly composed of a silicon dioxide film is formed on the entire surface. Then, a heat treatment at a temperature of 900 ° C. is performed in a nitrogen atmosphere to activate the implanted impurities and reflow the interlayer insulating film 8.

As a result, the semiconductor layer 22 in the N channel region
The source 6 and the drain 7 made of the N-type high-concentration impurity layer of the N-channel type semiconductor device 11 are formed in a. Further, a source 16 and a drain 17 made of a P-type high-concentration impurity layer of the P-channel semiconductor device 12 are formed in the P-channel semiconductor layer 22b.

Thereafter, a photoresist (not shown) for forming a contact hole 9 as a connection hole is formed on the interlayer insulating film 8 by patterning. Then, using the photoresist as an etching mask, the contact holes 9 shown in FIG.
6 and the drains 7 and 17 are provided at corresponding positions.

The etching process for forming the contact hole 9 is performed by a dry etching method using a mixed gas of C ₂ F ₆ , He and CHF ₃ as an etching gas. After that, the photoresist is removed. Next, a wiring material mainly composed of aluminum is provided on the entire surface of the semiconductor substrate, and a photoresist for forming wiring is pattern-formed thereon.

Thereafter, using the photoresist as an etching mask, the wiring material is etched to provide the wiring 10 shown in FIG. The etching of this wiring material is performed by BC
Dry etching is performed using a mixed gas of l ₃ , CHCl ₃ , Cl _2, and N ₂ as an etching gas. Thus, a semiconductor device in which the N-channel semiconductor device 11 and the P-channel semiconductor device 12 are provided on the SOI substrate 23 shown in FIG. 2 is completed.

[Third Embodiment of Manufacturing Method: FIGS. 29 to 40 and FIG. 3] Next, the method of manufacturing the semiconductor device (third embodiment) according to the present invention described with reference to FIG. This will be described as a third embodiment of the manufacturing method. FIG. 29 to FIG.
0 is a schematic sectional view showing a semiconductor device or its material in each step of the manufacturing method. A third embodiment of the method of manufacturing a semiconductor device will be described with reference to these drawings and FIG. 3 showing a completed state.

First, as shown in FIG. 29, an oxidation treatment is performed on the N-type semiconductor substrate 1 in a steam oxidation atmosphere.
Oxide film 41 made of a silicon dioxide film having a thickness of 550 nm
Is formed on the entire surface.

Next, a photoresist is formed on the entire surface of the oxide film 41, exposure and development are performed using a predetermined photomask, and an N channel region 42 for forming an N channel type MOS semiconductor device is formed. The photoresist 110 is patterned so as to open.

Then, using this photoresist 110 as an etching mask, oxide film 41 is etched with a hydrofluoric acid buffer. After that, the photoresist 110 used as the etching mask is removed.

Next, an oxidation process is performed in a mixed gas of oxygen and nitrogen to form a first buffer oxide film 44 made of a silicon dioxide film having a thickness of 80 nm as shown in FIG. As a result, a thick oxide film 41 is formed on the surface of the semiconductor substrate 1 in the P channel region 43 which is a region for forming the P channel type MOS semiconductor device, and an oxide film thinner than the oxide film 41 is formed in the N channel region 42. Is formed on the surface of the semiconductor substrate 1.

Thereafter, boron, which is a P-type impurity, was implanted with an acceleration energy of 60 KeV and an ion implantation amount of 2.0 × 10 ¹³ at.
Ions are implanted at about oms / cm ² . This ion implantation is performed only in the semiconductor substrate 1 in the N-channel region 42 where the thickness of the oxide film is small. Thereafter, the oxide film 41 and the first buffer oxide film 44 are removed by etching the entire surface with a hydrofluoric acid buffer.

Then, an oxidation treatment is performed in a mixed gas of oxygen and nitrogen to form a second buffer oxide film 45 made of a silicon dioxide film having a thickness of 40 nm on the entire surface of the semiconductor substrate 1 as shown in FIG. I do. Thereafter, a photoresist is formed on the entire surface, exposure and development are performed using a predetermined photomask, and a pattern of the photoresist 111 is formed so as to open the P-channel region 43.

Using this photoresist 111 as an ion implantation mask, phosphorus, which is an N-type impurity, is implanted with an acceleration energy of 100 KeV and an ion implantation amount of about 8.0 × 10 ¹² atoms / cm ^2. Under the conditions described above, ions are implanted into the semiconductor substrate 1 in the P-channel region 43. Thereafter, the photoresist 111 is removed, and the entire surface of the second buffer oxide film 45 is etched with a hydrofluoric acid buffer.

Next, the semiconductor substrate 1 is heat-treated in a mixed gas of oxygen and nitrogen. By this heat treatment, the ion-implanted impurities are activated. As shown in FIG.
An N well 5 is formed. Further, a pad oxide film 46 made of a silicon dioxide film having a thickness of 20 nm is formed on the entire surface of the semiconductor substrate 1 by this heat treatment.

These steps are almost the same as those in the first embodiment of the method of manufacturing a semiconductor device described with reference to FIGS. However, in the case of the third embodiment, the N channel region 42 is sufficiently larger than the P channel region 43, and therefore, the P well 4 is larger than the N well 5. Then, the P-channel MOS semiconductor device 1 shown in FIG.
1 and the MONOS type semiconductor device 35 can be manufactured.

Then, the bad oxide film 4 shown in FIG.
6, a silicon nitride film is formed on the entire surface by chemical vapor deposition (hereinafter referred to as "CVD") at a temperature of 740 ° C. using a gas of dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). The nitride film 47 has a thickness of 120 n.
m.

Thereafter, a photoresist, which is a photosensitive resin, is formed on the entire surface of the nitride film 47, and is exposed and developed using a predetermined photomask, and as shown in FIG. A photoresist 112 is formed so as to open a field region.

Then, using the photoresist 112 as an etching mask, the nitride film 47 is etched. The etching of the nitride film 47 is performed by a dry etching method using a mixed gas of SF ₆ , CHF ₃ and He.

Then, the field region around the element region is oxidized by using the oxidation-resistant film of the nitride film 47 as a mask, that is, as shown in FIG. It is formed with. This selective oxidation treatment is performed by performing oxidation treatment at a temperature of 1000 ° C. in a steam oxidation atmosphere.

Next, hot phosphoric acid (H ₃ H) heated to 180 ° C.
Using PO ₄ ), the nitride film 47 is removed, and the pad oxide film 46 is removed by etching with a hydrofluoric acid buffer. FIG. 34 shows a state after the removal.

Thereafter, an oxidation process is performed in a mixed gas of oxygen and nitrogen to form a gate oxide film 2 made of a silicon dioxide film having a thickness of about 10 nm on the N channel region of the semiconductor substrate 1 as shown in FIG. 42 and P channel region 43
Formed over the entire surface of the substrate. Then, a gate silicon nitride film 61 made of a silicon nitride film is formed on the entire surface of the semiconductor substrate 1 including the gate oxide film 2 by a CVD method to a thickness of about 5 nm.

The gate silicon nitride film 61 is formed by a CVD method at a temperature of 700 ° C. using a gas of dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). The two-layer film of the gate silicon nitride film 61 and the gate oxide film 2 forms a gate insulating film 62. Thereafter, using a gas of monosilane (SiH ₄ ), a temperature of 600
A first film made of a polycrystalline silicon film by a CVD method
Is formed over the entire surface with a thickness of about 450 nm.

Next, a photoresist is formed on the entire surface of the first gate electrode material 48, and exposure and development are performed using a predetermined photomask, so that the photoresist is formed in a region where a gate electrode of a pair of MOS semiconductor devices is formed. Then, a photoresist 113 is patterned as shown in FIG. And
Using the photoresist 113 as an etching mask, the first gate electrode material 48 and the gate silicon nitride film 61 are etched by a dry etching method using a mixed gas of SF ₆ and O ₂ as an etching gas. As shown at 36, a pair of gate electrodes 3 is formed.

Further, the gate oxide film 2 matched with the gate electrode 3 is removed. The etching of the gate oxide film 2 is performed using a hydrofluoric acid buffer. After that, the photoresist 113 is removed.

As a result, the gate insulating film 62 composed of a two-layer film of the gate oxide film 2 and the gate silicon nitride film 61 formed on the semiconductor substrate 1 and the first gate formed on the gate insulating film 62 As shown in FIG. 36, the electrode material 48 is formed on the N channel region 42 and the M
The portion is removed except for a portion constituting the OS semiconductor device (a portion having the gate electrode 3).

Next, an oxidation process is performed in a mixed gas of oxygen and nitrogen to form a memory oxide film 31 made of silicon dioxide having a thickness of about 2.2 nm, as shown in FIG. Formed over the entire surface. Further, the memory oxide film 31 is subjected to a nitriding treatment in an ammonia (NH ₃ ) atmosphere at a temperature of 950 ° C., to make the memory oxide film 31 a silicon nitride oxide film.

This nitriding process is performed to increase the data write / erase characteristics of the MONOS type semiconductor device which is a nonvolatile memory device. During the nitriding process, there has been a problem that highly reactive NH ₃ and H ₂ diffuse into the gate oxide film of the MOS type semiconductor device to generate positive charges. However, in this embodiment, the gate insulating film 6
Due to the configuration 2 with two-layered film of the gate silicon nitride film 61 is dense film as a gate oxide film 2, NH ₃ or H ₂
Can be suppressed, and the generation of positive charges can be suppressed.

Next, a memory nitride film 32 made of a silicon nitride film is formed on the entire surface including the memory oxide film 31 by a CVD method to a thickness of about 12 nm. This memory nitride film 32 is formed by dichlorosilane (SiH ₂ Cl ₂ ).
At a temperature of 70 using a mixed gas of water and ammonia (NH ₃ ).
It is formed at 0 ° C. by a CVD method.

Further, an oxidation treatment is performed in a steam oxidation atmosphere at a temperature of 950 ° C. to oxidize the memory nitride film 32 and form a top oxide film 33 made of a silicon dioxide film on the memory nitride film 32. By this oxidation treatment, the thickness of the memory nitride film 32 becomes about 9 nm, and the top oxide film 3
The film thickness of No. 3 is about 4 nm.

Next, a second gate electrode material 49 made of polycrystalline silicon is formed on the entire surface by a CVD method at a temperature of 600 ° C. using a gas of monosilane (SiH ₄ ) at a thickness of about 450 nm. Thereafter, a photoresist is formed on the entire surface, and exposure and development are performed using a predetermined photomask, and a photoresist 114 is patterned in a region where a memory gate electrode of the MONOS type semiconductor device is to be formed as shown in FIG. Form.

Then, using the photoresist 114 as an etching mask, the polycrystalline silicon film as the second gate electrode material 49 is etched by a dry etching method using a mixed gas of SF ₆ and O ₂ as an etching gas. The memory gate electrode 50 shown in FIG. 38 is formed.

Next, similarly, using the photoresist 114 as an etching mask, the top oxide film 33, the memory nitride film 32, and the memory oxide film 31 are removed using CF ₄ , He, and CBr _3.
Etching is performed by a dry etching method using a mixed gas of O ₂ and O ₂ as an etching gas. After that, the photoresist 114 used as the etching mask is removed.

Further, a photoresist is formed on the entire surface of the semiconductor substrate 1, exposed and developed using a predetermined photomask, and a photoresist 115 is pattern-formed so as to open the N-channel region 42. Using the photoresist 115 as a mask for ion implantation, arsenic, an N-type impurity, is implanted with an acceleration energy of 60 KeV and an ion implantation amount of 3.0 × 10 ¹⁵ atoms.
/ Cm ² , ions are implanted into the P well 4 in the N channel region 42. After that, the photoresist 115 is removed.

Although not shown, a photoresist is again formed on the entire surface of the semiconductor substrate 1, exposure and development are performed using a predetermined photomask, and a photoresist is formed so as to open the P channel region 43. . Using this photoresist as a mask for ion implantation, boron as a P-type impurity is ion-implanted at an acceleration energy of 40 KeV and an ion implantation amount of about 3.0 × 10 ¹⁵ atoms / cm ² . After that, the photoresist is removed.

Next, as shown in FIG. 39, an interlayer insulating film 8 mainly composed of a silicon dioxide film is formed on the entire surface. Thereafter, a heat treatment at a temperature of 900 ° C. is performed in a nitrogen atmosphere for both activation of the ion-implanted impurities and reflow of the interlayer insulating film 8.

As a result, the source 6 and the drains (sources) 7 and 18 of the N-channel type MOS semiconductor device 11 and the MONOS type semiconductor device 35 composed of the N-type high concentration impurity layer are formed.
Then, the source 16 and the drain 17 of the P-type high-concentration impurity layer of the P-channel type MOS semiconductor device 12 can be formed.

Next, although not shown, the interlayer insulating film 8
A photoresist for opening the contact hole 9 is patterned on the upper surface. Then, using the photoresist as an etching mask, the interlayer insulating film 8 is etched, and as shown in FIG.
The contact holes 9 are provided at positions corresponding to the gates 3 and 50, the sources 6 and 16, and the drains 7, 17 and 18 of FIG.

The etching process for forming the contact hole 9 is performed by a dry etching method using a mixed gas of C ₂ F ₆ , He and CHF ₃ as an etching gas. After that, the photoresist is removed.

Next, a wiring material mainly composed of aluminum is provided on the entire surface of the interlayer insulating film 8 (including the inside of the contact hole 9), and a photoresist for forming wiring is patterned on the wiring material. Then, using the photoresist as a mask, the wiring material is etched,
Each wiring 10 shown in FIG. 3 is provided.

This wiring material is etched by a dry etching method using a mixed gas of BCl ₃ , CHCl ₃ , Cl ₂ and N ₂ as an etching gas. Thereby, the N-channel MOS semiconductor device 11 shown in FIG.
, P-channel type MOS semiconductor device 12 and MONOS
A semiconductor device in which the mold semiconductor device 35 and the semiconductor device 35 are provided on the same semiconductor substrate 1 is completed.

[Fourth Embodiment of Manufacturing Method: FIGS. 41 to 5]
0 and FIG. 4] Next, a method of manufacturing the semiconductor device (fourth embodiment) according to the present invention described with reference to FIG. 4 will be described as a fourth embodiment of the manufacturing method. 41 to 50
FIG. 2 is a schematic cross-sectional view showing a semiconductor device or its material in each step of the manufacturing method. Using these drawings and FIG. 4 showing a completed state, a fourth method of manufacturing a semiconductor device will be described.
An embodiment will be described.

This semiconductor device, as shown in FIG.
S composed of a supporting substrate 20, an insulating film 21, and a semiconductor layer 22
An OI substrate 23 is used. Photoresist is formed on the entire surface of the SOI substrate 23, exposure processing and development processing are performed using a predetermined photomask, and an N-channel region 42 for forming an N-channel type MOS semiconductor device;
As shown in FIG. 41, a photoresist 120 is pattern-formed on a P-channel region 43 which is a region where a channel type MOS semiconductor device is formed and on a MONOS region 35a where a MONOS type semiconductor device is formed.

Using this photoresist 120 as an etching mask, the semiconductor layer 22 is etched, and FIG.
As shown in FIG. 7, the island-shaped first semiconductor layer 22a is formed in the N-channel region 42, the island-shaped second semiconductor layer 22b is formed in the P-channel region 43, and the island-shaped third semiconductor layer 22c is formed in the MONOS region 35a. Leave each part and remove the other parts. The etching of the semiconductor layer 22 is performed by a dry etching method using a mixed gas of SF ₆ and O ₂ as an etching gas. After that, the photoresist 120 used as the etching mask is removed.

Next, an oxidation treatment is performed in a mixed gas of oxygen and nitrogen to form a gate oxide film 2 made of a silicon dioxide film having a thickness of about 10 nm shown in FIG. , 22c. After that, a photoresist is formed on the entire surface of the SOI substrate,
Exposure and development processing are performed using a predetermined photomask, and as shown in FIG.
The photoresist 121 is opened so as to open the S region 35a.
Is patterned.

Using this photoresist 121 as a mask, boron, which is a P-type impurity, is implanted with an acceleration energy of 25 KeV and an ion implantation amount of 2.0 × 10 ¹³ atoms.
At about s / cm ² , ions are implanted into the first semiconductor layer 22a and the third semiconductor layer 22c. After that, the photoresist 121 used as the mask is removed.

Thereafter, a photoresist is again formed on the entire surface of the SOI substrate, and exposure and development are performed using a predetermined photomask, and as shown in FIG. Resist 122
Is patterned. Then, this photoresist 12
2 as a mask, phosphorus as an N-type impurity is
Acceleration energy 30 KeV, ion implantation amount 8.0 × 10
^At about ¹² atoms / cm ² , ions are implanted into the second semiconductor layer 22b. After that, the photoresist 122 is removed.

Next, a photoresist is formed again on the entire surface of the SOI substrate, and exposure and development are performed using a predetermined photomask. As shown in FIG. 45, the first semiconductor layer in the N-channel region 42 is formed. 22a and MON
Photoresist 123 is patterned to open both ends of third semiconductor layer 22c in OS region 35a.

Then, using this photoresist 123 as a mask, boron as a P-type impurity is implanted with an acceleration energy of 25 KeV and an ion implantation amount of 6.0 × 10 ¹³ atoms.
/ Cm ² at both ends of the first semiconductor layer 22a and both ends of the third semiconductor layer 22c. After that, the photoresist 123 used as the mask is removed.

Next, a photoresist is formed again on the entire surface of the SOI substrate, and exposure and development are performed using a predetermined photomask. As shown in FIG. 46, the second semiconductor layer in the P-channel region 43 is formed. A photoresist 124 is patterned so as to open both ends of 22b.

Using this photoresist 124 as a mask, phosphorus as an N-type impurity is implanted at an acceleration energy of 30 KeV and an ion implantation amount of 2.0 × 10 ¹³ atoms / c.
At about m ² , ions are implanted into both ends of the second semiconductor layer 22b. After that, the photoresist 124 is removed.

As described above, each of the semiconductor layers 22a, 22b,
By performing ion implantation at the ends of
The threshold voltage of the parasitic MOS formed in this portion can be increased, and the involvement of the parasitic MOS can be prevented.

Thereafter, each of the semiconductor layers 22a, 22b, 22
4C, the entire surface of the gate oxide film 2 formed on the entire surface of FIG.
7, a gate silicon nitride film 61 made of a silicon nitride film is formed with a thickness of about 5 nm. This gate silicon nitride film 61 is formed by dichlorosilane (SiH ₂ C).
l ₂ ) and ammonia (NH ₃ ) gas at a temperature of 70
This is performed at 0 ° C. by a CVD method.

A gate insulating film 62 is constituted by a two-layer film of the gate silicon nitride film 61 and the gate oxide film 2.

Thereafter, using a monosilane (SiH ₄ ) gas at a temperature of 600 ° C. by a CVD method, as shown in FIG. 47, a first gate electrode material 48 made of a polycrystalline silicon film is formed to a thickness of about 450 nm. To form the entire surface.

Next, a photoresist is formed on the entire surface of the first gate electrode material 48, exposure and development are performed using a predetermined photomask, and a pair of MOS semiconductors are formed as shown in FIG. Photoresist 125 is patterned only on the region where each gate electrode of the device is to be formed.

Then, using the photoresist 125 as an etching mask, the gate electrode material 48 and the gate silicon nitride film 61 are etched by a dry etching method using a mixed gas of SF ₆ and O ₂ as an etching gas. A pair of gate electrodes 3 and 3 shown in FIG. 48 are formed.

Thereafter, the gate oxide film 2 other than the portion aligned under each gate electrode 3 is removed. The etching of the gate oxide film 2 is performed using a hydrofluoric acid buffer. After that, the photoresist 125 is removed.

As a result, a gate insulating film 62 composed of a two-layer film of the gate oxide film 2 and the gate silicon nitride film 61 formed on the first semiconductor layer 22a and the second semiconductor layer 22b, respectively, The gate electrode 3 formed on the gate insulating film 62 forms a pair of MOS type semiconductor devices.

Next, an oxidation process is performed in a mixed gas of oxygen and nitrogen to form a memory oxide film 31 made of silicon dioxide having a thickness of about 2.2 nm on the entire surface as shown in FIG. Further, the memory oxide film 31 is heated to a temperature of 950.
A nitridation process is performed in an ammonia (NH ₃ ) atmosphere at a temperature of 0 ° C., and the memory oxide film 31 is changed to a silicon nitride oxide film.

This nitriding process is performed to speed up the data write / erase characteristics of the MONOS type semiconductor device which is a nonvolatile memory device. During the nitriding process, highly reactive NH ₃ and H ₂ diffuse into the gate oxide film of the MOS type semiconductor device and generate a positive charge, which has been a problem. However, in the manufacturing method of the present invention, the gate insulating film 62
Is composed of a two-layer film of the gate oxide film 2 and the dense gate silicon nitride film 61, the diffusion of NH ₃ and H ₂ can be suppressed, and the generation of positive charges can be suppressed. it can.

Next, a memory nitride film 32 of a silicon nitride film is formed on the entire surface including the memory oxide film 31 by a CVD method to a thickness of about 12 nm. This memory nitride film 32 is formed by dichlorosilane (SiH ₂ Cl ₂ ).
Temperature of 700 ° C. using a gas of hydrogen and ammonia (NH ₃ )
By the CVD method.

Further, an oxidation treatment is performed in a steam oxidation atmosphere at a temperature of 950 ° C. to oxidize the memory nitride film 32 and form a top oxide film 33 made of a silicon dioxide film on the memory nitride film 32. By this oxidation treatment, the thickness of the memory nitride film 32 becomes about 9 nm, and the top oxide film 3
The film thickness of No. 3 is about 4 nm.

Next, using a monosilane (SiH ₄ ) gas at a temperature of 600 ° C. by a CVD method, as shown in FIG. 48, a second gate electrode material 49 made of polycrystalline silicon is deposited to a thickness of about 450 nm. To form the entire surface.

Thereafter, although not shown, a photoresist is formed on the entire surface of the second gate electrode material 49, exposure and development are performed using a predetermined photomask, and the memory of the MONOS type semiconductor device is formed. A photoresist is patterned only in a region where a gate electrode is to be formed.

Then, using the photoresist as an etching mask, the polycrystalline silicon film as the second gate electrode material 49 is etched by a dry etching method using a mixed gas of SF ₆ and O ₂ as an etching gas. The memory gate electrode 50 shown in FIG. 49 is formed.

Next, similarly, using the photoresist as an etching mask, the top oxide film 33, the memory nitride film 32, and the memory oxide film 31 are removed using CF ₄ , He, and CBr _3.
And a mixed gas of O ₂ is etched by a dry etching method is used as an etching gas, as shown in FIG. 49, to remove any portions other than the portion to be aligned under the memory gate electrode 50. After that, the photoresist used as the etching mask is removed.

Next, a photoresist is formed on the entire surface of the SOI substrate, and exposure and development are performed using a predetermined photomask. As shown in FIG. 49, the N channel region 42 and the MONOS region 35a are opened. The photoresist 127 is patterned so as to perform the above.

Then, using this photoresist 127 as a mask for ion implantation, arsenic, which is an N-type impurity, is implanted with an acceleration energy of 60 KeV and an ion implantation amount of about 3.0 × 10 ¹⁵ atoms / cm ² . First semiconductor layer 22
a and the exposed portions of the third semiconductor layer 22c are implanted. After that, the photoresist 127 is removed.

Thereafter, although not shown, this SO
A photoresist is formed on the entire surface of the I-substrate, exposed and developed using a predetermined photomask, and the photoresist is patterned so as to open the P-channel region 43.

Then, using the photoresist as a mask for ion implantation, boron as a P-type impurity is accelerated at an energy of 40 KeV and an ion implantation amount of 3.
At about 0 × 10 ¹⁵ atoms / cm ² , ions are implanted into the exposed portion of the second semiconductor layer 22b. After that, the photoresist used for the mask is removed.

Next, after an interlayer insulating film 8 mainly composed of a silicon dioxide film shown in FIG. 50 is formed over the entire surface, the activation of the ion-implanted impurities and the reflow of the interlayer insulating film 8 are performed. A heat treatment at a temperature of 900 ° C. is performed. As a result, the N-channel type MOS semiconductor device 11 and the MONO
Sources 6 and 26 and drains 7 and 27 each of which is an N-type high-concentration impurity layer of the S-type semiconductor device 35, and a source 16 and a drain 17 which each include a P-type high-concentration impurity layer of the P-channel MOS semiconductor device 12 Can be formed.

Thereafter, a photoresist for forming a contact hole 9 in the interlayer insulating film 8 is patterned on the interlayer insulating film 8. Then, using the photoresist as an etching mask, the interlayer insulating film 8 is etched to correspond to the gates 3, 50, the sources 6, 16, 26, and the drains 7, 17, 27 of the semiconductor devices 11, 12, 35, respectively. A contact hole 9 is formed at a position where the contact hole 9 is to be formed.

The etching process for forming the contact hole 9 is performed by a dry etching method using a mixed gas of C ₂ F ₆ , He and CHF ₃ as an etching gas. After that, the photoresist used as the etching mask is removed.

Next, a wiring material mainly composed of aluminum is provided on the entire surface of the interlayer insulating film 8 (including the inside of the contact hole 9), and a photoresist for forming wiring is patterned on the upper surface.

Then, using the photoresist as a mask, the wiring material is etched to form each wiring 10 shown in FIG.
Is provided. This wiring material is etched by BCl ₃ and C
Dry etching is performed using a mixed gas of HCl ₃ , Cl _2, and N ₂ as an etching gas. Thereby, the N-channel MOS semiconductor device 11 shown in FIG.
, P-channel type MOS semiconductor device 12 and MONOS
The semiconductor device provided with the mold semiconductor device 35 on the SOI substrate 23 is completed.

[Fifth Embodiment of Manufacturing Method: FIGS. 51 to 5]
6 and FIG. 5] Next, a method of manufacturing the semiconductor device (fifth embodiment) according to the present invention described with reference to FIG. 5 will be described as a fifth embodiment of the manufacturing method. 51 to 56
FIG. 2 is a schematic cross-sectional view showing a semiconductor device or its material in each step of the manufacturing method. Using these drawings and FIG. 5 showing a completed state, a fifth method of manufacturing the semiconductor device will be described.
An embodiment will be described.

In the method of manufacturing a semiconductor device according to the fifth embodiment, a semiconductor substrate is used. Then, as shown in FIG. 51, the P well 4 is formed in the N channel region 42 of the semiconductor substrate 1.
After the N well 5 is formed in the P channel region 43, a process up to forming a field oxide film 13 by forming a silicon nitride film on the surface thereof and performing a selective oxidation process using the silicon nitride film as a mask is described in the first embodiment of the manufacturing method. This is the same as the steps described with reference to FIGS. 7 to 12 in the embodiment.

In this embodiment, the oxidation treatment is performed in the mixed gas of oxygen and nitrogen from the state shown in FIG.
As shown in FIG. 1, a gate oxide film 2 made of a silicon dioxide film having a thickness of about 10 nm is formed on the entire surface of the N channel region 42 and the P channel region 43. Thereafter, a gate silicon nitride film 61 made of a silicon nitride film is formed on the entire surface of the gate oxide film 2 by a CVD method to a thickness of about 5 nm. The gate silicon nitride film 61 is formed by dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (N
H ₃ ) gas is used at a temperature of 700 ° C. by a CVD method.

Next, a photoresist is formed on the entire surface of the gate silicon nitride film 61, and is exposed and developed using a predetermined photomask, and as shown in FIG. Resist 13
3 is patterned. And this photoresist 1
The gate silicon nitride film 61 is etched using 33 as an etching mask. The etching of the gate silicon nitride film 61 is performed by a dry etching method using a mixed gas of SF ₆ , CHF ₃ and He. afterwards,
The photoresist 133 is removed.

As a result, as shown in FIG. 53, gate silicon nitride film 61 in N channel region 42 is removed, leaving only gate oxide film 2. Therefore, the gate insulating film 62 in the N-channel region 42 is composed of only the gate oxide film 2, and the gate insulating film 62 in the P-channel region 43 is composed of the two-layer film of the gate oxide film 2 and the gate silicon nitride film 61. Will be.

Thereafter, a gate electrode material 48 made of a polycrystalline silicon film is formed on the entire surface by a CVD method at a temperature of 600 ° C. using a monosilane (SiH ₄ ) gas at a thickness of about 450 nm. Next, the gate electrode material 4
Photoresist is formed on the entire surface on the substrate 8, and exposure and development are performed using a predetermined photomask, and a photoresist 134 (FIG. 53) is pattern-formed only in a region where each gate electrode of the pair of MOS semiconductor devices is formed. .

Then, using the photoresist 134 as an etching mask, the gate electrode material 48 and the gate silicon nitride film 61 are etched by a dry etching method using a mixed gas of SF ₆ and O ₂ as an etching gas. After that, the photoresist 134 used as the etching mask is removed.

As a result, as shown in FIG. 54, in the P channel region 43, a gate insulating film 62 composed of a two-layer film of the gate oxide film 2 and the gate silicon nitride film 61 provided on the semiconductor substrate 1 is formed. The gate electrode 3 provided on the gate insulating film 62 constitutes a MOS type semiconductor device. In the N-channel region 42, the MOS type semiconductor device is constituted by the gate oxide film 2 provided on the semiconductor substrate 1 and the gate electrode 3. Constitute.

Thereafter, a photoresist is formed on the entire surface of the semiconductor substrate 1 and exposed and developed using a predetermined photomask to form a photoresist 135 for opening the N-channel region 42 as shown in FIG. Is patterned.

Then, using this photoresist 135 as a mask for ion implantation, arsenic, which is an N-type impurity, has an acceleration energy of 60 KeV and an ion implantation amount of 3.
At about 0 × 10 ¹⁵ atoms / cm ² , the P
Ions are implanted into well 4. Then, photoresist 1
35 is removed.

Next, a photoresist is formed again on the entire surface of the semiconductor substrate 1, and exposure and development are performed using a predetermined photomask, and a photoresist 136 for opening the P channel region 43 is formed as shown in FIG. Form a pattern.

Then, using this photoresist 136 as a mask for ion implantation, boron as a P-type impurity is accelerated at an energy of 40 KeV and an ion implantation amount of 3.
At about 0 × 10 ¹⁵ atoms / cm ² , the N
Ions are implanted into well 5. After that, the photoresist is removed.

Thereafter, in the first embodiment, FIG.
In the same manner as described with reference to FIG. 18, an interlayer insulating film mainly composed of a silicon dioxide film is formed on the entire surface of semiconductor substrate 1 to activate the ion-implanted impurities and reflow the interlayer insulating film. 900 ° C in a nitrogen atmosphere
Is performed. As a result, the source 6 and the drain 7 composed of the N-type high-concentration impurity layer of the N-channel type MOS semiconductor device 11 shown in FIG. 16 and the drain 17 can be formed.

Thereafter, a contact hole 9 is formed in the interlayer insulating film 8, and each wiring 10 is formed therefrom using a wiring material mainly composed of aluminum. Thus, a semiconductor device in which the N-channel MOS semiconductor device 11 and the P-channel MOS semiconductor device 12 shown in FIG. 5 are provided on the same semiconductor substrate 1 is completed.

[Sixth Embodiment of Manufacturing Method: FIGS. 57 to 6]
6 and FIG. 6] Next, a method of manufacturing the semiconductor device (sixth embodiment) according to the present invention described with reference to FIG. 6 will be described as a sixth embodiment of the manufacturing method. FIGS. 57 to 66
FIG. 2 is a schematic cross-sectional view showing a semiconductor device or its material in each step of the manufacturing method. Using these drawings and FIG. 6 showing a completed state, a sixth method of manufacturing a semiconductor device will be described.
An embodiment will be described.

In this embodiment, as in the second embodiment, an SOI substrate 23 composed of a support substrate 20, an insulating plate 21, and a semiconductor layer 22 is used. Then, a photoresist 140 is patterned on the SOI substrate as shown in FIG. 57, and the semiconductor layer 22 is etched using the photoresist 140 as an etching mask. Thus, the island-shaped first semiconductor layer 22a of the N-channel region 42 and the island-shaped second semiconductor layer 22b of the P-channel region 43 are formed on the insulating plate 21.

Thereafter, gate oxide film 2 is formed on the entire surface of each of semiconductor layers 22a and 22b. Then, as shown in FIG. 58, a photoresist 141 having an opening in the N-channel region 42 is formed by patterning.
Is used as a mask, boron as an N-type impurity is ion-implanted into the first semiconductor layer 22a. Similarly, as shown in FIG. 59, the photoresist 14 opening the P-channel region 43 is formed.
Is used as a mask, and phosphorus, which is a P-type impurity, is ion-implanted into the second semiconductor layer 22b using the mask as a mask.

Further, as shown in FIG. 60, a photoresist 143 is formed in a pattern, and boron, which is an N-type impurity, is ion-implanted again into the N-channel region. Thus, an inversion preventing impurity layer is formed in the first semiconductor layer 22a. Further, as shown in FIG.
Is formed, and boron, which is a P-type impurity, is ion-implanted again into the P-channel region. Thereby, the second
An impurity layer for preventing inversion is formed in the semiconductor layer 22b. These steps are the same as the steps described in the second embodiment with reference to FIGS. 19 to 24, and thus detailed description thereof will be omitted.

Thereafter, as shown in FIG. 62, a gate silicon nitride film 61 made of a silicon nitride film is formed on the entire surface of the gate oxide film 2 by CVD at a thickness of about 5 nm. This gate silicon nitride film 61 is formed by a CVD method at a temperature of 700 ° C. using a gas of dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ).

Next, a photoresist, which is a photosensitive resin, is formed on the entire surface, exposed and developed using a predetermined photomask, and a photoresist 145 is patterned to open the N-channel region. afterwards,
Using this photoresist 145 as an etching mask,
The gate silicon nitride film 61 is etched. This gate silicon nitride film 61 is etched by SF ₆ and C
Etching is performed by a dry etching method using a mixed gas of HF ₃ and He. Then, this photoresist 1
Remove 45.

Thus, the gate insulating film of N channel region 42 is constituted only by gate oxide film 2, and gate insulating film 62 of P channel region 43 is formed of a two-layer film of gate oxide film 2 and gate silicon nitride film 61. Will be configured.

Next, as shown in FIG.
CVD at a temperature of 600 ° C. using a reaction gas of (SiH ₄ )
A gate electrode material 48 made of a polycrystalline silicon film is formed on the entire surface by a method with a thickness of about 450 nm.

Further, a photoresist is formed on the entire surface of the gate electrode material 48, exposure processing and development processing are performed using a predetermined photomask, and the photoresist is formed only in a region where a gate electrode of a pair of MOS semiconductor devices is formed. 1
46 is patterned.

Then, using the photoresist 146 as an etching mask, the gate electrode material 48 and the gate silicon nitride film 61 are etched by a dry etching method using a mixed gas of SF ₆ and O ₂ as an etching gas. After that, the photoresist 146 is removed.

As a result, as shown in FIG. 64, in the P channel region 43, a gate insulating film 62 composed of a two-layer film of the gate oxide film 2 and the gate silicon nitride film 61 provided on the semiconductor layer 22b, A MOS type semiconductor device is constituted by the gate electrode 3 provided on the gate insulating film 62 and N
In the channel region 42, a MOS type semiconductor device is constituted by the gate oxide film 2 and the gate electrode 3 provided on the semiconductor layer 22a.

Next, a photoresist is formed on the entire surface of the SOI substrate, and exposure and development are performed using a predetermined photomask. As shown in FIG. 65, a photoresist 147 for opening the N-channel region 42 is formed. Form a pattern.

Using this photoresist 147 as a mask for ion implantation, arsenic, which is an N-type impurity, is implanted with an acceleration energy of 40 KeV and an ion implantation amount of 3.0.
At about × 10 ¹⁵ atoms / cm ² , ions are implanted into the exposed portion of the first semiconductor layer 22a. Then, the photoresist 14
7 is removed.

Thereafter, although not shown, this SO
A photoresist is formed on the entire surface of the I-substrate, exposed and developed using a predetermined photomask, and the photoresist is patterned so as to open the P-channel region 43.

Then, using the photoresist as a mask for ion implantation, boron as a P-type impurity is
Acceleration energy 30 KeV, ion implantation amount 3.0 × 10
^At about ¹⁵ atoms / cm ² , ions are implanted into the exposed portion of the second semiconductor layer 22b. After that, the photoresist is removed.

Next, as shown in FIG. 66, an interlayer insulating film 8 mainly composed of a silicon dioxide film is formed on the entire surface. Then, at a temperature of 900 in a nitrogen atmosphere, the activation of the ion-implanted impurities and the reflow of the interlayer insulating film 8 are performed.
A heat treatment at ℃ is performed. As a result, the N channel type source 6 made of the N type high concentration impurity layer of the MOS semiconductor device 11 is used.
, Drain 7 and P-channel type MOS semiconductor device 12
The source 16 and the drain 17 composed of the P type high concentration impurity layer can be formed.

Thereafter, the contact hole 9 shown in FIG. 6 is formed in the interlayer insulating film 8, and each wiring 10 made of a wiring material mainly composed of aluminum is formed therein, thereby forming the N-channel MOS semiconductor device shown in FIG. 11 and P channel MOS
A semiconductor device in which the semiconductor device 12 and the semiconductor device 12 are provided on the same SOI substrate 23 is completed.

[Description with Characteristic Diagram] When the semiconductor device according to the present invention described above is used in a radiation environment,
The change in threshold voltage will be described with reference to the characteristic diagram of FIG. Figure 67
Shows a comparison between a case where the semiconductor device of the present invention and a conventional semiconductor device are used in a radiation irradiation environment, and shows a change in threshold voltage when each semiconductor device is irradiated with gamma rays.

The horizontal axis of FIG. 67 indicates the thickness of the gate insulating film, and the vertical axis indicates the amount of change in threshold voltage when gamma rays are irradiated with 1 × 10 ⁷ RAD. In the figure, the triangles and triangles indicate the measurement results in the case of a conventional semiconductor device in which the gate insulating film is constituted only by the gate oxide film, the triangle indicates the characteristics of the N-channel MOS semiconductor device, and the triangle indicates the characteristics of the P-channel MOS semiconductor device. Channel type M
The characteristics of the OS semiconductor device are shown.

○ and ● show the measurement results in the case of the semiconductor device according to the present invention. Similarly, ● shows the characteristics of the N channel type MOS semiconductor device, and ○ shows the P channel type MO semiconductor device.
5 shows characteristics of an S semiconductor device. The change in the threshold voltage increases as the thickness of the gate insulating film increases, because the amount of positive charges generated by gamma ray irradiation increases.

In the case where the thickness of the gate insulating film is 15 nm, which is the result of the semiconductor device according to the present invention, the effect of suppressing the change in threshold voltage in the P-channel MOS semiconductor device is greater than that of the conventional device. I understand.

Therefore, as shown in the embodiment of the present invention, the gate insulating film of each of the N-channel type MOS semiconductor device and the P-channel type MOS semiconductor device is formed of a two-layer film of a gate oxide film and a gate silicon nitride film. The gate insulating film of the N-channel type MOS semiconductor device is constituted only by the gate oxide film, and the gate insulating film of the P-channel type MOS semiconductor device is composed of two layers of a gate oxide film and a gate silicon nitride film. It may be constituted by a film.

As a result, it is possible to suppress a change in the threshold voltage due to the generation of positive charges in a radiation environment. Further, when the N-channel MOS semiconductor device, the P-channel MOS semiconductor device and the MONOS type semiconductor device are formed on the same substrate, the semiconductor device according to the present invention can be formed by a heat treatment step in an ammonia atmosphere. A change in threshold voltage can also be suppressed.

The change in the threshold voltage due to the heat treatment in the ammonia atmosphere and the characteristics of the semiconductor device according to the present invention will be described with reference to the characteristic diagram of FIG. FIG. 68 shows the correlation between the gate voltage and the drain current of a P-channel type MOS semiconductor device.

The abscissa of FIG. 68 shows the gate voltage applied to the gate electrode of the P-channel MOS semiconductor device, and the ordinate shows the logarithm of the drain current flowing due to the gate voltage. The solid line in the figure shows the characteristics of the P-channel MOS semiconductor device according to the present invention, and the broken line shows the characteristics of the conventional P-channel MOS semiconductor device.

As shown in FIG. 68, in the conventional P-channel type MOS semiconductor device, the threshold voltage shifts to a higher value due to the heat treatment in an ammonia atmosphere in the course of manufacturing. This is because ammonia or hydrogen diffuses in the gate oxide film or at the interface between the gate oxide film and the semiconductor substrate due to the treatment in the ammonia atmosphere, and generates a positive charge by reacting.

On the other hand, the P-channel type M of the present invention
In the OS semiconductor device, the gate insulating film is composed of a two-layer film of a gate oxide film and a gate silicon nitride film. Therefore, the dense gate silicon nitride film reduces the diffusion of ammonia and hydrogen and suppresses the amount of positive charges generated. Therefore, the characteristics as designed can be obtained without a change in the threshold voltage.

[0254]

As described above, according to the semiconductor device and the method of manufacturing the same according to the present invention, the threshold voltage change under a radiation environment, which has been a problem in the semiconductor device using the semiconductor substrate and the SOI substrate, has been described. Can be suppressed, and stable characteristics can be obtained in a radiation environment.

Further, when the N-channel type MOS semiconductor device, the P-channel type MOS semiconductor device and the MONOS type semiconductor device are formed on the same semiconductor substrate or the same SOI substrate, the semiconductor device is subjected to a heat treatment in an ammonia atmosphere. A change in threshold voltage can also be suppressed.

That is, at least a P-channel type MOS
By forming the gate insulating film of a semiconductor device with a two-layer film of a gate oxide film and a gate silicon nitride film, the dense gate silicon nitride film reduces the diffusion of ammonia and hydrogen, and generates a positive charge. And a change in threshold voltage can be suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing the structure of a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a schematic sectional view showing a structure of a second embodiment of the semiconductor device according to the present invention;

FIG. 3 is a schematic sectional view showing the structure of a third embodiment of the semiconductor device according to the present invention.

FIG. 4 is a schematic sectional view showing the structure of a fourth embodiment of the semiconductor device according to the present invention;

FIG. 5 is a schematic sectional view showing the structure of a fifth embodiment of the semiconductor device according to the present invention.

FIG. 6 is a schematic sectional view showing the structure of a sixth embodiment of the semiconductor device according to the present invention.

FIG. 7 is a schematic sectional view showing a step of the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a schematic cross-sectional view showing a step of the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a schematic cross-sectional view showing a step in the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 10 shows a first method of manufacturing a semiconductor device according to the present invention.
It is a typical sectional view showing a process of an embodiment.

FIG. 11 is a first view illustrating a method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 12 is a first view illustrating a method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 13 is a first view illustrating a method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 14 is a first view illustrating a method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 15 is a first view illustrating a method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 16 shows a first example of a method of manufacturing a semiconductor device according to the present invention.
It is a typical sectional view showing a process of an embodiment.

FIG. 17 is a first view illustrating a method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 18 shows a first example of a method for manufacturing a semiconductor device according to the present invention.
It is a typical sectional view showing a process of an embodiment.

FIG. 19 is a second view illustrating the method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 20 is a view showing a second step of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 21 is a second view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 22 is a second view illustrating the method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 23 is a second view illustrating the method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 24 is a second view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 25 is a second view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 26 is a second view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 27 is a second view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 28 is a second view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 29 is a third view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 30 is a third view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 31 is a third view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 32 shows a third method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 33 is a third view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 34 shows a third method of manufacturing a semiconductor device according to the present invention.
It is a typical sectional view showing a process of an embodiment.

FIG. 35 is a third view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 36 shows a third method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 37 shows a third method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 38 shows a third method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 39 is a third view illustrating the method of manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 40 is a third view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 41 is a fourth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 42 is a fourth step of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 43 is a fourth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 44 is a fourth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 45 is a fourth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 46 is a fourth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 47 is a fourth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 48 is a fourth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 49 is a fourth step of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 50 is a fourth step of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 51 is a fifth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 52 is a fifth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 53 is a fifth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 54 is a fifth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 55 is a fifth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 56 is a fifth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 57 is a sixth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 58 is a sixth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 59 is a sixth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 60 is a sixth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 61 is a sixth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 62 is a sixth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 63 is a sixth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 64 is a sixth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 65 is a sixth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 66 is a sixth view of the method for manufacturing a semiconductor device according to the present invention;
It is a typical sectional view showing a process of an embodiment.

FIG. 67 is a diagram showing the correlation between the thickness of the gate insulating film of the present invention and the conventional N-channel type MOS semiconductor device and the conventional P-channel type MOS semiconductor device and the amount of change in the threshold voltage due to radiation irradiation.

FIG. 68 is a diagram showing a correlation between a gate voltage and a drain current of the present invention and a conventional P-channel type MOS semiconductor device.

FIG. 69 is a schematic sectional view showing an example of the structure of a conventional semiconductor device.

FIG. 70 is a schematic sectional view showing another example of the structure of the conventional semiconductor device.

FIG. 71 is a schematic sectional view showing still another example of the structure of the conventional semiconductor device.

FIG. 72 is a schematic cross-sectional view showing a step of a conventional semiconductor device manufacturing method for manufacturing the semiconductor device shown in FIG. 71.

FIG. 73 is a schematic cross-sectional view showing the next step in the same manner.

FIG. 74 is a schematic sectional view showing the next step in the same manner.

FIG. 75 is a schematic cross-sectional view showing the next step in the same manner.

FIG. 76 is a schematic cross-sectional view showing the next step in the same manner.

[Explanation of symbols]

 1: Semiconductor substrate 2: Gate oxide film 3: Gate electrode 4: P well 5: N well 6: Source of N channel MOS semiconductor device 7: Drain of N channel MOS semiconductor device 8: Interlayer insulating film 9: Contact hole 10: Wiring 11: N-channel type MOS semiconductor device 12: P-channel type MOS semiconductor device 13: Field oxide film 16: Source of P-channel type MOS semiconductor device 17: Drain of P-channel type MOS semiconductor device 18: Drain of MONOS type semiconductor device Reference Signs List 20: support base 21: insulating film 22: semiconductor layer 22a to 22c: first to third semiconductor layers 23: SOI substrate 26: source of MONOS type semiconductor device 27: drain of MONOS type semiconductor device 31: memory oxide film 32 : Memory nitride film 33: top oxide film 34: memory insulating film 35: ONOS type semiconductor device 35a: MONOS region 41: Oxidation 42: N-channel region 43: P-channel region 44: First buffer oxide film 45: Second buffer oxide film 48: First gate electrode material 49: Second Gate electrode material 46: pad oxide film 47: nitride film 50: memory gate electrode 61: gate silicon nitride film 62: gate insulating film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 627F

Claims (12)

[Claims] 1. An N-channel MOS semiconductor device and a P-channel MOS semiconductor device each having a semiconductor substrate, a gate insulating film provided on the semiconductor substrate, and a gate electrode provided on the gate insulating film. A semiconductor device, wherein the gate insulating film is formed of a two-layer film of a gate oxide film and a gate silicon nitride film made of a silicon dioxide film. 2. The semiconductor device according to claim 1, wherein a memory insulating film including a memory oxide film, a memory nitride film, and a top oxide film provided on the semiconductor substrate, and a memory provided on the memory insulating film. MONOS having gate electrode
A semiconductor device further comprising a semiconductor device. 3. An N-channel MOS semiconductor device and a P-channel MOS semiconductor device each having a semiconductor substrate, a gate insulating film provided on the semiconductor substrate, and a gate electrode provided on the gate insulating film. The gate insulating film of the N-channel MOS semiconductor device is constituted by a gate oxide film made of a silicon dioxide film, and the gate insulating film of the P-channel MOS semiconductor device is
A semiconductor device comprising a two-layer film of a gate oxide film and a gate silicon nitride film made of a silicon dioxide film. 4. An N-channel type including an SOI substrate including a supporting substrate, an insulating film, and an island-shaped semiconductor layer, a gate insulating film provided on the semiconductor layer, and a gate electrode provided on the gate insulating film. A semiconductor device comprising a MOS semiconductor device and a P-channel type MOS semiconductor device, wherein the gate insulating film is formed of a two-layer film of a gate oxide film and a gate silicon nitride film made of a silicon dioxide film. 5. The semiconductor device according to claim 4, wherein a memory insulating film including a memory oxide film, a memory nitride film, and a top oxide film provided on the semiconductor layer, and a memory provided on the memory insulating film. A semiconductor device further comprising a MONOS type semiconductor device having a gate electrode. 6. An N-channel type having an SOI substrate including a supporting substrate, an insulating film and an island-shaped semiconductor layer, a gate insulating film provided on the semiconductor layer, and a gate electrode provided on the gate insulating film. The semiconductor device includes a MOS semiconductor device and a P-channel type MOS semiconductor device.
The gate insulating film of the P-channel type MOS semiconductor device is constituted by a gate oxide film made of a silicon dioxide film.
A semiconductor device comprising a two-layer film of a gate oxide film and a gate silicon nitride film made of a silicon dioxide film. 7. A step of oxidizing a semiconductor substrate in an oxidizing atmosphere to form an oxide film on the entire surface of the semiconductor substrate; and forming an oxide film in an N-channel region for forming an N-channel MOS semiconductor device on the semiconductor substrate. Etching, forming a first buffer oxide film for introducing a P-type impurity into the N-channel region, and introducing a P-type impurity into the N-channel region of the semiconductor substrate; Forming a second buffer oxide film on the entire surface of the semiconductor substrate after etching the oxide film on the entire surface of the semiconductor substrate; and exposing a P-channel region on the semiconductor substrate to form a P-channel type MOS semiconductor device. N with a conductive resin as a mask
Forming a pad oxide film on the entire surface of the semiconductor substrate after etching the second buffer oxide film and activating each of the introduced impurities in an oxidizing atmosphere; Forming a nitride film made of a silicon nitride film on the pad oxide film; etching the nitride film in a region of the semiconductor substrate where a field oxide film is to be formed; Forming the field oxide film on the N channel region and separating the N channel region and the P channel region, and then removing the nitride film and the pad oxide film; Forming a gate oxide film on the entire surface of the region in an oxidizing atmosphere, forming a gate silicon nitride film on the entire surface of the gate oxide film; Forming a gate electrode material on the entire surface of the silicon nitride film, etching the gate electrode material and the gate silicon nitride film to form a gate electrode, and using a photosensitive resin as an ion implantation mask to form the semiconductor substrate. Forming an N-type high-concentration impurity layer in the source and drain formation regions in the N-channel region, and using a photosensitive resin as an ion implantation mask to form a source and drain formation region in the P-channel region of the semiconductor substrate Forming a P-type high-concentration impurity layer; forming an interlayer insulating film mainly composed of a silicon dioxide film over the entire surface of the semiconductor substrate; and heat-treating the N-type and P-type high-concentration impurity layers. Activating; and forming a plurality of contact holes in the interlayer insulating film by photo-etching; Forming a wiring connected to each gate electrode, source, and drain of the N-channel MOS semiconductor device and the P-channel MOS semiconductor device via a contact hole. . 8. A step of oxidizing a semiconductor substrate in an oxidizing atmosphere to form an oxide film on the entire surface of the semiconductor substrate; and forming the oxide film on an N-channel type MOS semiconductor device on the semiconductor substrate. Etching, forming a first buffer oxide film for introducing a P-type impurity into the N-channel region, and introducing a P-type impurity into the N-channel region of the semiconductor substrate; Forming a second buffer oxide film on the entire surface of the semiconductor substrate after etching the oxide film on the entire surface of the semiconductor substrate; and exposing a P-channel region on the semiconductor substrate to form a P-channel type MOS semiconductor device. N with a conductive resin as a mask
Introducing a mold impurity, etching the second buffer oxide film, activating each of the introduced impurities in an oxidizing atmosphere, and then forming a pad oxide film; and forming a pad oxide film on the pad oxide film. Forming a nitride film made of a silicon nitride film on the semiconductor substrate, etching a nitride film in a region of the semiconductor substrate where a field oxide film is to be formed, and forming the field oxide film on the semiconductor substrate by selective oxidation. Forming and isolating the N-channel region and the P-channel region, and then removing the nitride film and the pad oxide film; and forming an oxidizing atmosphere over the N-channel region and the P-channel region of the semiconductor substrate. Forming a gate oxide film therein and forming a gate silicon nitride film on the entire surface of the gate oxide film; Forming a first gate electrode material and forming a gate electrode by photoetching; oxidizing the entire surface of the semiconductor substrate in an oxidizing atmosphere to form a memory oxide film; Forming a nitride film on the oxide film; forming a memory nitride film on the memory oxide film; oxidizing the memory nitride film in an oxidizing atmosphere to form a top oxide film; Forming a second gate electrode material, etching the second gate electrode material, the top oxide film, the memory nitride film, and the memory oxide film by photo-etching to form a memory gate electrode; Forming an N-type high-concentration impurity layer in a source and drain formation region in an N-channel region of the semiconductor substrate using a resin as an ion implantation mask; Forming a P-type high-concentration impurity layer in a source and drain formation region in a P-channel region of the semiconductor substrate using a photosensitive resin as an ion implantation mask; and forming a silicon dioxide film on the entire surface of the semiconductor substrate. Forming an interlayer insulating film mainly composed of: a step of activating the N-type and P-type high-concentration impurity layers by heat treatment; and a step of forming a plurality of contact holes in the interlayer insulating film by photoetching. Through the contact hole, the N-channel MOS semiconductor device, the P-channel MOS semiconductor device and the MONOS
Forming wirings respectively connected to each gate electrode, source, and drain of the semiconductor device. 9. A step of oxidizing a semiconductor substrate in an oxidizing atmosphere to form an oxide film on the entire surface of the semiconductor substrate; and forming the oxide film in an N-channel region for forming an N-channel MOS semiconductor device on the semiconductor substrate Etching, forming a first buffer oxide film for introducing a P-type impurity into the N-channel region, and introducing a P-type impurity into the N-channel region of the semiconductor substrate; Forming a second buffer oxide film on the entire surface of the semiconductor substrate after etching the oxide film on the entire surface of the semiconductor substrate; and exposing a P-channel region on the semiconductor substrate to form a P-channel type MOS semiconductor device. N with a conductive resin as a mask
Forming a pad oxide film on the entire surface of the semiconductor substrate after etching the second buffer oxide film and activating each of the introduced impurities in an oxidizing atmosphere; Forming a nitride film made of a silicon nitride film on the pad oxide film; etching the nitride film in a region of the semiconductor substrate where a field oxide film is to be formed; Forming the field oxide film on the N channel region and separating the N channel region and the P channel region, and then removing the nitride film and the pad oxide film; Forming a gate oxide film in an oxidizing atmosphere over the entire surface of the region, forming a gate silicon nitride film over the entire surface of the gate oxide film; Removing the gate silicon nitride film so as to leave the gate silicon nitride film in the N-channel region by etching; forming a gate electrode material on the entire surface of the semiconductor substrate; and etching the gate electrode material. Forming a gate electrode; forming an N-type high-concentration impurity layer in a source and drain formation region in an N-channel region of the semiconductor substrate using the photosensitive resin as an ion implantation mask; Forming a P-type high-concentration impurity layer in a source and drain formation region in a P-channel region of the semiconductor substrate by using as an ion implantation mask; and forming a silicon dioxide film over the entire surface of the semiconductor substrate. Forming an interlayer insulating film; and activating the N-type and P-type high-concentration impurity layers by heat treatment. Forming a plurality of contact holes in the interlayer insulating film by photoetching; and, via the contact holes, respective gate electrodes, sources, and drains of an N-channel MOS semiconductor device and a P-channel MOS semiconductor device. Forming a wiring to be connected to each of the semiconductor devices. 10. An N-channel type, wherein a photosensitive resin is formed on a semiconductor layer of an SOI substrate including a supporting substrate, an insulating film, and a semiconductor layer, and the semiconductor layer is etched using the photosensitive resin as an etching mask. Forming a first island-shaped semiconductor layer forming a MOS semiconductor device and a second island-shaped semiconductor layer forming a P-channel MOS semiconductor device; and first and second semiconductor layers thereof Is oxidized in an oxidizing atmosphere,
Forming a gate oxide film on the surface of each of the semiconductor layers; forming a P-type channel impurity layer in the region of the first semiconductor layer using a photosensitive resin as an ion implantation mask; Forming an N-type channel impurity layer in the region of the second semiconductor layer by using as an ion implantation mask; and forming a P-type impurity in a boundary region of the first semiconductor layer by using a photosensitive resin as an ion implantation mask. Forming an N-type inversion prevention impurity layer in a boundary region of the second semiconductor layer using a photosensitive resin as an ion implantation mask; and forming a surface of each of the semiconductor layers. Forming a gate silicon nitride film on the gate oxide film, forming a gate electrode material on the gate silicon nitride film, and etching the gate electrode material and the gate silicon nitride film. And ring, and forming a gate electrode using a photosensitive resin as an ion implantation mask, the source and drain formation region in the first semiconductor layer, N
Forming a high-concentration impurity layer of a mold type; using a photosensitive resin as an ion implantation mask, forming P and P regions in the source and drain formation regions of the second semiconductor layer.
Forming an N-type and P-type high-concentration impurity layer by heat treatment; forming an interlayer insulating film mainly composed of a silicon dioxide film on the entire surface of the semiconductor layer; Forming a plurality of contact holes in the interlayer insulating film by photo-etching; and, through the contact holes, the gate electrode, the source, and the source electrode of the N-channel MOS semiconductor device and the P-channel MOS semiconductor device. Forming a wiring connected to the drain and the drain, respectively. 11. An N-channel type by forming a photosensitive resin on a semiconductor layer of an SOI substrate including a supporting substrate, an insulating film, and a semiconductor layer, and etching the semiconductor layer using the photosensitive resin as an etching mask. An island-shaped first semiconductor layer forming a MOS semiconductor device, an island-shaped second semiconductor layer forming a P-channel type MOS semiconductor device, and an island-shaped third semiconductor layer forming a MONOS type semiconductor device Forming a gate oxide film on a surface of each of the first to third semiconductor layers by oxidizing the first to third semiconductor layers in an oxidizing atmosphere; and using a photosensitive resin as an ion implantation mask. Forming a P-type channel impurity layer in a region of the first semiconductor layer and the third semiconductor layer; and using a photosensitive resin as an ion implantation mask, forming an N-type channel impurity region in a region of the second semiconductor layer. channel Forming an impurity layer, using a photosensitive resin as an ion implantation mask, forming a P-type inversion preventing impurity layer in a boundary region between the first semiconductor layer and the third semiconductor layer; Forming an N-type inversion-preventing impurity layer in a boundary region of the second semiconductor layer by using as an ion implantation mask; forming a gate silicon nitride film on the entire surface of the semiconductor substrate; Forming a first gate electrode material over the entire surface of the film and forming a gate electrode by photoetching; oxidizing the entire surface of the semiconductor substrate in an oxidizing atmosphere to form a memory oxide film; Heat-treating the memory oxide film into a nitrided oxide film, forming a memory nitride film on the memory oxide film, and oxidizing the memory nitride film in an oxidizing atmosphere to top Forming an oxide film, forming a second gate electrode material on the top oxide film, and etching the second gate electrode material, the top oxide film, the memory nitride film, and the memory oxide film by photoetching. Forming a memory gate electrode, and using the photosensitive resin as an ion implantation mask to form the first gate.
Forming an N-type high-concentration impurity layer in source and drain formation regions of the third semiconductor layer; and forming the second semiconductor layer using a photosensitive resin as an ion implantation mask.
In the source and drain formation regions in the semiconductor layer of
A step of forming a P-type high-concentration impurity layer, a step of forming an interlayer insulating film mainly composed of a silicon dioxide film over the entire surface of the semiconductor layer, and a step of heat-treating the N-type and P-type high-concentration impurity layers. Activating, forming a plurality of contact holes in the interlayer insulating film by photoetching, an N-channel MOS semiconductor device, a P-channel MOS semiconductor device, and an MO through the contact holes.
Forming a wiring connected to each of the gate electrode, source, and drain of the NOS type semiconductor device. 12. An N-channel MOS semiconductor, wherein a photosensitive resin is formed on a semiconductor layer of an SOI substrate including a support substrate, an insulating film, and a semiconductor layer, and the semiconductor layer is etched using the photosensitive resin as an etching mask. Forming an island-shaped first semiconductor layer forming a device and a second semiconductor layer forming a P-channel MOS semiconductor device; and oxidizing the first and second semiconductor layers in an oxidizing atmosphere. Forming a gate oxide film on the surface of each semiconductor layer; forming a P-type channel impurity layer in a region of the first semiconductor layer using a photosensitive resin as an ion implantation mask; Forming an N-type channel impurity layer in a region of the second semiconductor layer using a photosensitive resin as an ion implantation mask; and forming a boundary between the first semiconductor layer using a photosensitive resin as an ion implantation mask. Forming a P-type anti-inversion impurity layer in the region; forming an N-type anti-inversion impurity layer in a boundary region of the second semiconductor layer using a photosensitive resin as an ion implantation mask; Forming a gate silicon nitride film on the gate oxide film on the surface of the semiconductor layer, and leaving the gate silicon nitride film in the region of the first semiconductor layer by photoetching, and leaving the gate silicon nitride film in the other region Removing the nitride film, forming a gate electrode material over the entire surface of the semiconductor layer, etching the gate electrode material to form a gate electrode, using a photosensitive resin as an ion implantation mask, The first
N in the source and drain formation regions in the semiconductor layer of
Forming a high-concentration impurity layer of a mold; and using the photosensitive resin as an ion implantation mask,
P in the source and drain formation regions in the semiconductor layer
Forming an N-type and P-type high-concentration impurity layer by heat treatment; forming an interlayer insulating film mainly composed of a silicon dioxide film over the entire surface of the semiconductor layer; Forming a plurality of contact holes in the interlayer insulating film by photo-etching; and, via the contact holes, the gate electrode, source, and source electrode of the N-channel MOS semiconductor device and the P-channel MOS semiconductor device. Forming a wiring connected to the drain and the drain, respectively.