JPH0228381A - Manufacture of nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To surely restrain the contact between a high concentration impurity region and a source region or a drain region without being accompanied with alignment slippage allowance so as to micronize an element by selectively oxidizing a substrate after forming an opening by etching, and selectively introducing impurity into the substrate. CONSTITUTION:A first insulating film 27 and an oxidationresistant film 23 are formed in order on a substrate 21 and these are etched so as to form an opening 32, and then the substrate 21 is selectively oxidized so as to form a field oxide film 26, and this is etched so as to expose the substrate 21. And it is oxidized so as to form a gate insulating film 27, and a first polysilicon film 28 is formed on the field oxide film 26 and the gate insulating film 27, and an opening 33 is formed. Next, by selectively introducing impurity into the substrate 21 a high concentration impurity region is formed, and a second insulating film 29 and thereon a second polysilicon film 30 are formed. Hereby, diffusion of the high concentration impurity region by heat treatment can be softened, and the contact between the high concentration impurity region and the source region or the drain region can be suppressed surely without alignment slippage allowance, and the element micronization can be realized.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Background of the invention (Figures 3 and 4) Prior art (Figure 5) Problems to be solved by the invention Means and action for solving the problem Embodiment An embodiment of the present invention (FIGS. 1 and 2) Effects of the invention [Summary] Regarding a method of manufacturing a non-volatile semiconductor memory device, it is possible to form a high concentration impurity region and a source region or a drain region without any misalignment margin. The purpose of the present invention is to provide a method for manufacturing a non-volatile semiconductor memory device that can reliably suppress contact with other regions and realize element miniaturization. a step of selectively etching the oxidation-resistant film to form an opening for forming a field oxide film; and a step of forming an opening for forming a field oxide film using the oxidation-resistant film as a mask. forming a field oxide film by selectively oxidizing the substrate through an etching process; selectively etching the first insulating film and the field oxide film to expose the substrate; and selecting the substrate. a step of forming a first polysilicon film on the field oxide film and the gate insulating film; and a step of forming a first polysilicon film on the field oxide film of the first polysilicon film. A step of selectively etching a portion to form an opening for forming a high concentration impurity region, and selectively introducing impurities into the substrate through the opening for forming a high concentration impurity region, a step of forming a concentrated impurity region; a step of selectively oxidizing the first polysilicon film to form a second insulating film; and forming a second polysilicon film on the second insulating film. and a step of doing so.

[Industrial Application Field] The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device,
Specifically, the present invention can be applied to a method of manufacturing a non-volatile semiconductor memory device that requires high voltage, such as an EPROM, and in particular relates to a method of manufacturing a non-volatile semiconductor memory device that can achieve element miniaturization. .

In recent years, for example, EPROMs have come to have a storage capacity of 1 Mbit to 4 Mbit on one chip, but there is no end to the demand for increased storage capacity. - In order to reduce the cost of semiconductor memory devices, there is a demand to reduce the chip size. To achieve this, the memory unit, which consists of one or more electronic elements called memory cells, must be made smaller. In particular, in the case of EPROM, since memory cells use a high voltage, there is a problem in that parasitic transistors (also called parasitic channels) are likely to occur, and there is a limit to their miniaturization.

However, in order to achieve higher levels of integration than ever before, parasitic transistors are less likely to occur (and moreover, smaller memory cells are required).

[Background of the invention]

In a semiconductor device, since a plurality of semiconductor devices are formed on the same semiconductor substrate, it is essential to separate the devices from each other. This is because if the elements interfere with each other, the parasitic transistor becomes conductive and the device does not operate normally. Particularly in MIS type semiconductor devices, it is necessary to prevent parasitic transistors from forming between drains of adjacent transistors, between drains and sources, or between sources. Regarding this parasitic transistor, please refer to “Introduction to VLST Technology, P52-54, Heibonsha, September 1986”
It is described in.

The parasitic transistor will be described below with reference to the drawings.

FIG. 3 is a diagram illustrating details of the parasitic transistor.

In this figure, 4 elements are, for example, p-type substrates, 42a, 4
2b is an n-type source region, 43a and 43b are drain regions, 44. a, 44b are p-type channels/
L/ region, 45a, 45b are gate insulating films, 46a,
46b is a gate, 47 is a field oxide film made of, for example, SiO□, 48 is a glabella insulating film made of, for example, PSG,
49 is a wiring layer made of, for example, AP, and 5o is, for example, a p-type high concentration impurity region.

Note that the transistor T includes a source region 42a1, a drain region 43a1, a channel region 44a1, and a gate insulating film 45.
The transistor T2 consists of a source region 42b1, a drain region 43b, a channel region 44b, a gate insulating film 45b, and a gate insulating film 46b.
It consists of

As shown in FIG. 3, if there is a wiring 49 spanning the drain region 43a of the transistor T and the source region 42b of another transistor T2, the wiring 49 is composed of the drain region 43a, the source region 42, and the wiring 49 as a gate. A parasitic transistor is generated, and when the wiring 49 becomes high voltage, the substrate surface under the wiring 49 is reversed and the parasitic transistor becomes conductive, so that a current flows between the drain region 43a and the source region 42b. A phenomenon occurs. To prevent this, transistor T and transistor T! It is common to form a high-concentration impurity region 50 in a portion of the substrate surface between the two substrates, which has a high impurity concentration and which makes it difficult for the conductivity type to be reversed. Especially in the case of EPROM,
Since a high voltage is used during writing, there is a problem in that this parasitic transistor is likely to become in a quadruple state.

The EFROM will be explained below with reference to the drawings.

4(a) to 4(d) are diagrams explaining the details of the memory cell of the EPROM, and FIG. 4(a) is a top view, and FIG.
b) is a sectional view taken along line AA', FIG. 4(c) is a sectional view taken along line BB', and FIG. 4(d) is a sectional view taken along line C-C'. Here E
One PROM memory cell is composed of one transistor.

In these figures, 51 is, for example, a p-type semiconductor substrate, 52a, 52b are drain regions made of, for example, n-type impurity regions, 53a, 53b are, for example, n-type impurity regions to source regions, 54a, 54b, 54c. ,54d,
54e and 54f are floating gates (also called floating gates) made of first polysilicon, 55a,
55b, 55c are control gates (also called control gates) made of second polysilicon, 56a, 5
6b is a bit line consisting of Af, 57a, 57b, 57c
is the ground line 58a consisting of A2.

58b, 58C158d, 58e, 58f, 58g, 5
8h, 581 is for example p to prevent parasitic transistors.
The type 2 high concentration impurity region 59 is an insulating film made of, for example, Sin.

Note that here, the control gates 55a, 55b,
55c is shared by a plurality of memory cells and is also called a word line. Bit lines 56a, 56b are connected to drain regions 52a152b of transistors of multiple memory cells. Grounds vA57a, 57b, 57c are connected to source regions 53a153b of transistors of memory cells, and source regions 53a, 53b are set to, for example, 0■.

Next, the principle of operation will be explained.

EFROM has floating gates 54a, 54b, 54c, and 54d when the memory cells are irradiated with ultraviolet light.

The charges in 54e and 54f escape to the semiconductor substrate 51 and become zero. In this state, control gates 55a, 55b, 55c as word lines are connected to 5cm, bit lines 56a, 56
When b is set to a voltage such as lV, the floating gates 54a, 54b, 54c, 54
The voltages of d, 54e, and 54f rise to, for example, about 3■,
The transistor of the memory cell becomes conductive. In addition, control gates (55a, 55b, 5) as word lines are also used.
When a high voltage of about 12.5V is applied to 5c and about 7V to bit lines 56a and 56b, the transistor causes avalanche breakdown and generates a large amount of high-energy electrons. Some of these electrons are then transferred to the floating gates 54a, 54b, 54c, 54d, 54e, 54.
reaches f. Floating gates 54a, 54b, 5
4c, 54d, 54e.

When electrons exist in 54f, 5V is applied to control gates 55a, 55b, and 55c as word lines, and bit cotton 5 is applied.
Even if a voltage of lV is applied to 6a, 56b, floating gates 54a, 54b, 54c, 54d, 54e, 5
Since 4f is, for example, about -3■, the transistor of the memory cell becomes non-conductive. In this way EPRO
M stores information of "1" and "0".

During the second write, a parasitic current path from the drain of the transistor of the memory cell being written to through the inversion layer on the word line to the drain → channel → source of the transistor of the adjacent memory cell that coexists with the word line should not occur. , a region with high impurity concentration is required between the transistors of the memory cell. For example, the control gate 55a as a word line has a voltage of 12.5V, and the bit line 56a has a voltage of 7V.
If this is the case, if there is no high concentration impurity region 58e, a parasitic current bus will occur from the drain region 52a, passing under the control gate 55a to the drain region 52b, and further passing under the floating gate 54b to the source region 53a.

On the other hand, if the n-type impurity region of the drain of the memory cell collides with the high-concentration impurity region for preventing parasitic transistors, the PN junction capacitance becomes large (and the operating speed of the EPROM becomes slow). It is necessary to separate the memory cell from the drain of the transistor.This is a major impediment to the miniaturization of memory cells, so a new manufacturing method is required.

[Conventional technology]

The conventional manufacturing method for nonvolatile semiconductor memory devices is
All about electronics special volume VLSI technology and applications k3 fLIS memory is described in JP 37-42 published by Ohmsha, March 1986.

Since this is a general explanation, a conventional method for manufacturing a nonvolatile semiconductor memory device will be specifically explained using the drawings.

Figure 5 (a) to (x), (i)'(r)'(L)'
~(x)'(x)'' is a diagram illustrating an example of a conventional method for manufacturing a nonvolatile semiconductor memory device, and FIG.
) to (x) are cross-sectional views, and Fig. 5 (t)' to (X)' are 5th cross-sectional views.
Figures (1) to (x) rotated by 90 degrees (cross-sectional view in the bit line direction), Figure 5 (i)'(r)'
(x)" is a top view. The illustrated example shows a case where it is applied to an EFROM manufacturing method.

In these figures, 21 is, for example, a p-type substrate, 22
is a first insulating film made of SiO□, for example, and has a function of protecting the substrate 21. 23 is, for example, Si,
Oxidation-resistant films made of N, 24a, 24b, 24c, 24
d is a resist film, and 25 is, for example, a p-type high concentration impurity region, which has a function of preventing the generation of parasitic transistors. 26 is a field oxide film made of, for example, StO□; 27 is a gate insulating film made of, for example, SiOx;
28 is a first polysilicon film made of polysilicon;
9 is a second insulating film made of, for example, SiO2, 30 is a second polysilicon film made of polysilicon, and 31 is an opening.

Note that the first polysilicon film 28 functions as a floating gate, and the second polysilicon film 3
0 functions as a control gate.

Next, the manufacturing method will be explained.

First, as shown in FIG. 5(a), for example, at 1100°C
After forming the first insulating film 22 on the substrate 21 by thermal oxidation method, as shown in FIG.
An oxidation-resistant film 23 is formed by depositing Si3N thereon.

Next, as shown in FIG. 5(c), after coating a resist on the oxidation-resistant film 23 to form a resist film 24a, a fifth
As shown in Figure (d), the resist film 24a is selectively patterned, for example, by exposure and development. At this time, the resist film 24a is patterned so that only so-called transistor regions that will become the drain, channel, and source of a transistor to be formed in the future remain.

Next, as shown in FIG. 5(e), the oxidation-resistant film 23 is selectively etched by plasma etching using, for example, CHF3 gas, using the resist 24a as a mask.

At this time, the first insulating film 22 is exposed. Then the fifth
As shown in Figure (f), the oxidation-resistant film 23 and the resist film 2
After forming a resist film 24b by applying a resist to the entire surface so as to cover 4a, as shown in FIG. A forming opening 31 is formed.

At this time, the resist film 24b is patterned so that only the high concentration impurity region for preventing a parasitic transistor to be formed in the future is removed.

Next, as shown in FIG. 5(h), the substrate 2 is implanted using the resist film 24b as a mask by, for example, B' ion implantation.
After selectively forming high-concentration impurity regions 25 in 1, the resist films 24a and 24b are peeled off and removed, as shown in FIG. 5(i).

Next, as shown in FIG. 5(j), a field oxide film 26 is formed in areas other than the transistor region by field oxidation using the oxidation-resistant film 23 as a mask.

At this time, the field oxide film 26 is formed with oxygen going around to the end of the oxidation-resistant film 23, and this part is called a bird's beak (also called a bird's beak). For this reason, the oxidation-resistant film 23 is etched to be slightly thicker (~0.5 μm) than the channel width of a transistor to be formed in the future. Further, due to the application of heat, B' diffuses and the high concentration impurity region 25 expands. Then the fifth
As shown in Figure (k), the entire oxidation-resistant film 23 is selectively removed by plasma etching using, for example, CHF, gas, or the like.

Next, as shown in FIG. 5(1), field oxidation II! is performed by wet etching using an etchant such as a hydrofluoric acid solution. 126 and the first insulating film 22 are selectively etched to expose the substrate 21, as shown in FIG. 5(m).
As shown in FIG. 2, a gate insulating film 27 is formed by thermal oxidation at 1100° C., for example. Here, the first insulating film 22
The reason why the gate insulating film 27 is formed by oxidizing again after once removing is to form a gate insulating film 27 of good quality and to form the thickness of the gate insulating film 27 with high precision. At this time, since heat is added again, B' is diffused and the high concentration impurity region 25 is expanded.

Next, as shown in FIG. 5(n), a first polysilicon film 28 is formed by depositing polysilicon on the field oxide film 26 and gate insulating film 27 by thermally decomposing SiH using, for example, the CVD method. After that, as shown in FIG. 5(0), a resist is applied on the first polysilicon film 28 to form a resist film 24C.

Next, as shown in FIG. 5(p), the resist film 24c is selectively patterned, for example, by exposure and development. At this time, the resist film 24c is patterned so that only the portion that will become the first polysilicon film 28 as a floating gate to be formed in the future remains. Then the fifth
As shown in FIG. 5(q), the first polysilicon film 28 is selectively etched by plasma etching using, for example, CC1 gas or SF6 gas, using the resist film 24c as a mask, and then the etching process shown in FIG. 5(r) is performed. The resist film 24C is peeled off and removed as shown in FIG.

Next, as shown in FIG. 5(s), for example, 1100°C
A second insulating film 29 is formed on the first polysilicon film 28 by a thermal oxidation method. At this time, heat is added again, so B
2 is further diffused and the high concentration impurity region 25 is expanded. Next, as shown in FIG. 5(1) and (t)', for example, CV
A second polysilicon film 30 is formed by depositing polysilicon on the entire surface by thermally decomposing SiH4 using method D.

Next, as shown in FIGS. 5(u) and (U)', after coating the entire surface with resist to form a resist film 24d, a fifth
As shown in FIGS. (V) and (V)', the resist film 24d is selectively patterned, for example, by exposure and development. At this time, the resist film 24d is patterned so that only portions that will become word lines to be formed in the future remain.

Next, as shown in FIGS. 5(W) and (W)', by wet etching with an etchant such as a hydrofluoric acid solution, the resist film 24d is used as a mask, and the area from the second polysilicon film 30 to the gate insulating film 27 is etched. After selectively etching, the resist film 24d is peeled off and removed, as shown in FIGS. 5(X) and 5(X)'.

Then, a semiconductor device as shown in FIG. 3 is completed through steps of forming a source region, a drain region, a channel, an interlayer insulating film, etc., and a step of forming contacts between each electrode and a wiring layer.

[Problem to be solved by the invention]

However, in such a conventional manufacturing method of a non-volatile semiconductor memory device, the drain region 43a of the transistor T or the source region 42b of the transistor T2 as shown in FIG. In order to separate the high concentration impurity region 50 (high concentration impurity region 25 in FIG. 5) to some extent, the accuracy of the machine, etc. is required when forming the opening 31 for forming the high concentration impurity region shown in FIG. 5(g). It is necessary to take a misalignment margin from the oxidation-resistant film 23, and furthermore, it is necessary to take the positional deviation margin from the oxidation-resistant film 23.
And as shown in FIG. 5(3), the high concentration impurity region 25
When B is diffused and expanded by heat treatment, the drain region or the source region (in FIG. 3, the drain region 43a of the transistor T or the source region 4 of the transistor T2)
There was a problem in that consideration had to be taken to avoid collisions (which fall under 2b).

As a means to solve the above problem, an opening 31 is formed in advance in the resist film 24b during the step shown in FIG. 5(g).
This can be achieved by appropriately separating the oxidation-resistant film 23 from the oxidation-resistant film 23, but this has the disadvantage of making device miniaturization difficult.

Therefore, the present invention provides a nonvolatile semiconductor memory device that can reliably suppress contact between a high concentration impurity region and a source or drain region without providing misalignment margins, and can realize element miniaturization. The purpose is to provide a manufacturing method for.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a non-volatile semiconductor memory device according to the present invention includes the steps of sequentially forming a first insulating film and an oxidation-resistant film on a substrate, and selectively etching the oxidation-resistant film to perform field oxidation. a step of forming an opening for film formation; and a step of forming a field oxide film by selectively oxidizing the substrate through the opening for forming the field oxide film using the oxidation-resistant film as a mask. , said first
selectively etching the insulating film and field oxide film to expose the substrate; selectively oxidizing the substrate to form a gate insulating film; a step of forming a first polysilicon film; a step of selectively etching a portion of the first polysilicon film on the field oxide film to form an opening for forming a high concentration impurity region; a step of forming a high concentration impurity region by selectively introducing impurities into the substrate through an opening for forming a high concentration impurity region; and a step of selectively oxidizing the first polysilicon film. The method includes a step of forming a second insulating film, and a step of forming a second polysilicon film on the second insulating film.

[Effect]

In the present invention, a first insulating film and an oxidation-resistant film are sequentially formed on a substrate, and after an opening for forming a field oxide film is formed by selectively etching the oxidation-resistant film, the oxidation-resistant film is used as a mask. A field oxide film is formed by selectively oxidizing the substrate through the opening for forming the field oxide film. Next, the substrate is exposed by selectively etching the first insulating film and the field oxide film, and a gate insulating film is formed by selectively oxidizing the substrate. A polysilicon film is formed. Next, the portion of the first polysilicon film on the field oxide film is selectively etched to form an opening for forming a high concentration impurity region, and then impurities are etched through the opening for forming a high concentration impurity region. A high concentration impurity region is formed by selectively introducing the impurity into the substrate. After a second insulating film is formed by selective oxidation of the first polysilicon film, a second polysilicon film is formed on the second insulating film.

Therefore, it is possible to alleviate the diffusion of the high concentration impurity region due to heat treatment, and it is also possible to reliably suppress contact between the high concentration impurity region and the source or drain region without providing misalignment margin. This makes it possible to realize element miniaturization.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1(a) to (V) and (r)' to (V)' are diagrams for explaining an embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, and FIG. a) to (V) are cross-sectional views, and Fig. 1 (r)' to (■)' are views of Fig. 1 (r) to (V) rotated by 90 degrees (cross-sectional views in the bit line direction). It is.

In these figures, the same reference numerals as in FIGS. 5(a) to (X) indicate the same or corresponding parts, 32 is an opening for forming a field oxide film, and 33 is an opening for forming a high concentration impurity region. .

Next, the manufacturing process will be explained.

First, as shown in Fig. 1(a),
After forming the first insulating film 22 on the base ff121 by the thermal oxidation method, as shown in FIG.
5tiN4 is deposited on the first insulating film 22 by a CVD method using a gas and Nt gas to form an oxidation-resistant film 23. This corresponds to a step of sequentially forming a first insulating film and an oxidation-resistant film.

Next, as shown in FIG. 1C, after coating a resist on the oxidation-resistant film 23 to form a resist film 24a, a first
As shown in Figure (d), the resist film 24a is selectively patterned, for example, by exposure and development. At this time, the resist film 24a is patterned so that only so-called transistor regions that will become the drain, channel, and source of a transistor to be formed in the future remain.

Next, as shown in FIG. 1(e), the oxidation-resistant film 23 is selectively etched using the resist film 24a as a mask by plasma etching using, for example, CHF3 gas to form an opening 32 for forming a field oxide film. do. At this time, the first insulating film 22 is exposed. This corresponds to the step of selectively etching the oxidation-resistant Ill to form an opening for forming a field oxide film, according to the present invention. Next, as shown in FIG. 1(f), after stripping and removing the resist T-24a, as shown in FIG. 1(g), field oxidation is performed using the oxidation-resistant film 23 as a mask in areas other than the transistor area. The field oxide film 2 is formed by selectively oxidizing the substrate 21 through the opening 32 for forming the oxide film.
form 6. This corresponds to the step of the present invention in which a field oxide film is formed by selectively oxidizing the substrate through an opening for forming a field oxide film using the oxidation-resistant film as a mask.

Next, as shown in FIG. 1(h), for example, Cl-IF5
After selectively removing all the oxidation-resistant film 23 by plasma etching using gas or the like, as shown in FIG. 1 (+),
For example, the field oxide film 26 and the first insulating film 2 are etched by wet etching using an etchant such as a hydrofluoric acid solution.
2 is selectively etched to expose the substrate 21. This corresponds to the step of selectively etching the first insulating film and the field oxide film to expose the substrate according to the present invention. Next, as shown in FIG. 1(j), for example, 1100
A gate insulating film 27 is formed by thermal oxidation at .degree. This corresponds to the step of selectively oxidizing the substrate to form a gate insulating film according to the present invention. Next, as shown in FIG. 1(k), polysilicon is deposited on the field oxide film 26 and the gate insulating film 27 by thermal decomposition of SiHa using the CVD method, for example, to form a first polysilicon film 28. Form. This corresponds to the step of forming the first polysilicon film on the field oxide film and gate insulating film according to the present invention.

Next, as shown in FIG. 1<1), a resist is applied onto the first polysilicon film 28 to form a resist film 24c.

Next, as shown in FIG. 1(m), the resist film 24c is selectively patterned, for example, by exposure and development. At this time, the resist film 24C is patterned so that only the portion that will become the first polysilicon film 28 as a floating gate to be formed in the future remains. Next, as shown in FIG. 1(n), using the resist film 24c as a mask, the portion of the first polysilicon film 28 on the field oxide film 26 is selectively etched by plasma etching using, for example, CCZ, gas, or SF6 gas. Etching is performed to form an opening 33 for forming a high concentration impurity region. This corresponds to the step of the present invention in which the portion of the first polysilicon film on the field oxide film is selectively etched to form an opening for forming a high concentration impurity region.

Next, as shown in FIG. 1(0), a high-concentration impurity region is implanted into the substrate 21 through the opening 33 for forming a high-concentration impurity region using the resist film 24c as a mask by, for example, B' ion implantation method. 25 is selectively formed. This corresponds to the step of forming a high concentration impurity region by selectively introducing impurities into the substrate through the opening for forming the high concentration impurity region according to the present invention. Next, as shown in FIG. 1(p), the resist film 24c is peeled off and removed.

Next, as shown in FIG. 1(q), for example, at 1100°C
A second insulating film 29 is formed on the first polysilicon film 28 by a thermal oxidation method. At this time, since heat is applied, B' is diffused and the high concentration impurity region 25 is expanded.

This corresponds to the step of selectively oxidizing the first polysilicon film to form the second insulating film according to the present invention. Then,
As shown in FIGS. 1(r) and 1(r)', a second polysilicon film 30 is formed by depositing polysilicon on the entire surface by thermally decomposing 5iHn using, for example, the CVD method. This corresponds to the step of forming the second polysilicon film on the second insulating film according to the present invention.

Next, as shown in FIGS. 1(S) and 1(S)', after coating the entire surface with resist to form a resist film 24d, a first
As shown in FIGS. (1) and (t)', the resist film 24d is selectively patterned, for example, by exposure and development. At this time, the resist film 24d is patterned so that only the portion that will become a word line to be formed in the future remains.

Next, as shown in FIGS. 1(u) and (U)', the resist v! is wet-etched using an etchant such as a hydrofluoric acid solution. , 24d as a mask, after selectively etching from the second polysilicon film 30 to the gate insulating film 27, as shown in FIGS. 1(V) and (V)',
The resist film 24d is peeled off and removed.

Then, a semiconductor device as shown in FIG. 3 is completed by forming a source region, a drain region, a channel, an interlayer insulating film, etc., and forming contacts between each electrode and a wiring layer.

That is, in the above embodiment, in order to prevent the diffusion of B in the high concentration impurity region 25, the ion implantation of B for forming the high concentration impurity region 25 is performed in a later step, that is, in the conventional example, the eighth step is the fifth step. The process is performed at the step shown in Figure (h), whereas in the above embodiment, it is performed at the 15th step shown in Figure 1 (Q), and moreover, it is performed at the step shown in Figure 1 (Q).
Since the high concentration impurity region 25 is formed in the self-line of the polysilicon film 28, contact between the high concentration impurity region 25 and the source region or the drain region can be reliably suppressed without providing any misalignment margin. In addition, it is possible to achieve element miniaturization. In the conventional example, the spread of B due to heat in the high concentration impurity region 25 is 5th.
The steps shown in Figures (j), 5(m), and 5(S) occur three times, whereas in the above example, the steps shown in Figure 1(q) only occur once. Therefore, the influence of the spread due to the diffusion of B' can be alleviated more than in the conventional example.

Specifically, in the above embodiment, as shown in FIG. 2(a), the distance M between the drain regions 35a and 35b of the transistor of the memory cell is the same as that of the first polysilicon film 28 as a floating gate. If the alignment accuracy with the transistor region is α (μm), and the width when etching the first polysilicon film 28 is β (μm), then
Ml-2α ten β. On the other hand, in the conventional example, as shown in Fig. 2(b)
As shown in FIG.
The width of the drain region 35c and the drain region 35d to be formed in the future are δ (μm) and the distance at which the gate width becomes narrower than the oxidation-resistant film 23 due to the bird's beak is ε (μm).
The interval M2 is M2=2γ+δ+2ε.

For example, in the latest process α= r =0.3, β−
Since δ=0.8 and ε=0.2, the distance M1 between the drain region 35a and the drain region 35b is 1.4 μm in the above embodiment, whereas in the conventional example, the distance M1 between the drain region 35c and the drain region 35d is The distance M2 is 1°8
It becomes μm. Since the channel width of the transistor is about 0.8 μm, the size of the memory cell in the word line direction is
In the above embodiment, the thickness is 2.2 μm, whereas in the conventional example, it is 2.6 μm, which is a large difference. This difference is especially important.
This is decisive for miniaturization of FROM. In addition, in the conventional example, the influence of diffusion due to heat in the high concentration impurity region 25 is
This problem was alleviated by appropriately setting the distance ε at which the gate width becomes narrower than the oxidation-resistant film 25 due to the bird's beak.

[Effects] According to the present invention, contact between a high concentration impurity region and a source region or a drain region can be reliably suppressed without providing misalignment margin, and element miniaturization can be achieved. effective.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, FIG. 2 is a diagram for explaining the effects of one embodiment, and FIGS.
Figure 3 is a diagram explaining the details of the invention, Figure 3 is a diagram explaining the details of the parasitic transistor, Figure 4 is a diagram explaining the details of the EPROM memory cell, and Figure 5 is a diagram explaining the details of the conventional non-volatile semiconductor. FIG. 2 is a diagram illustrating an example of a method for manufacturing a storage device. 21... Substrate, 22... First insulating film, 23... Oxidation resistant film, 24a, 24c, 24d...Resist film, 25
...High concentration impurity region, 26... Field oxide film, 27... Gate insulating film, 28-... First polysilicon film, 29...・・・
...Second insulating film, 30...Second polysilicon film, 32...
・-Opening for field oxide film formation, 33...
・Opening for forming high concentration impurity region. (BakiNN ＾Sai1Cause (Q) [=$r; 6cpr and ffpc*
+ru. y Sai S drawing (1) += Pu 1 Shir; Wakuchido MA/Shi 1 Iruichi] 5 Captive example's Rihi Kei Hair explanation ji 4 Fig. 2 Ro loincloth

Claims (1)

[Claims] A step of sequentially forming a first insulating film and an oxidation-resistant film on a substrate; a step of selectively etching the oxidation-resistant film to form an opening for forming a field oxide film; forming a field oxide film by selectively oxidizing the substrate through the opening for forming the field oxide film using the oxidation-resistant film as a mask; selectively etching to expose the substrate; selectively oxidizing the substrate to form a gate insulating film; and forming a first polysilicon film on the field oxide film and the gate insulating film. selectively etching a portion of the first polysilicon film on the field oxide film to form an opening for forming a high concentration impurity region; and a step of forming an opening for forming a high concentration impurity region. forming a high-concentration impurity region by selectively introducing impurities into the substrate through the substrate; and forming a second insulating film by selectively oxidizing the first polysilicon film. A method for manufacturing a nonvolatile semiconductor memory device, comprising: forming a second polysilicon film on the second insulating film.