KR100974421B1 - Method for improving design rule of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for improving a design rule of a semiconductor device capable of stably securing the design rule, according to an aspect of the present invention for achieving the above technical problem, to form a first insulating film on a substrate step; Forming a first conductivity type well in one region of the substrate, and forming a second conductivity type well in the other region of the substrate adjacent to the first conductivity type well; Implanting source ions including F (Fluorine) into the second conductivity well; And forming a trench having a step in the isolation region between the first and second conductivity wells so that the substrate of the second conductivity well is more deeply etched than the first conductivity well. Provide a method for improvement.

Florin (F), SiF4, Design Rule, Trench, N-well, P-well, Silicon

Description

METHOD FOR IMPROVING DESIGN RULE OF SEMICONDUCTOR DEVICE}             

1A to 1E are cross-sectional views illustrating a method of improving a design rule of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100 silicon substrate 101 first insulating film

102: first conductivity type well 103: second conductivity type well

104: second insulating film 105: photosensitive film

106: trench

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method suitable for improving a design rule of a semiconductor device by adjusting trench isolation region formation, well formation order, and implanted ions during a semiconductor device manufacturing process.

In the conventional SRAM cell process of a standard logic process, a silicon trench is etched to form a shallow trench isolation region first, and then an N well and a P well formation process are performed. Proceed by forming an NMOS transistor.

However, as devices are integrated, it may be necessary to form a cell designed with a smaller space than the N-well or P-well minimum space design rule. In this case, the desired SRAM cell cannot be secured because the cell space cannot be secured. It may not be possible to form, thus making it difficult to secure the SRAM cell characteristics.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of improving a design rule of a semiconductor device capable of stably securing design rules.

According to an aspect of the present invention for achieving the above technical problem, forming a first insulating film on a substrate; Forming a first conductivity type well in one region of the substrate, and forming a second conductivity type well in the other region of the substrate adjacent to the first conductivity type well; Implanting source ions including F (Fluorine) into the second conductivity well; And forming a trench having a step in the isolation region between the first and second conductivity wells so that the substrate of the second conductivity well is more deeply etched than the first conductivity well. Provide a method for improvement.
BF ₂ is used as a source ion including F.
Formation of the trench having the step, after the step of implanting the source ions,
Forming a second insulating film on the first insulating film; Patterning the photoresist so that the second insulating film over the isolation region is exposed; Sequentially etching the second and first insulating layers using the patterned photoresist as a mask; And etching the substrate with a gas including F as a mask of the patterned photoresist.
The first and second insulating films may be formed of an oxide film and a nitride film, respectively.
The gas containing F is characterized by using CF ₄ .
Injecting the source ion containing the F into the second conductivity type well, SiF ₄ is generated in the second conductivity type well.

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Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1A to 1E are cross-sectional views illustrating a method of improving a design rule of a semiconductor device according to an embodiment of the present invention.

The method of improving the design rule of the semiconductor device according to the present embodiment is to improve the design rule margin of the first conductivity type well, and as shown in FIG. 1A, the semiconductor substrate 100 in which the first and second well formation regions are defined. ), A first pad insulating film 101 is formed by a thermal oxidation process.

In this case, the first and second well forming regions mean an N well forming region and a P well forming region, respectively, and the semiconductor substrate 100 is a silicon substrate. The first pad insulating film 101 uses an oxide film.

Subsequently, the photosensitive film (not shown) is patterned by a photo process so that the first well forming region of the semiconductor substrate 100 is opened, and the first conductive type ion is implanted into the open semiconductor substrate 100 to form a first conductive type. Wells 102 are formed.

Next, a photosensitive film (not shown) is patterned by a photo process so that the second well formation region of the semiconductor substrate 100 is opened, and a second conductivity type ion is implanted into the open semiconductor substrate 100. Wells 103 are formed.

In this case, the first conductivity type is N type, the second conductivity type is P type, and the first and second conductivity types 102 and 103 refer to N wells and P wells, respectively.

Threshold voltage ions are implanted into the surface of the second conductivity type well 103. In this case, as a threshold voltage ion, a source of a fluorine-based source ion such as BF2 is used.

In the case of BF ₂ , when injected into the second conductivity type well 103 of the semiconductor substrate 100, boron (B) and florin (F) are separated to form a SiF ₄ bond until the Si is formed. And in the form of SiF _{4 in} the silicon substrate 100.

As shown in FIG. 1B, SiF ₄ is generated at different concentrations depending on the depth in the second conductivity type well 103.

The second pad insulating film 104 is formed on the first pad insulating film 101 by chemical vapor deposition. In this case, a nitride film is used as the second pad insulating film 104.

Next, a photoresist film (PR) 105 is coated on the second pad insulating film 104, and the photoresist film 105 is patterned by an exposure and development process so as to expose a shallow trench isolation (STI) region.

As illustrated in FIG. 1C, the second and first pad insulating layers 101 and 104 are sequentially etched using the patterned photosensitive film 105 as a mask so that the semiconductor substrate 100 is exposed.

As illustrated in FIG. 1D, the semiconductor substrate 100 is etched using the patterned photosensitive film 105 and the etched first and second pad insulating films 101 and 104 as masks.

The semiconductor substrate 100 is etched using CF ₄ gas.

When using a CF ₄ gas as described above to etch the semiconductor substrate 100, Si in the semiconductor substrate 100 surface by the F and the reaction of CF ₄ and to generate SiF _4, the generated SiF ₄ go off The semiconductor substrate 100 is etched.

At this time, since the SiF ₄ is generated on the surfaces of the first and second conductivity type wells 102 and 103 without the need for energy, and the semiconductor substrate 100 is etched, there is no difference in etching of each well region.

However, in an area deeper than the surface, a difference occurs in the etching depth of the first and second conductivity type wells 102 and 103.

The reason for the difference in etching depth is that SiF ₄ is already present in the second conductivity type well 103.

As a result, when the semiconductor substrate 100 is etched using CF ₄ gas, the second conductivity type well 103 is etched deeper than the first conductivity type well 102 so that the stepped cell is shown in FIG. 1E. Row trench 106 is formed.

If the trench trench 106 is formed deeper in the second conductivity type well 103 as described above, the cell can also be applied to a cell having a small design rule margin.

In the above-described process, when the first and second regions are defined and a trench isolation region is to be formed between the first and second regions, the second region is formed more deeply than the first region. The design rule of the method is to improve the margin.

As described above, the SiF ₄ generated by the reaction of the silicon atoms and the F atoms in the semiconductor substrate of the second region is generated in advance so that the second region is later etched deeper than the first region.

The above-described example is to improve the design rule margin of the second conductivity type well (P well) region. On the contrary, to improve the design rule margin of the first conductivity type well (N well) region, before the trench etching is performed, The source ion containing Florin (F: Fluorine) may be implanted into the first conductivity type well to generate SiF ₄ in the first conductivity type well in advance. Other processes are the same as in the above example.

Although not shown in the drawing, after the wells and trenches are formed, PMOS transistors are formed in the first conductivity type well (N well), and NMOS transistors are formed in the second conductivity type well (P well).

The processes are applicable to SRAM cells.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

The design rule improvement method of the semiconductor device of the present invention described above has the following effects. By forming the trench deeper in the second conductivity type well than the first conductivity type well, the design rule margin of the second conductivity type well can be improved. This makes it easy to apply to cells with smaller design rules.

Claims (6)

Forming a first insulating film on the substrate; Forming a first conductivity type well in one region of the substrate, and forming a second conductivity type well in the other region of the substrate adjacent to the first conductivity type well; Implanting source ions including F (Fluorine) into the second conductivity well; And Forming a trench having a step in an isolation region between the first and second conductivity wells so that the substrate of the second conductivity well is more deeply etched than the first conductivity well. Design rule improvement method of a semiconductor device comprising a. The method of claim 1, Method for improving the design rule of a semiconductor device, characterized in that using BF ₂ as the source ion containing the F. The method of claim 1, Formation of the trench having the step, After implanting the source ions, Forming a second insulating film on the first insulating film; Patterning the photoresist so that the second insulating film over the isolation region is exposed; Sequentially etching the second and first insulating layers using the patterned photoresist as a mask; And And etching the substrate with a gas including F as the mask on the patterned photoresist. The method of claim 3, And the first and second insulating films are formed of an oxide film and a nitride film, respectively. The method of claim 3, The gas containing F is a method of improving the design rule of a semiconductor device, characterized in that using CF ₄ . The method of claim 1, And injecting source ions including F into the second conductive well, thereby generating SiF ₄ in the second conductive well.

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