CN108807281A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
- Publication number
- CN108807281A CN108807281A CN201810689887.8A CN201810689887A CN108807281A CN 108807281 A CN108807281 A CN 108807281A CN 201810689887 A CN201810689887 A CN 201810689887A CN 108807281 A CN108807281 A CN 108807281A
- Authority
- CN
- China
- Prior art keywords
- well region
- ion
- area
- layer
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of semiconductor devices and forming method thereof, method includes：Semiconductor substrate is provided, semiconductor substrate includes the firstth area, the secondth area and third area, and the secondth area is between the firstth area and third area；First ion doping is carried out to semiconductor substrate, forms the first well region in semiconductor substrate, the first well region is interior doped with the first ion；The initial grid layer on covering third area surface is formed on a semiconductor substrate；Later, second ion doping is carried out to the semiconductor substrate in the secondth area and third area, it is the second well region by the first well region transoid in the secondth area, it is third well region by the first well region transoid in third area, doped with the second ion in second well region and third well region, second ion and the first ionic conduction type are on the contrary, the ion concentration of the second well region is more than the ion concentration of third well region；First grid structure is formed on the second well region；Initial grid layer is etched, forms second grid structure on third well region.The method reduces number of mask, reduces cost.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technology
With being constantly progressive for semiconductor technology, the integrated level of semiconductor devices is continuously improved, and this requires in one piece of core
On piece can form more transistors.
Threshold voltage is the critical nature of transistor, has great influence to the performance of transistor.The crystal of different function
Pipe often there is different requirements to need the threshold to different crystal pipe during forming different crystal pipe threshold voltage
Threshold voltage is adjusted.
In order to which the threshold voltage to different crystal pipe is adjusted, it can be doped in the channel region of transistor, form threshold
Threshold voltage regulatory region.The concentration of the threshold voltage adjustments ion of high threshold voltage transistors is less than the threshold of low threshold voltage transistor
Threshold voltage adjusts the concentration of ion.It can be brilliant by forming the threshold voltage adjustments ion pair of various concentration in different crystal pipe
The threshold voltage of body pipe is adjusted.
However, the multi-Vt transistor process flow that the prior art is formed is complicated, patterning process access times are more,
It is of high cost.
Invention content
The technical problem to be solved by the present invention is to provide a kind of semiconductor devices and forming method thereof, simplification of flowsheet subtracts
Few patterning process access times, reduce cost.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of semiconductor devices, including：It provides
Semiconductor substrate, the semiconductor substrate include the firstth area, the secondth area and third area, secondth area be located at firstth area with
Between the third area；First ion doping is carried out to the firstth area, the secondth area and third area of the semiconductor substrate, first
The first well region is formed in area, the secondth area and third area semiconductor substrate, first well region is interior doped with the first ion；Described
Semiconductor substrate third forms initial grid layer in area；After forming the initial grid layer, to partly leading for the secondth area and third area
Body substrate carries out the second ion doping, is the second well region by the first well region transoid in the secondth area, by the first well region in third area
Transoid is third well region, and second well region and third well region are interior doped with the second ion, second ion and the first ion
Conduction type is on the contrary, the second ion doping concentration of the second well region is more than the second ion doping concentration of third well region；Partly leading
First grid structure is formed in body substrate, at least one first grid structure is located on the second well region；Form first grid structure
Afterwards, the initial grid layer is etched, forms second grid structure on the third well region.
Optionally, firstth area is different from the type of device that secondth area and the third area are formed；
Optionally, the method for second ion doping includes：Carry out first time ion implanting, the first secondary ion note
The depth entered is less than the thickness of initial grid layer；After first time ion implanting, second of ion implanting of progress, described second
The depth of ion implanting is more than the thickness of initial grid layer.
Optionally, the method for second ion doping further includes：After second of ion implanting, carry out at least
Primary third time ion implanting, the depth of the third time ion implanting are more than the thickness of initial grid layer.
Optionally, the injection ion dose of the first time ion implanting is more than the injection ionic agent of second of ion implanting
Amount.
Optionally, the injection ion dose of the third time ion implanting is more than the injection ionic agent of second of ion implanting
Amount.
Optionally, the injection ion energy of second of ion implanting is more than the injection ion energy of first time ion implanting
Amount.
Optionally, the injection ion dose of the third time ion implanting is more than the injection ionic agent of second of ion implanting
Amount.
Optionally, the material of the initial grid layer includes：Polysilicon, non-crystalline silicon, microcrystal silicon, amorphous germanium or metal gates material
Material.
Optionally, further include forming the first mask layer on the first well region surface before the second ion doping；With the initial grid
Floor and the semiconductor substrate that the first mask layer is the secondth area of mask pair carry out the second ion doping.
Optionally, the first ion doping technique includes ion implantation technology or solid-source doping technique.
Optionally, after first ion doping, before initial grid layer is formed, further include：In the semiconductor substrate first
Area, the secondth area and third area surface form gate dielectric layer, and the initial grid layer is located at gate dielectric layer surface.
Optionally, the forming method of the first grid structure includes：The gate dielectric layer on the second well region surface is removed, exposure
Go out the second well region surface；The first gate dielectric layer is formed on the second well region surface；First grid is formed in first grid dielectric layer surface
Film；The second mask layer, which is formed, in first grid film surface etches the first grid film using second mask layer as mask,
First grid layer is formed on the second well region surface, forms the first grid structure.
Optionally, the forming method of the second grid structure includes：After forming first grid structure, etch described initial
Grid layer and gate dielectric layer form second grid structure on the third well region.
Optionally, further include：The 4th well region, the 4th well region and first are formed in firstth area semiconductor substrate
Well region is adjacent, and there is the first ion, the 4th well region ion concentration to be higher than the first well region ion concentration in the 4th well region.
Optionally, the forming method of the 4th well region includes：Before carrying out the second ion doping, in the firstth area of part and
Third ion doping is carried out in the semiconductor substrate in the secondth area, and the 4th well region is formed in the firstth area.
Optionally, further include：The second grid structure is formed on the first well region, and described is formed on the 4th well region
One gate structure.
Correspondingly, being formed by semiconductor devices using above-mentioned any one method the present invention also provides a kind of.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
In the forming method for the semiconductor devices that technical solution of the present invention provides, served as a contrast in semiconductor by the first ion doping
The first ion is adulterated in the firstth area of bottom, the secondth area and third area, is formed in the firstth area of semiconductor substrate, the secondth area and third area
First well region；Second ion doping is carried out to the secondth area of semiconductor substrate and third area, the Doped ions of the second doping are second
Ion, the second ion are opposite with the first ionic conduction type so that the secondth area and third area semiconductor substrate realize transoid, at this time
It needs to protect first the firstth area of semiconductor substrate, needs a patterning process；The second ion is used as by initial grid layer simultaneously
The mask layer of doping, using the difference in height of initial grid layer in the secondth area of semiconductor substrate the second well region, in semiconductor substrate
The formation of third well region in 3rd area, initial grid layer needs a patterning process；The Doped ions conduction type of first well region with
Second well region is different with the Doped ions conduction type type of third well region, and the Doped ions of the second well region and third well region are conductive
Type Type is identical, and the second well region is different with the well region Doped ions concentration of third well region, therefore forms the first well region, the second well region
Secondary image chemical industry skill is only needed with third well region, forms first grid structure on the second well region and second on third well region
A patterning process is respectively needed when gate structure, reduces the number of patterning process, it is less to the damage of semiconductor substrate,
Technological process is simplified simultaneously, the performance of semiconductor devices is improved, optimizes technological process.
Further, the semiconductor devices further includes the 4th well region, is mask using initial grid layer, is noted by third ion
Enter to form the 4th well region；It is mask by the first mask layer, carries out the second ion implanting, forms the second well region and third well region；
Therefore form four well regions and need mask twice, image conversion technique twice has been carried out, patterned number is reduced, semiconductor has been served as a contrast
The damage at bottom is less, while having saved technological process, improves the performance of semiconductor devices, optimizes technological process.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of semiconductor devices；
Fig. 2 to Figure 14 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Specific implementation mode
As described in background, the performance of the semiconductor devices of the prior art is poor.
Fig. 1 is a kind of structural schematic diagram of semiconductor devices.
With reference to figure 1, semiconductor substrate 100 is located at the first well region 111 in semiconductor substrate 100, the second well region 112, the
Three well regions 113 and the 4th well region 114, first well region, 111 and second well region 112 are interior with the first trap ion, the first well region
111 ion concentration is more than the ion concentration of the second well region 112, has second in 113 and the 4th well region 114 of the third well region
Trap ion, the second trap ion and the first trap ionic conduction type are on the contrary, the ion concentration of the third well region 113 is more than the 4th trap
The ion concentration in area 114；First grid structure on first well region；Second grid on second well region
Structure；Third gate structure on the third well region；The 4th gate structure on the 4th well region.
Wherein, first well region is used to form low threshold voltage PMOS transistor；Second well region is used to form height
Threshold voltage PMOS transistor；The third well region is used to form low threshold voltage NMOS transistor；4th well region is used for
Form high threshold voltage NMOS transistor.
The first well region 111, the second well region 112, third well region 113 and the 4th trap are formed in the semiconductor substrate 100
It when area 114, in each well region forming process, is required to be formed once graphically, forms four well regions and need to carry out four figures
Shape.Four gate structures are respectively formed on four well regions, the gate structure includes gate dielectric layer and grid layer.
In order to form the different gate dielectric layer of thickness in different zones, need to carry out at least once the material layer for forming gate dielectric layer
Graphically.In order to be respectively formed grid layer on different gate dielectric layers, need at least progress primary graphical, then the semiconductor
At least need six graphical, excessive patterning process in forming process, complex process, and to semiconductor substrate etching mistake
It is more, it is formed so as to cause semiconductor devices poor.
The embodiment of the present invention is the doping concentration difference that mask makes different well regions by initial grid layer, while after conduct
Continue the material layer of gate structure, graphical number is less in the method, less to semiconductor substrate damage, improves semiconductor
The performance of device, and simplify technique.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 2 to Figure 14 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Referring to FIG. 2, providing semiconductor substrate 200.
The semiconductor substrate 200 includes the first area A, the second area B and third area C, and the secondth area B is located at described first
Between area A and the third area C；First area A is different from the type of device that the second area B and third area C is formed.
When the firstth area A is used to form P-type device, the secondth area B and third area C are used to form N-type device；Work as institute
It states the first area A and is used to form N-type device, the secondth area B and third area C are used to form P-type device.
In the present embodiment, the firstth area A is used to form N-type device, and the second area B and third area C are used to form p-type device
Part.
In one embodiment, the firstth area A is used to form P-type device, and the second area B and third area C are used to form N-type device
Part.
In the present embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon.The semiconductor substrate 200 can also be
Polysilicon or non-crystalline silicon.The material of the semiconductor substrate 200 can also be the semi-conducting materials such as germanium, SiGe, GaAs.Institute
It can also be semiconductor-on-insulator structure to state semiconductor substrate 200, the semiconductor-on-insulator structure include insulator and
The material of semiconductor material layer on insulator, the semiconductor material layer includes silicon, germanium, SiGe, GaAs or indium gallium
The semi-conducting materials such as arsenic.
With continued reference to Fig. 2, the first ion doping is carried out to the semiconductor substrate 200, in the first area A, the second area B and the
The first well region 211 is formed in three area C, the Doped ions are the first ion.
First ion doping provides Doped ions to form the first well region and subsequent 4th well region.
When the firstth area A is used to form N-type device, first ion is p-type ion, the first ion packet
It includes：Boron ion, BF2-Ion or indium ion.
When the firstth area A is used to form P-type device, first ion is N-type ion, the first ion packet
It includes：Phosphonium ion, arsenic ion or antimony ion.
In the present embodiment, the firstth area A is used to form N-type device, and first ion is boron ion.
In one embodiment, the firstth area A is used to form P-type device, and first ion is phosphonium ion.
The first ion doping technique includes ion implantation technology or solid-source doping technique.
In the present embodiment, the technique of first ion doping is ion implantation technology, the parameter packet of the ion implanting
It includes：Injection ion is boron ion, and Implantation Energy is 100KeV to 200KeV, injects 0.3 micron to 0.6 micron of depth, injectant
Amount ranging from 5.0 × 1012atom/cm2~5.0 × 1013atom/cm2。
Referring to FIG. 3, forming initial gate material layer 240 on semiconductor substrate 200；The shape in initial gate material layer 240
At patterned layer 205.
Initial 240 surface of gate material layer of 205 covering part of the patterned layer.
The patterned layer 205 is to form the mask layer of initial grid layer.
The material of the patterned layer 205 includes photoresist.
In the present embodiment, before initial grid layer material layer 240 is formed, further include：It is formed on 200 surface of the semiconductor substrate
Gate dielectric layer 241, the initial grid layer material layer 240 are located at 241 surface of gate dielectric layer.
The material of the gate dielectric layer 241 includes：Silica, silicon oxynitride or high dielectric constant material.
The gate dielectric layer 241 provides material to be subsequently formed the gate dielectric layer of second grid structure, and is noted as ion
Fashionable protective layer.
Referring to FIG. 4, being initial gate material layer 240 described in mask etching with the patterned layer 205, in semiconductor substrate
200 surfaces form initial grid layer 242, and the initial grid layer 242 covers the semiconductor substrate surface in third area.
In the present embodiment, the initial grid layer 241 also semiconductor substrate surface of the firstth area of covering part A.
The initial grid layer 242 provides grid layer to be subsequently formed second grid structure, while as follow-up second ion
The mask layer of doping and third ion doping.
The material of the initial grid layer 242 includes：Polysilicon, non-crystalline silicon, microcrystal silicon, amorphous germanium or metal gate material.
The metal gate material includes：Aluminium, tantalum, tungsten, tantalum nitride or titanium nitride.
In the present embodiment, the material of the initial grid layer 242 is polysilicon.
The thickness of the initial grid layer 242 is 0.1 micron to 0.2 micron.
The thickness of the initial grid layer 242 determines subsequent first time ion implanting, second of ion implanting and third
The depth of the injection ion of secondary ion injection, the injection ion depth of first time ion implanting are less than the thickness of initial grid layer, the
Secondary ion injects and the depth of the injection ion of third time ion implanting needs the thickness more than initial grid layer.Initial grid layer
242 thickness are too low, can not ensure the quality of first time ion implanting；Initial 242 thickness of grid layer is blocked up, second of ion implanting and
The injection ion energy needs of third time ion implanting are excessively high, and technology difficulty is higher, and larger to semiconductor substrate damage, unfavorable
In the performance of device.
In the present embodiment, 242 surface of initial grid layer is also formed with barrier layer, when the barrier layer is as ion implanting
Barrier layer and subsequent etching stop-layer.
The material on the barrier layer includes：Silicon nitride, fire sand, nitrogen silicon boride, nitrogen silicon oxide carbide or silicon oxynitride.
In the present embodiment, the material on the barrier layer is silicon nitride.
In other embodiment, barrier layer is not formed on 242 surface of initial grid layer.
In the present embodiment, further include：The 4th well region of formation in the semiconductor substrate 200 of the firstth area A, the described 4th
Well region is adjacent with the first well region, has the first ion in the 4th well region.
In the present embodiment, first well region is used to form low threshold voltage PMOS transistor；Second well region is used for
Form high threshold voltage PMOS transistor；The third well region is used to form low threshold voltage NMOS transistor；4th trap
Area is used to form high threshold voltage NMOS transistor.
Referring to FIG. 5, after forming initial grid layer 242, the 4th well region is formed in the firstth area A semiconductor substrates 200
214。
The forming method of 4th well region 214 includes：The semiconductor substrate of part the firstth area A and the second area B are carried out
Third ion doping, the Doped ions are the first ion, and the 4th well region 214 is formed in the first area A.
The third ion doping technique includes ion implantation technology or solid-source doping technique.
In the present embodiment, the third ion doping technique is ion implantation technology.
Specifically, being that mask carries out the semiconductor substrate of part the firstth area A and the second area B with the initial grid layer 242
Third ion doping, the third ion doping are 214 threshold voltage ion doping of the 4th well region.
The depth of the third ion implanting is less than the thickness of initial grid layer 242, controls the depth of ion implanting so that the
The ion of three ion dopings cannot reach in the first well region 211 of 242 lower section of initial grid layer, only be exposed in the first area A
The first well region 211 in and the first well region 211 of the second area B in form doped region.
After the third ion doping, the 4th well region 214 is formed in the first area A, the ion of the 4th well region 214 is dense
Ion concentration of the degree higher than first well region 211；Second well region 202 among being formed in the second area B, the second trap of the centre
The ion concentration in area 202 is equal with 214 ion concentration of the 4th well region, is more than the ion concentration of the first well region 211.
It is identical that first well region 211 and the 4th well region 214 are formed by semiconductor device type, but function is different.
In the present embodiment, first well region 211 is used to form high threshold voltage semiconductor devices, the 4th well region
214 are used to form low threshold voltage semiconductor device.
The well region Doped ions concentration of high threshold voltage semiconductor devices is less than the well region of low threshold voltage semiconductor device
Doped ions concentration.
The third ion doping is the 4th well region threshold voltage ion doping, to form the threshold voltage tune of the 4th well region
Save area.
In the present embodiment, the firstth area A is used to form N-type device, and first ion is boron ion.
In the present embodiment, the third ion doping technique includes ion implantation technology, the parameter packet of the ion implanting
It includes：Injection ion is boron ion, and Implantation Energy is 10KeV to 30KeV, injects 0.03 micron to 0.1 micron of depth, implantation dosage
Ranging from 1.0 × 1012atom/cm2~1.0 × 1013atom/cm2。
After forming the first well region 211 and the 4th well region 214, the second well region is formed in 200 second area B of semiconductor substrate,
Semiconductor substrate 200 third area C forms third well region, and the forming method of second well region and third well region includes：It is being formed
After the initial grid layer 242, the second ion doping is carried out to the semiconductor substrate 200 of the second area B and third area C, by second
The first well region transoid in area B is the second well region 212, is third well region 213 by 211 transoid of the first well region in third area C, described
In second well region 212 and third well region 213 doped with the second ion, second ion and the first ionic conduction type on the contrary,
Second ion doping concentration of the second well region 212 is more than the second ion doping concentration of third well region 213.
The second ion doping technique includes ion implantation technology.
The method of second ion doping includes：Carry out first time ion implanting, the depth of the first time ion implanting
Thickness of the degree less than initial grid layer 242；After first time ion implanting, carry out second of ion implanting, described second from
The depth of son injection is more than the thickness of initial grid layer 242.
The method of second ion doping further includes：After second of ion implanting, at least once the is carried out
Ion implanting three times, the depth of the third time ion implanting are more than the thickness of initial grid layer.
The forming method of specific second well region 212 and third well region 213 please refers to Fig. 6 to Fig. 8.
It is mask pair the with the initial grid layer 242 referring to FIG. 6, after forming the first well region 211 and the 4th well region 214
The semiconductor substrate 200 of two area B carries out first time ion implanting, and the injection ion is the second ion, second ion and
First ionic conduction type is opposite.
Specifically, being that mask carries out first time ion implanting to intermediate second well region 202 with the initial grid layer 242, make
Part 202 transoid of intermediate second well region is obtained, the first doped region 207 is formed in second area's B semiconductor substrates 200.
In the present embodiment, before carrying out first time ion implanting, further include：It is formed in the semiconductor substrate of the first area A
First mask layer 206, first mask layer 206 cover the initial grid layer 242 on 211 surface of the first well region.
First mask layer 206 is the mask layer of the second ion doping, and the first well region is protected in the second ion doping
211 and the 4th well region 214.
The material of first mask layer 206 is photoresist.
In one embodiment, first mask layer 206 is not formed, using the half of the secondth area of selective ion implanting pair B
Conductor substrate 200 carries out ion implanting.
The conductive ion type of first doped region 207 is identical as the second ionic conduction type.
The first time ion implanting is the second well region threshold voltage ion implanting, to form the threshold voltage of the second well region
Area.
The secondth area B is formed by semiconductor device type and the first area A, and to be formed by semiconductor device type different,
Well region then in the first area A is different from the Doped ions type of well region in the second area B.
When the conduction type of first ion is N-type, the conduction type of second ion is p-type, described second
Ion includes：Phosphonium ion, arsenic ion or antimony ion.
When the conduction type of first ion is p-type, the conduction type of second ion is N-type, described second
Ion includes：Boron ion, BF2-Ion or indium ion.
In the present embodiment, the firstth area A is used to form N-type device, and first ion is boron ion, then the second ion
Type be N-type ion, second ion be phosphonium ion.
In one embodiment, the firstth area A is used to form P-type device, and first ion is phosphonium ion, then second from
The type of son is p-type ion, and second ion is boron ion.
In the present embodiment, the Doped ions in the second well region of the centre 202 are phosphonium ion, intermediate second well region 202
Doped ions conduction type is p-type.The injection ion of the first time ion implanting is the second ion, the conductive-type of the second ion
Type is N-type ion, and first time ion implanting, the i.e. part to intermediate second well region 202 in part are carried out to intermediate second well region 202
Ion carries out contra-doping so that the Doped ions conduction type of the first doped region 207 in intermediate second well region 202 is N-type.
Since initial grid layer 241 is located at 200 third area C Surface of semiconductor substrate, when carrying out first time ion implanting, control
The depth of first time ion implanting processed so that the injection ion of first time ion implanting cannot reach 200 third of semiconductor substrate
Area's C Surface only forms the first doped region 207 in the second well region of centre 202.
The parameter of the first time ion implanting includes：Injection ion is arsenic ion, and Implantation Energy arrives for 30KeV
150KeV injects 0.02 micron to 0.08 micron of depth, implantation dosage ranging from 5.0 × 1012atom/cm2~5.0 ×
1013atom/cm2。
Referring to FIG. 7, after first time ion implanting, second is carried out to the semiconductor substrate 200 of the second area B and third area C
Secondary ion injects, and the injection ion is the second ion.
Second of ion implanting is third well region threshold voltage ion implanting, to form the threshold voltage of third well region
Area.
Specifically, carrying out second of ion implanting to the first well region 211 in intermediate second well region 202 and third area C, make
211 transoid of the first well region of part in third area C is obtained, forms third doped region 209 in the semiconductor substrate of third area C, together
When make 202 transoid of the second well region among part, the second doped region 208 is formed in the semiconductor substrate of the second area B.
The third doped region 209 is the threshold voltage doped region of third well region.
The conductive ion type of the third doped region 209 is identical as the second ionic conduction type.
The conductive ion type of second doped region 208 is identical as the second ionic conduction type.
In the present embodiment, Doped ions in the first well region 211 in the third area C are phosphonium ion, in third area C
The Doped ions conduction type of first well region 211 is p-type.The injection ion of second of ion implanting is the second ion, the
The conduction type of two ions is N-type ion, carries out second of ion implanting to the first well region 211 in third area C, i.e., to part
The part ion of the first well region 211 in third area C carries out contra-doping so that the first well region of part 211 in third area C is anti-
Type forms third doped region 209, and the Doped ions conduction type of third doped region 209 is N-type.
Second of ion implanting, the i.e. part ion to intermediate second well region 202 in part are carried out to intermediate second well region 202
Continue contra-doping so that the Doped ions conduction type of the second doped region 208 in the semiconductor substrate of the second area B is N
Type.
First doped region 207 is the threshold voltage doped region in the second well region being subsequently formed, the third doped region 209
For the threshold voltage doped region in the third well region that is subsequently formed.
It is identical that second well region and third well region are formed by semiconductor device type, but function is different.
In the present embodiment, second well region is used to form low threshold voltage semiconductor device, and the third well region is used for
Form high threshold voltage semiconductor devices.
The well region Doped ions concentration of high threshold voltage semiconductor devices is less than the well region of low threshold voltage semiconductor device
Doped ions concentration.
The injection ion dose of the first time ion implanting is more than the injection ion dose of second of ion implanting so that
Second ion concentration of the first doped region 207 is more than the second ion concentration of third doped region 209.
The injection ion depth of second of ion implanting is higher than the thickness of initial grid layer so that the second ion enters centre
In third well region 203.
The injection ion energy of second of ion implanting is more than the injection ion energy of first time ion implanting so that
The initial grid layer of injection ion penetration of second of ion implanting reaches intermediate third well region.
The parameter of second of ion implanting includes：Injection ion is phosphonium ion, and Implantation Energy arrives for 100KeV
300KeV injects 0.03 micron to 0.07 micron of depth, implantation dosage ranging from 1.0 × 1012atom/cm2~1.0 ×
1013atom/cm2。
Referring to FIG. 8, after second of ion implanting, third is carried out to the semiconductor substrate 200 of the second area B and third area C
Secondary ion injects, and the injection ion is the second ion, is the second well region 212 by 202 transoid of the second well region of the centre, by institute
It is third well region 213 to state 211 transoid of the first well region in third area C.
The third time ion implanting is to form the trap injection of the second well region 212 and third well region 213, second well region
212 and third well region 213 trap ionic conduction type it is identical as the second ionic conduction type.
In the present embodiment, the Doped ions of the first well region 211 in the third area C are phosphonium ion, the first of third area C
The Doped ions conduction type of well region 211 is p-type.The injection ion of the third time ion implanting be the second ion, second from
The conduction type of son is N-type ion, and second ion is boron ion.
Third time ion implanting is carried out to the semiconductor substrate 200 of the second area B and third area C, i.e., to intermediate second well region
The ion of the first well region 211 in 202 and third area C carries out contra-doping so that the doping of semiconductor substrate 200 in the second area B
Ionic conduction type is N-type, forms the second well region 212；Make the Doped ions conductive-type of semiconductor substrate 200 in third area C
Type is N-type, forms third well region 213.
The injection ion depth of third time ion implanting is higher than the thickness of initial grid layer 242 so that the second ion enters
In the first well region 211 of third area C.
The third time ion implanting can be multiple ion implanting.
Third time ion implanting parameter includes：Injection ion is phosphonium ion, and Implantation Energy is 400KeV to 600KeV, injection
0.05 micron to 1.2 microns of depth, implantation dosage ranging from 1.0 × 1013atom/cm2~1.0 × 1014atom/cm2。
The injection ion energy of the third time ion implanting is more than the injection ion energy of second of ion implanting so that
The injection ion of third time ion implanting can reach in the second well region of centre 202 of the lower section of the second doped region 208, Yi Ji
In the first well region 211 of the third area C of three doped regions, 209 lower section.
After forming the second well region 212 and third well region 213, first mask layer 206 is removed,
The technique for removing first mask layer 206 is cineration technics or wet processing.
First well region 211, the 4th well region 214, the second well region 212 and third well region 213 are formed, is only formed and is covered twice
Film layer carries out secondary image chemical industry skill, less to the damage of semiconductor substrate, while having saved technological process, improves and partly leads
The performance of body device, optimizes technological process.
After forming the first well region 211, the 4th well region 214, the second well region 212 and third well region 213, on a semiconductor substrate
First grid structure is formed, at least one first grid structure is located on the second well region；After forming first grid structure, institute is etched
Initial grid layer is stated, forms second grid structure on the third well region.
In the present embodiment, further include：The second grid structure is formed on the first well region, and institute is formed on the 4th well region
State first grid structure.
In other embodiment, first grid structure is formed on the first well region；Second grid knot is formed on the second well region
Structure；Third gate structure is formed on third well region；The 4th gate structure is formed on the 4th well region.
After forming the second well region 212 and third well region 213, second grid structure is formed on the second well region surface.
Referring to FIG. 9, after forming the second well region 212 and third well region 213, the gate medium on 212 surface of the second well region of removal
Layer 241；The first gate dielectric layer 251 is formed on 212 surface of the second well region, first grid is formed on 251 surface of the first gate dielectric layer
Film 252, the first grid film 252 also cover 242 top surface of initial grid layer.
In the present embodiment, second well region 212 is used to form low threshold voltage P-type semiconductor device, the third trap
Area 213 is used to form high threshold voltage P-type semiconductor device.
Since the voltage of high threshold voltage semiconductor devices is higher, to ensure the performance of device, high threshold voltage semiconductor
The gate dielectric layer of device is thicker compared to the gate dielectric layer of low threshold voltage semiconductor device.
In the present embodiment, second well region 212 is used to form low threshold voltage semiconductor device, the third well region
213 are used to form high threshold voltage semiconductor devices, and the gate dielectric layer thickness of first grid structure is less than second grid structure
Gate dielectric layer thickness, therefore need to form the gate dielectric layer of first grid structure on 212 surface of the second well region.
The forming method of first gate dielectric layer 251 includes：The gate dielectric layer 241 on 212 surface of the second well region is removed, cruelly
Expose 212 top surface of the second well region；First gate dielectric layer 251 is formed on 212 surface of the second well region using oxidation technology.
In the present embodiment, semiconductor substrate 200 further includes the first well region 211 and the 4th well region 214, and the first well region is used for shape
At high threshold voltage N-type semiconductor device, the 4th well region 214 is used to form low threshold voltage N-type semiconductor device；That is the second trap
Area 212 and the 4th well region 214 are used to form low threshold voltage semiconductor device, and the first well region 211 and third well region 213 are used for shape
At high threshold voltage semiconductor devices.
In the present embodiment, the grid on 214 surface of the 4th well region of removal while removing the gate dielectric layer on 212 surface of the second well region
Dielectric layer exposes 214 top surface of the 4th well region；First gate medium is formed on 212 surface of the second well region using oxidation technology
The first gate dielectric layer 251 is formed on 214 surface of the 4th well region while layer, is located at first gate medium on 214 surface of the 4th well region
Layer is the gate dielectric layer of the 4th gate structure.
In the present embodiment, there is barrier layer, the barrier layer can protect at the top of initial grid layer on 242 surface of initial grid layer
It is not oxidized, but initial 242 side wall of grid layer is aoxidized, and oxide layer is formed.
In other embodiment, 242 surface of initial grid layer does not form barrier layer, and the first gate dielectric layer is formed in oxidation
Meanwhile 242 top surface of initial grid layer above the first well region and third well region and sidewall surfaces can also form oxide layer, it should
Etching stop layer when oxide layer can be as subsequent etching first grid film 252, for protecting initial grid layer 242.
Referring to FIG. 10, after forming first grid film 252, the second mask layer 260 is formed on 252 surface of first grid film,
252 surface of first grid film on second mask layer, 260 the second well region of covering part, 212 surface.
In the present embodiment, 252 table of first grid film on 260 the 4th well region of covering part of the second mask layer, 214 surface
Face.
Second mask layer 260 provides mask layer to be subsequently formed first grid structure and the 4th gate structure.
The material of second mask layer 260 includes：Photoresist.
The technical process for forming second mask layer 260 includes：Spin coating forms initial second on semiconductor substrate 200
Mask layer (not shown), initial second mask layer covering first grid film, 252 surface；To initial second mask layer into
Row exposure-processed, the exposure template in the exposure process exposes initial second mask layer in part, to initial after exposure
Two mask layers carry out development treatment, expose 252 part surface of first grid film, form second mask layer 260.
1 is please referred to Fig.1, is first grid film 252 and the first gate medium described in mask etching with first mask layer 260
Layer 251 forms first grid structure until exposing 212 top surface of the second well region on 212 surface of the second well region.
Further include the 4th well region 214 in the present embodiment, first grid film 252 and the first gate dielectric layer 251 are also located at the 4th
214 surface of well region, the first mask layer 260 also are located at 252 surface of first grid film on the 4th well region 214.
It is first grid film 252 and the first gate dielectric layer 251 described in mask etching with first mask layer 260, is formed
While first grid structure, the first grid film 252 and the first gate dielectric layer 251 on the 4th well region surface are also etched, the 4th
214 surface of well region forms first grid structure, meanwhile, initial grid layer of the etching removal in the first well region 211 and third well region 213
The first grid film 252 on 242 surfaces exposes the surface on the barrier layer at 242 top of initial grid layer.
In other embodiment, barrier layer, initial grid of the etching removal in the first well region 211 and third well region 213 are not formed
The oxide layer on 242 surface of first grid film 252 and initial grid layer on 242 surface of layer, exposes 242 top surface of initial grid layer.
It please refers to Fig.1 2, after forming first grid structure, forms third mask layer 270 on a semiconductor substrate, described the
Initial 242 top surface of grid layer of three mask layers, 270 covering part.
The third mask layer 270 also covers first grid structure side wall and top surface.
The third mask layer 270 is the mask layer for being subsequently formed second grid structure.
The material of the third mask layer 270 includes photoresist.
The technical process for forming the third mask layer 270 includes：Spin coating forms initial third on semiconductor substrate 200
Mask layer (not shown), the initial third mask layer covering first grid structure side wall and top surface and initial grid layer
242 tops and sidewall surfaces；Processing is exposed to the initial third mask layer, the exposure template in the exposure process is sudden and violent
The initial third mask layer in exposed portion carries out development treatment to the initial third mask layer after exposure, exposes initial grid layer 242
Part surface forms the third mask layer 270.
3 are please referred to Fig.1, is mask with the third mask layer 270, the initial grid layer 242 on 213 surface of etching third well region
With gate dielectric layer 241 second grid is formed on 213 surface of third well region until exposing 213 atop part surface of third well region
Structure.
In the present embodiment, the initial grid layer 242 is also located at the first well region surface, and the third mask layer 270 also is located at
242 surface of initial grid layer of second well region, while etching initial grid layer 242 and gate dielectric layer 241 on third well region surface
The initial grid layer 242 and gate dielectric layer 241 for etching 211 surface of the first well region, expose 211 part surface of the first well region,
One well region, 211 surface forms second grid structure.
In the present embodiment, 242 surface of initial grid layer has barrier layer, the initial grid on 213 surface of etching third well region
Further include the barrier layer for etching initial 242 surface of grid layer before layer 242 and gate dielectric layer 241.
In the present embodiment, first well region and third well region are used to form low threshold voltage semiconductor device, same
The second grid structure is formed in one technique, can save the process flow.
Due to the material layer for the grid layer that initial grid layer is second grid structure and first grid structure, first is formed
During gate structure and second grid structure, it is only necessary to form mask twice, be mask using initial grid layer, pass through third
Ion implanting forms the 4th well region；It is mask by the first mask layer, carries out the second ion implanting, forms the second well region and third
Well region；Therefore form the first well region, the second well region, third well region and the 4th well region and need mask twice, therefore, in semiconductor substrate
Interior four gate structures for forming four well regions and being located on four well regions, need four masks, carry out four times graphically,
The number for reducing patterning process, it is less to the damage of semiconductor substrate, while technological process has been saved, improve semiconductor
The performance of device, optimizes technological process.
4 are please referred to Fig.1, after forming second grid structure, in the first grid structure and second grid structure side wall shape
At side wall, the side wall covering first grid structure side wall and second grid structure side wall；After forming side wall, in first grid knot
The second source and drain doping area is formed in the semiconductor substrate 200 of structure both sides；In the semiconductor substrate 200 of second grid structure both sides
Form third source and drain doping area.
The forming method of the side wall includes：Spacer material layer, the side wall material are formed in the semiconductor substrate 200
The bed of material covers first grid structure side wall and top surface and second grid structure side wall and top surface；It is etched back to the side
The walling bed of material is formed until exposing 200 top surface of semiconductor substrate in first grid structure and second grid structure side wall
The side wall.
In the present embodiment, further include：It is formed in the second grid structure semiconductor substrates on two sides 200 of the first well region 211
First source and drain doping area；It is mixed forming the 4th source and drain in the first grid structure semiconductor substrates on two sides 200 of the 4th well region 214
Miscellaneous area.
It is formed before side wall, further includes that the second well region 212 and third well region 213 are lightly doped, in the second well region 212
On first grid structure both sides form the second lightly doped district, second grid structure both sides on third well region 213 form the
Three lightly doped districts.
Further include that the first well region 211 and the 4th well region 214 are lightly doped, on the first well region 211 in the present embodiment
Second grid structure semiconductor substrates on two sides 200 in formed the first lightly doped district, the first grid knot on the 4th well region 214
The 4th lightly doped district is formed in structure semiconductor substrates on two sides 200.
Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of semiconductor devices, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate includes the firstth area, the secondth area and third area, and secondth area is located at described
Between firstth area and the third area；
First ion doping is carried out to the firstth area, the secondth area and third area of the semiconductor substrate, the firstth area, the secondth area and
The first well region is formed in third area semiconductor substrate, first well region is interior doped with the first ion；
Initial grid layer is formed in semiconductor substrate third area；
After forming the initial grid layer, the second ion doping is carried out to the semiconductor substrate in the secondth area and third area, by the
The first well region transoid in 2nd area is the second well region, is third well region, second well region by the first well region transoid in third area
With in third well region doped with the second ion, second ion and the first ionic conduction type on the contrary, the second of the second well region
Ion doping concentration is more than the second ion doping concentration of third well region；
First grid structure is formed on a semiconductor substrate, and at least one first grid structure is located on the second well region；
After forming first grid structure, the initial grid layer is etched, forms second grid structure on the third well region.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that firstth area and described second
The type of device that area and the third area are formed is different.
3. the forming method of semiconductor devices according to claim 1, which is characterized in that the side of second ion doping
Method includes：First time ion implanting is carried out, the depth of the first time ion implanting is less than the thickness of initial grid layer；For the first time
After ion implanting, second of ion implanting is carried out, the depth of second of ion implanting is more than the thickness of initial grid layer.
4. the forming method of semiconductor devices according to claim 3, which is characterized in that the side of second ion doping
Method further includes：After second of ion implanting, third time ion implanting at least once, the third secondary ion note are carried out
The depth entered is more than the thickness of initial grid layer.
5. the forming method of semiconductor devices according to claim 3, which is characterized in that the first time ion implanting
Inject the injection ion dose that ion dose is more than second of ion implanting.
6. the forming method of semiconductor devices according to claim 4, which is characterized in that the third time ion implanting
Inject the injection ion dose that ion dose is more than second of ion implanting.
7. the forming method of semiconductor devices according to claim 3, which is characterized in that second of ion implanting
Inject the injection ion energy that ion energy is more than first time ion implanting.
8. the forming method of semiconductor devices according to claim 4, which is characterized in that the third time ion implanting
Inject the injection ion dose that ion dose is more than second of ion implanting.
9. the forming method of semiconductor devices according to claim 1, which is characterized in that the material packet of the initial grid layer
It includes：Polysilicon, non-crystalline silicon, microcrystal silicon, amorphous germanium or metal gate material.
10. the forming method of semiconductor devices according to claim 1, which is characterized in that before the second ion doping, also wrap
It includes and forms the first mask layer on the first well region surface；Partly the leading as the secondth area of mask pair using the initial grid layer and the first mask layer
Body substrate carries out the second ion doping.
11. the forming method of semiconductor devices according to claim 1, which is characterized in that the first ion doping work
Skill includes ion implantation technology or solid-source doping technique.
12. the forming method of semiconductor devices according to claim 1, which is characterized in that after first ion doping,
Before initial grid layer is formed, further include：Gate dielectric layer is formed on the firstth area of the semiconductor substrate, the secondth area and third area surface,
The initial grid layer is located at gate dielectric layer surface.
13. the forming method of semiconductor devices according to claim 12, which is characterized in that the first grid structure
Forming method includes：The gate dielectric layer for removing the second well region surface exposes the second well region surface；It is formed on the second well region surface
First gate dielectric layer；First grid film is formed in first grid dielectric layer surface；The second mask layer is formed in first grid film surface,
Using second mask layer as mask, the first grid film is etched, first grid layer is formed on the second well region surface, forms institute
State first grid structure.
14. the forming method of semiconductor devices according to claim 13, which is characterized in that the second grid structure
Forming method includes：After forming first grid structure, the initial grid layer and gate dielectric layer, the shape on the third well region are etched
At second grid structure.
15. the forming method of the semiconductor devices according to claim 1 or 14, which is characterized in that further include：Described
The 4th well region is formed in one area's semiconductor substrate, the 4th well region is adjacent with the first well region, with the in the 4th well region
One ion, the 4th well region ion concentration are higher than the first well region ion concentration.
16. the forming method of semiconductor devices according to claim 15, which is characterized in that the formation of the 4th well region
Method includes：Before carrying out the second ion doping, third ion is carried out in the semiconductor substrate in the firstth area of part and the secondth area
Doping forms the 4th well region in the firstth area.
17. the forming method of semiconductor devices according to claim 15, which is characterized in that further include：In the first well region
It is upper to form the second grid structure, the first grid structure is formed on the 4th well region.
18. a kind of being formed by semiconductor devices using any one of claim 1 to 17 method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810689887.8A CN108807281B (en) | 2018-06-28 | 2018-06-28 | Semiconductor device and method of forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810689887.8A CN108807281B (en) | 2018-06-28 | 2018-06-28 | Semiconductor device and method of forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108807281A true CN108807281A (en) | 2018-11-13 |
| CN108807281B CN108807281B (en) | 2020-09-01 |
Family
ID=64072424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810689887.8A Active CN108807281B (en) | 2018-06-28 | 2018-06-28 | Semiconductor device and method of forming the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108807281B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111697073A (en) * | 2019-03-15 | 2020-09-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111834228A (en) * | 2020-07-30 | 2020-10-27 | 上海华虹宏力半导体制造有限公司 | Preparation method of LDMOS device |
| CN115020343A (en) * | 2022-07-19 | 2022-09-06 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor device |
| CN116053274A (en) * | 2023-01-28 | 2023-05-02 | 合肥晶合集成电路股份有限公司 | Semiconductor integrated device and manufacturing method thereof |
| CN116864450A (en) * | 2023-09-05 | 2023-10-10 | 合肥晶合集成电路股份有限公司 | Preparation method of MOS transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648288A (en) * | 1992-03-20 | 1997-07-15 | Siliconix Incorporated | Threshold adjustment in field effect semiconductor devices |
| US6090652A (en) * | 1996-12-28 | 2000-07-18 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions |
| CN101842898A (en) * | 2007-10-30 | 2010-09-22 | 国际商业机器公司 | Method for enabling multiple vt devices using high-k metal gate stacks |
| CN103026485A (en) * | 2010-08-17 | 2013-04-03 | 德州仪器公司 | CMOS transistor fabrication with different threshold voltages |
| CN103730419A (en) * | 2012-10-12 | 2014-04-16 | 北大方正集团有限公司 | Threshold voltage adjusting method |
-
2018
- 2018-06-28 CN CN201810689887.8A patent/CN108807281B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648288A (en) * | 1992-03-20 | 1997-07-15 | Siliconix Incorporated | Threshold adjustment in field effect semiconductor devices |
| US6090652A (en) * | 1996-12-28 | 2000-07-18 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions |
| CN101842898A (en) * | 2007-10-30 | 2010-09-22 | 国际商业机器公司 | Method for enabling multiple vt devices using high-k metal gate stacks |
| CN103026485A (en) * | 2010-08-17 | 2013-04-03 | 德州仪器公司 | CMOS transistor fabrication with different threshold voltages |
| CN103730419A (en) * | 2012-10-12 | 2014-04-16 | 北大方正集团有限公司 | Threshold voltage adjusting method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111697073A (en) * | 2019-03-15 | 2020-09-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111697073B (en) * | 2019-03-15 | 2023-07-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111834228A (en) * | 2020-07-30 | 2020-10-27 | 上海华虹宏力半导体制造有限公司 | Preparation method of LDMOS device |
| CN111834228B (en) * | 2020-07-30 | 2024-03-29 | 上海华虹宏力半导体制造有限公司 | Preparation method of LDMOS device |
| CN115020343A (en) * | 2022-07-19 | 2022-09-06 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor device |
| CN116053274A (en) * | 2023-01-28 | 2023-05-02 | 合肥晶合集成电路股份有限公司 | Semiconductor integrated device and manufacturing method thereof |
| CN116864450A (en) * | 2023-09-05 | 2023-10-10 | 合肥晶合集成电路股份有限公司 | Preparation method of MOS transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108807281B (en) | 2020-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108807281A (en) | Semiconductor devices and forming method thereof | |
| KR100205320B1 (en) | Mosfet and fabrication thereof | |
| KR101547707B1 (en) | Method of creating asymmetric field-effect-transistors | |
| US10103244B2 (en) | Drain extended MOS transistors with split channel | |
| US7718506B2 (en) | Isolation structure for MOS transistor and method for forming the same | |
| CN107919284A (en) | The forming method of semiconductor structure | |
| US4075754A (en) | Self aligned gate for di-CMOS | |
| US9761594B2 (en) | Hardmask for a halo/extension implant of a static random access memory (SRAM) layout | |
| EP1275147B1 (en) | Method of manufacturing a semiconductor device | |
| CN105762103A (en) | Semiconductor structure and forming method therefor | |
| US7144782B1 (en) | Simplified masking for asymmetric halo | |
| US7015554B2 (en) | Semiconductor device and method for fabricating the same | |
| JP4383929B2 (en) | Method for manufacturing high voltage transistor of flash memory device | |
| US10217754B2 (en) | Semiconductor device and method of fabricating the same | |
| KR101477606B1 (en) | A method for forming a semiconductor structure | |
| CN108470680B (en) | Method for manufacturing semiconductor structure | |
| US20190067127A1 (en) | Semiconductor structure and fabrication method thereof | |
| US20090114957A1 (en) | Semiconductor device and method of manufacturing the same | |
| CN102110636A (en) | Methods for improving reverse narrow channel effect and manufacturing metal oxide semiconductor (MOS) transistor | |
| CN109545674B (en) | Semiconductor device forming method and semiconductor device | |
| CN107170704A (en) | Semiconductor structure and forming method thereof | |
| CN111785777B (en) | High voltage CMOS device and method of manufacturing the same | |
| CN116779615B (en) | Integrated semiconductor device and manufacturing method thereof | |
| CN113437148B (en) | Semiconductor structure and forming method thereof | |
| KR100546124B1 (en) | Transistor Formation Method of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |