JPH11121612A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance reliability in a structure, by a method wherein a conductive member between an underlayer wiring and a columnar connection part is integrally formed. SOLUTION: A width of an underlayer wiring 8 is W0 and a plug 7 has a columnar plane which is a trapezium accommodated in this width. A length in an extension direction of the underlay wiring 8 is L0 , a height of the underlayer wiring 8 is Hw, and a height of the plug 7 is Hp. The plug 7 is directed downward in an extension direction of the underlayer wiring 8 in a connection portion with the underlayer wiring 8, namely the plug 7 has a shape enlarged slightly toward a direction of the underaleyr wiring 8, and a length of this enlarged part is L1 , and such a continuous structure is mechanically filmy a connection body, and resistance is not electrically increased. Accordingly, a conductive material comprising the underlay wiring 8 and the plug 7 is simultaneously and integrally formed and connection resistance is not caused, and it is possible to attain preferable electric characteristics and attain a structure having high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a multi-layer wiring of a semiconductor device having upper and lower wirings and columnar connecting portions (hereinafter, appropriately referred to as plugs) connecting the upper and lower wirings. The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device, a method of forming a plug called a columnar connecting portion (columnar convex portion) or a through-hole plug for connecting a lower layer wiring of a multilayer wiring to an upper layer wiring is disclosed in, for example, JP-A-63-76350. No., Japanese Unexamined Patent Publication No.
No. 47935, JP-A-9-69559 and the like.

FIG. 4 is a view for explaining an example of a structure of interlayer connection in a conventional semiconductor device. In a conventional semiconductor device, as shown in FIG.
One interlayer insulating film 2 is formed, and a lower wiring 41 is formed thereon. Then, the second interlayer insulating film 3 is laminated on the first interlayer insulating film 2 so as to surround the lower wiring 41. Further, a resist mask 42 is formed in order to form a vertical connection portion connecting an upper layer wiring (not shown) formed on the second interlayer insulating film 3 and the lower layer wiring 41, and a through hole is formed in the resist mask 42. Opening 43a for hole formation
Is formed, and the second interlayer insulating film 3 is etched from the opening 43a by etching to form a through hole 43b reaching the lower wiring 41.

Thereafter, the resist mask 42 is removed, and a conductive material is buried in the through hole 42b to make contact with a wiring formed in an upper layer. In the formation of such a conventional multilayer wiring, an opening defect is likely to occur at the time of patterning a resist for opening a through-hole as the diameter of the through-hole becomes finer. In addition, there is a problem that the opening position of the through hole is likely to shift due to the miniaturization of the lower wiring and the miniaturization of the wiring interval.

FIG. 5 is a view for explaining another multilayer wiring structure in a conventional semiconductor device.
5A is a front sectional view, and FIG. 5B is a side sectional view.
In this example, first, a first interlayer insulating film 2 is formed on a semiconductor substrate 1 as shown in FIG. Next, on the first interlayer insulating film 2, a plurality of conductive members 50 in which a lower wiring 51, an etching stopper 52, and a plug member 53 are stacked are formed in parallel at predetermined intervals, and then a plurality of conductive members 5 are formed.
The second interlayer insulating film 54 is buried in the gap 0.

Next, a resist pattern 55 slightly larger than the through-hole plug to be formed is formed on the conductive member 50, and the plug member 53 is etched by using the resist pattern as an etching mask to obtain a resist pattern 55 shown in FIG. As shown in the side sectional view of FIG. 7, a lower layer wiring 51 and a through-hole plug 53a are formed.

In such a structure and a manufacturing method, the plug member 53 is etched by the etching stopper 52.
, But since isotropic etching is used, FIG.
As shown in (b), the connection portion of the through-hole plug 53a with the etching stopper 52 is over-etched, and L1 shorter than the width Lo of the through-hole plug 53a.
It can be as long as one.

In addition, in forming such a conventional multilayer wiring structure, since an etching stopper 52 is required at the boundary with the lower wiring 51, the formation of the conductive member 50 is complicated, and the isotropic etching is performed. The etching process was also complicated, for example, by alternately switching between and anisotropic etching.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a first object of the present invention is to provide a conductive member in which a lower wiring and an interlayer connection plug are formed at one time. It is another object of the present invention to provide a semiconductor device having excellent characteristics.

A second object of the present invention is to provide a method of manufacturing a semiconductor device in which a step of forming a plug for connection between multilayer wirings is simplified.

[0011]

A semiconductor device according to the present invention comprises a lower wiring and an upper wiring arranged at predetermined intervals in an interlayer insulating film; and a lower wiring formed substantially perpendicular to the lower wiring and the upper wiring. A columnar connecting portion for connecting a wiring and the upper layer wiring is provided, and a conductive member between the lower layer wiring and the columnar connecting portion is formed at a time.

Further, in the semiconductor device according to the present invention, a main component material of the conductive member is made of one or more of polycrystalline silicon, aluminum, copper, cobalt, titanium, molybdenum, and tungsten. It is assumed that.

Further, in the semiconductor device according to the present invention, the conductive member is made of a material having substantially the same etching characteristics at least at a connection portion between the lower wiring and the columnar connection portion. It is.

Further, in the semiconductor device according to the present invention, the columnar connecting portion has a shape that is enlarged in a direction of extension of the lower layer wiring toward a direction of the lower layer wiring at a connection portion with the lower layer wiring. It is assumed that.

Next, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a groove in an interlayer insulating film on a semiconductor substrate, a step of filling a conductive member inside the groove, and a step of forming the conductive member. A step of forming a resist pattern for forming a columnar connection portion on the surface; and forming a lower layer wiring from the conductive member by etching the conductive member by a predetermined amount using the resist pattern as a mask, and forming a lower layer wiring from the lower layer wiring to an upper layer. Forming an extending columnar connecting portion.

Further, the method of manufacturing a semiconductor device according to the present invention is characterized in that the method further includes a step of removing the resist pattern and forming an upper layer wiring on the columnar connection portion.

Further, in the method of manufacturing a semiconductor device according to the present invention, the conductive member is etched by anisotropic etching.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. The same reference numerals in the drawings denote the same or corresponding parts.

Embodiment 1 1 and 2 are views showing a structure of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a perspective view thereof, FIG. 1A is a diagram showing a lower layer wiring and a columnar connecting portion (plug), and FIG. 1B is a diagram showing an upper layer wiring formed thereon. FIG. 2 shows FIG.
FIGS. 2A and 2B are a plan view and a cross-sectional view, respectively, of the semiconductor device of FIG.
(C) is a side sectional view.

First, in FIGS. 1A and 1B, 1 is a semiconductor substrate, 2 is a first interlayer insulating film formed on the semiconductor substrate 1, and 3 is a semiconductor substrate on the interlayer insulating film 2. The formed second interlayer insulating film, 4 is a groove formed in the interlayer insulating film 3, 8 is a lower wiring formed on the interlayer insulating film 2 at the bottom of the groove 4, and 9 is an interlayer insulating film 3. An upper layer wiring 7 formed on the upper portion extends vertically from the lower layer wiring 8 and reaches the upper layer wiring 8 to connect a columnar connecting portion (plug) for connecting the two wirings, and 10 is formed on the interlayer insulating film 3 and formed therein. Is a third interlayer insulating film on which the upper wiring 9 runs.

In this structure, the lower wiring 8 and the plug 7
Are formed simultaneously at the same time. In other words, they are integrally formed in the same process or in a process that directly continues.
Therefore, good electrical characteristics can be obtained without generating connection resistance.

Next, referring to the plan view of FIG. 2A, the width of the lower wiring 8 is Wo, and the plug 7 has a quadrangular columnar shape within the width thereof. The length in the extension direction of No. 8 is Lo. Referring to the front sectional view of FIG. 2B, the height of lower wiring 8 is Hw, and the height of plug 7 is Hp.

Further, referring to the side cross-sectional view of FIG. 2C, the plug 7 is connected downward with the lower wiring 8 at the connection portion with the lower wiring 8, that is, in the direction of the lower wiring 8. It has a shape slightly enlarged toward. The length of the enlarged portion is L1 in the figure. Such a continuous structure is mechanically a strong connection, and is extremely desirable without increasing the electrical resistance.

Embodiment 2 FIG. FIG. 3 is a diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and shows a manufacturing process of the semiconductor device having the structure described in the first embodiment as an example. Referring to the manufacturing method with reference to FIG. 3, first, with reference to FIG. 3 (a), a first interlayer insulating film 2 made of, for example, silicon oxide SiO ₂ on the semiconductor substrate 1 of silicon or the like. Note that the semiconductor substrate 1 includes a substrate on which a circuit element or an electronic circuit is already formed. Next, the first interlayer insulating film 2
A second interlayer insulating film 3 is formed thereon. The thickness of the second interlayer insulating film 3 is, for example, 1300 nm.

Next, referring to FIG. 3B, a groove 4 having a width Wo is formed in the interlayer insulating film 3 by using a photolithography technique and a dry etching technique. The width Wo of this groove 4
Is set to, for example, 300 nm as a width required for the lower wiring. The depth of the groove 4 is, for example, 130
It is set to 0 nm.

Next, referring to FIG. 3C, a conductive member 5 made of, for example, tungsten is deposited by a CVD method.
It is deposited so as to fill the groove 4 and extend to the surface of the interlayer insulating film 3. Next, referring to FIG. 3D, the excess conductive member 5 is etched back, for example, excess tungsten is etched back with sulfur hexafluoride SF ₆ gas to expose the surface 3E of the interlayer insulating film 3. Let it.

Next, referring to FIG. 3 (e) and FIGS. 2 (a) to 2 (c), the lower wiring 8
A resist pattern 6 is formed by a photolithography technique at a portion where a plug 7 for connecting the wiring 7 and the upper wiring 9 is formed. Then, the conductive member 5 is etched using the resist pattern 6 as a mask. For example, tungsten is etched by SF ₆ gas. FIG. 3E is a diagram in which the etching is in progress.

Next, FIG. 3 (f), and FIG.
Referring to FIG. 2C, the etching amount is controlled to a predetermined amount, the length of plug 7 is Hp, and the thickness of lower wiring 8 made of a conductive material remaining at the bottom of groove 4 is Hw. By the way, the etching is stopped. In this case, it is desirable to perform etching by anisotropic etching so that side etching does not occur. Thereby, a plug having a vertical side surface can be formed.

As a preferred example, the depth of the groove 4 is, for example, 1300 nm as described above, the height Hw required for the lower wiring is 500 nm, for example, and the height Hp required for the plug 7 is 800 nm, for example. And

Through the above steps, the lower wiring 8 and the plug 7
Are formed at a time with the same conductive material, and then are formed into a predetermined shape as the lower wiring 8 and the plug 7 by etching.

Next, referring to FIG. 1B, a third interlayer insulating film 10 is formed on interlayer insulating film 3 at the same time as filling the portion of trench 4 where the conductive material has been etched away. .
A groove is formed in the interlayer insulating film 10 so as to pass over the plug 7, and the upper wiring 9 is formed in the groove. This allows
The lower wiring 8 and the upper wiring 9 are connected via the plug 7, and a semiconductor device is formed. Further, by repeating the cycle of the above-described steps, it is possible to form a multi-layer wiring not limited to two layers but more.

The manufacturing method described above can be summarized as follows. A groove for forming a lower wiring (or a first wiring) is formed in the interlayer insulating film. The depth of this groove is a value obtained by adding the depth required as an interlayer insulating film between the lower wiring and the upper wiring (or the second wiring) to the depth required for the lower wiring. Next, the groove is filled with a conductive material, and a resist pattern having a size corresponding to the through hole is formed thereon at a position corresponding to the through hole. Next, the conductive material in the groove is etched through the resist pattern so as to leave a necessary thickness as a lower wiring at the bottom in the groove. As a result, a columnar wiring (plug) connecting the lower wiring and the upper wiring is formed. Thereafter, the resist is removed, an interlayer insulating film is formed while filling the groove from which the conductive material has been removed, and the interlayer insulating film is planarized as necessary. An upper layer wiring is formed thereon, and is connected to the columnar wiring (plug) formed earlier. Thus, a multilayer wiring structure in which the lower wiring and the upper wiring are connected is formed.

According to the manufacturing method described above, since the lower wiring 8 and the plug 7 are formed simultaneously with the same material at a time, the manufacturing process of the multilayer wiring can be shortened. Also,
Foreign matter generated when a conductive material such as tungsten is deposited is reduced, and a highly reliable wiring can be formed.

In the conventional through-hole plug described with reference to FIG. 4, a plug is formed by opening a through-hole. However, in this conventional method, it is necessary to open a fine hole. . However, in the method of this embodiment, the resist pattern when forming the through-hole plug is not a hole, but the resist is left on the conductive material to be the through-hole plug, and the through-hole plug is left by etching. The formation facilitates photolithography. Also, the through-hole plug mask can be larger than the size required for the through-hole plug, and especially in the direction crossing the groove, so that photolithography becomes easy in that respect.

Further, it can be seen that the surface at the boundary between the plug 7 and the lower wiring 8 has a continuous curved surface as shown in FIG. It can also be seen that the length L1 of this boundary portion is larger than the plug length L0 in the direction in which the groove 4 extends. Such a continuous structure is highly desirable both electrically and mechanically. According to the manufacturing method as described above, a connection structure having such a shape can be formed.

Embodiment 3 Next, a semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention will be described. In the first and second embodiments, the case where tungsten is used as the conductive member to be the lower wiring and the plug has been described. However, other conductive materials can be used.

As an example, in a step corresponding to FIG.
0 nm is deposited, and a thin titanium film is formed on the bottom or side surface of the groove 4. Then, an aluminum alloy containing copper was
It is also possible to form a stacked structure of two layers by depositing 00 nm.

In the case of aluminum, a chlorine Cl ₂ gas and a boron chloride BCl ₃ gas are used as an etching gas, and the condition of only anisotropic etching is applied. Can be a preferred continuous structure. In addition, even when a three-layer structure including titanium nitride TiN or Ti + TiN is used in place of the titanium Ti in the above-described order, similarly preferable results were obtained.

As described above, the conductive material causes the portion to be the lower wiring and the portion to be the plug to be deposited at a time. Here, "at one time" is used to mean not only depositing the same material at one time, but also directly and continuously and integrally depositing different kinds in the same process.

Further, it was confirmed that, besides tungsten and aluminum, polycrystalline silicon, copper, cobalt, titanium, molybdenum and the like can be applied as a main component material as a conductive member having a uniform etching characteristic. Also,
It was also confirmed that a plurality of these conductive materials can be applied in a laminated structure as in the second embodiment.

However, if a two-layer structure of, for example, aluminum and titanium, or polycrystalline silicon and tungsten is present at the boundary between the plug 7 and the lower wiring 8, the etching characteristics are suddenly changed. There is a possibility that constriction due to over-etching as shown in FIG. Therefore, at the boundary between the plug and the lower wiring,
It is desirable to use a conductive material having substantially the same etching characteristics. In other words, it is desirable not to include a material that serves as an etching stopper.

As described above, according to this embodiment, the appropriate conductive material as described above can be used for the members to be the lower wiring and the plug.

[0043]

Since the present invention is configured as described above, it has the following effects. Claim 1
According to the inventions of (1) to (2), since the lower wiring and the member to be the plug are formed by one-time deposition of the conductive material, there is an effect that a highly reliable structure is obtained.

According to the third aspect of the present invention, the boundary between the lower wiring and the plug is formed of a material having substantially the same etching characteristics and does not include, for example, a material serving as an etching stopper whose etching characteristics change rapidly. In addition, the shape of the boundary between the lower wiring and the plug is not constricted, and a highly reliable plug can be obtained.

According to the fourth aspect of the invention, the connection length of the boundary between the lower wiring and the plug of the conductive member is long, and there is an effect that high reliability can be obtained both electrically and mechanically.

According to the fifth aspect of the present invention, since the lower wiring and the member serving as the plug can be formed by temporarily depositing the conductive material, the manufacturing process of the multilayer wiring can be shortened, and a highly reliable structure can be obtained. There is. In addition, it is difficult to cause misalignment between the wiring and the plug formation position, and there is an effect that photolithography for forming the plug becomes easy.

According to the invention of claim 6, connection between the lower wiring and the upper wiring is realized, and a semiconductor device having a multilayer wiring structure is obtained.

According to the seventh aspect of the present invention, the etching for forming the plug can be performed only by the anisotropic etching, and there is an effect that a wiring structure having high dimensional accuracy and few errors can be formed.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a structure of a semiconductor device according to a first embodiment of the present invention, particularly a structure of a lower wiring and a plug.

FIG. 2 is a diagram showing a structure of the semiconductor device according to the first embodiment of the present invention, particularly a structure of a lower wiring and a plug;
(A) is a plan view, (b) is a front sectional view, and (c) is a side sectional view.

FIGS. 3A to 3F are views for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIGS. 3A to 3F are front sectional views showing the steps;

FIG. 4 is a diagram for explaining a structure of an interlayer connection and a manufacturing method in a conventional semiconductor device.

FIG. 5 is a diagram for explaining a structure and a manufacturing method of an interlayer connection in another conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate, 2 first interlayer insulating film, 3 second interlayer insulating film, 3E exposed surface of second interlayer insulating film, 4 grooves,
5 conductive member, 6 resist pattern, 7 plug, 8
Lower wiring, 9 upper wiring, 10 third interlayer insulating film,
41 lower layer wiring, 42 resist, 43a resist opening, 43b contact hole, 50 conductive member, 51
Lower layer wiring, 52 etching stopper, 53 through-hole plug member, 53a through-hole plug.

Claims (7)

[Claims] 1. A lower wiring and an upper wiring arranged at predetermined intervals in an interlayer insulating film, and a columnar connection formed substantially perpendicular to the lower wiring and the upper wiring and connecting the lower wiring and the upper wiring. And a conductive member between the lower wiring and the columnar connection portion is formed at a time. 2. The material according to claim 1, wherein the main component material of the conductive member is at least one of polycrystalline silicon, aluminum, copper, cobalt, titanium, molybdenum, and tungsten. Semiconductor device. 3. The conductive member according to claim 1, wherein the conductive member is made of a material having substantially the same etching characteristics at least at a connection portion between the lower wiring and the columnar connection portion. Semiconductor device. 4. The column-shaped connection portion has a shape which is enlarged in a direction of extension of the lower layer wiring toward a direction of the lower layer wiring at a connection portion with the lower layer wiring. The semiconductor device according to any one of the above. 5. A step of forming a groove in an interlayer insulating film on a semiconductor substrate, a step of filling a conductive member inside the groove, and a resist pattern for forming a columnar connection on the surface of the conductive member. Forming a lower layer wiring from the conductive member by etching the conductive member by a predetermined amount using the resist pattern as a mask, and forming a columnar connecting portion extending from the lower layer wiring to an upper layer. A method for manufacturing a semiconductor device, comprising: 6. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of removing said resist pattern and forming an upper layer wiring on said columnar connection portion. 7. The method according to claim 5, wherein the etching of the conductive member is performed by anisotropic etching.