JPH11119727A - Ac type pdp driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an erroneous lighting in the fighting keeping period and to realize a high quality display without flickering by making the pulse width of a fixed number of pieces of voltage pulses applied in the starting stage of the lighting keeping period shorter than those of another voltage pulses. SOLUTION: In a sustaining period TS, an address electrode A is biased to positive polarity potential for preventing a useless discharge, and initially a positive polarity sustaining pulse Ps1 is applied to all sustaining electrodes X. Succeedingly, the sustaining pulse Ps1 is applied successively to the sustaining electrode Y and the sustaining electrode X. Thereafter, the sustaining pulse Ps is applied alternately to the sustaining electrodes Y and X. In such a case, the pulse widths (w) of the first to third sustaining pulses Ps1 applied in the starting stage of the sustaining period TS are shorter than the pulse widths (w) of fourth sustaining pulses Ps and after that. Thus, a surface discharge hardly occurs in a non-lighting cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an AC type PDP.
(Plasma Display Panel) is applied to a display by erasing addressing.

2. Description of the Related Art PDPs are self-luminous thin display devices using a substrate pair as a support, and have been widely used in applications such as television images and computer monitors with the practical use of color screens. . It is also attracting attention as a large screen flat-type device for HDTV.

[0003]

2. Description of the Related Art In a matrix display type PDP,
The memory effect is used to maintain the lighting state of cells serving as display elements (sustain). The AC PDP is structured so as to structurally have a memory function by coating electrodes with a dielectric. At the time of display by an AC type PDP, line-sequential addressing is performed to form a state in which only the cells to be lit (emit light) are charged, and then the lighting sustaining voltage Vs of alternating polarity is applied to all the cells at once.
Is applied. The lighting maintenance voltage Vs satisfies the expression (1).

Vf-Vwall <Vs <Vf (1) Vf: discharge starting voltage Vwall: wall voltage In a cell having wall charges, the wall voltage Vwall is superimposed on the lighting sustaining voltage Vs, so that the effective voltage applied to the cell ( Discharge occurs when Veff exceeds the discharge start voltage Vf. Since the wall charges having the polarity opposite to the previous polarity are re-formed by the discharge, the discharge is generated again when the lighting sustaining voltage Vs having the polarity opposite to the previous time is applied. By shortening the application period of the lighting sustain voltage Vs, a visually continuous lighting state can be obtained. The luminance of the display depends on the total light emission amount (integrated light emission intensity) during the lighting sustain period.

Generally, a sustain pulse having a peak value corresponding to the lighting sustain voltage Vs is alternately applied to a pair of electrodes. The polarity of the sustain pulse is constant, but the polarity of the relative voltage between the electrodes is inverted each time it is applied. The frequency of the sustain pulse is fixed, and the number of sustain pulses (ie, the number of discharges) is set according to the luminance. Inevitably, the higher the luminance, the longer the lighting maintenance period. Note that there is also a form in which sustain pulses having different polarities (the sum of peak values is the lighting sustaining voltage Vs) are simultaneously applied to the pair of electrodes.

[0006]

Conventionally, in the case where addressing of a selective erasing type (erasing addressing) in which a discharge for charge erasing is generated only in cells which do not need to be lit after the entire screen is uniformly charged once. However, there is a problem that there is a cell that is turned on when a sustain pulse is applied, even though the cell does not need to be turned on. In other words, even if the wall charges of the cells that do not need to be lit are erased normally by erase addressing, if the space charges generated by the discharge for erasing remain excessively, discharge occurs in the cells that do not need to be lit due to the priming effect. In some cases, wall charges were reformed.

SUMMARY OF THE INVENTION It is an object of the present invention to prevent erroneous lighting during the lighting maintaining period and realize a high-quality display without flicker.

[0008]

According to the present invention, the discharge probability in the starting stage in the lighting sustain period is made lower than that in the succeeding stages within a range where lighting leakage does not occur. This allows
In a cell that does not need to be lit and does not have an appropriate amount of wall charge, no discharge occurs, and even if it occurs, the cell is weak, so that the wall charge is not reformed.

According to the method of the first aspect of the present invention, all the cells constituting the screen are charged with wall charges, and only the cells which do not need to be lighted are erased from the wall charges. A method for driving an AC-type PDP in which a voltage pulse for maintaining lighting is periodically applied, wherein a pulse width of a certain number of the voltage pulses applied at a start stage of the lighting maintaining period is set to be larger than other voltage pulses. Is also shortened.

According to a second aspect of the present invention, the peak value of a certain number of the voltage pulses applied at the start stage of the lighting sustain period is made lower than other voltage pulses. 4. The driving method according to claim 3, wherein the predetermined number is one.
2, or 3.

[0011]

FIG. 1 is a configuration diagram of a plasma display device 100 according to the present invention. Plasma display device 100
Is a drive unit 80 for selectively lighting an AC type PDP 1 which is a matrix type color display device and a large number of cells C constituting a screen (screen) SC.
And a wall-mounted television receiver,
It is used as a monitor for computer systems.

The PDP 1 has a pair of sustain electrodes X and Y as first and second main electrodes arranged in parallel with each other.
Address electrodes A as sustain electrodes X and Y
PDP with a three-electrode surface discharge structure arranged so as to intersect
It is. The sustain electrodes X and Y extend in the row direction (horizontal direction) of the screen SC, and the one sustain electrode Y is used as a scan electrode for selecting a cell in a row unit at the time of addressing. The address electrodes A extend in the column direction (vertical direction), and are used as data electrodes for selecting cells in column units. The area where the sustain electrode group and the address electrode group intersect is the display area, that is, the screen SC
It is.

The drive unit 80 includes a controller 81,
It has a frame memory 82, a data processing circuit 83, a subfield memory 84, a power supply circuit 85, an X driver 87, a Y driver 88, and an address driver 89.
To the drive unit 80, field data Df for each pixel indicating the luminance level (gradation level) of each color of R, G, B is input together with various synchronization signals from an external device such as a TV tuner or a computer.

The field data Df is once stored in a frame memory 82 and then sent to a data processing circuit 83. The data processing circuit 83 is data conversion means for setting a combination of subfields to be turned on, and outputs subfield data Dsf corresponding to the field data Df. The subfield data Dsf is stored in the subfield memory 84. The value of each bit of the subfield data Dsf is information indicating whether or not it is necessary to light a cell in the subfield.

The X driver circuit 87 applies a drive voltage to the sustain electrode X, and the Y driver circuit 88 applies a drive voltage to the sustain electrode Y. Address driver circuit 89
Applies a drive voltage to the address electrode A according to the subfield data Dsf. A predetermined power is supplied from the power supply circuit 85 to these driver circuits.

FIG. 2 is a perspective view showing the internal structure of the PDP 1. In the PDP 1, a pair of sustain electrodes X and Y are arranged for each row L on the inner surface of the glass substrate 11 on the front side. Row L is a horizontal cell column on the screen.
Each of the sustain electrodes X and Y is composed of a transparent conductive film 41 and a metal film (bus conductor) 42, and is covered with a dielectric layer 17 made of low melting point glass and having a thickness of about 30 μm. On the surface of the dielectric layer 17, a protective film 18 made of magnesia (MgO) and having a thickness of several thousand angstroms is provided. The address electrodes A are arranged on a base layer 22 that covers the inner surface of the glass substrate 21 on the rear side, and have a thickness of 10 mm.
It is covered with a dielectric layer 24 of about μm. On the dielectric layer 24, a partition 29 having a height of 150 μm and having a linear band shape in a plan view is provided between each address electrode A. These partition walls 29 divide the discharge space 30 in the row direction for each sub-pixel (unit light-emitting region), and define the gap size of the discharge space 30. Then, R, G, and R for color display are covered so as to cover the inner surface on the back side including the upper side of the address electrode A and the side surface of the partition wall 29.
The three color phosphor layers 28R, 28G, and 28B are provided. The arrangement pattern of the three colors is a stripe pattern in which cells in one column have the same emission color and adjacent columns have different emission colors.

The discharge space 30 is filled with a discharge gas in which xenon is mixed with neon as a main component (filling pressure is 5
00 Torr), the phosphor layers 28R, 28G, 28B are locally excited by ultraviolet light emitted by xenon during discharge to emit light. One pixel (pixel) of the display is composed of three sub-pixels arranged in the row direction. The structure within each sub-pixel is a cell (display element). Since the arrangement pattern of the partition walls 29 is a stripe pattern, the discharge space 3
The portion corresponding to each column of 0 is continuous in the column direction across all the rows L. Therefore, the dimension of the electrode gap (referred to as an inverted slit) between adjacent rows L is sufficiently larger than the surface discharge gap (for example, a value in the range of 80 to 140 μm) of each row L, and the discharge coupling in the column direction is improved. The value is selected to be a value that can be prevented (for example, a value within a range of 400 to 500 μm).

Next, a driving method in the plasma display device 100 will be described. FIG. 3 is a diagram showing a field configuration and a driving sequence. For example, in the display of a television image, in order to reproduce gradation by binary lighting control, each field f of a time series as an input image (a subscript of a code represents a display order) is, for example, 8 sub-frames. s
f1, sf2, sf3, sf4, sf5, sf6, sf
7, sf8. In other words, each field f forming the frame F is divided into eight sub-frames sf1 to sf1
Replace with the set of f8. However, when playing back non-interlaced images such as computer output,
Each frame is divided into eight. Then, the relative ratio of luminance in these subfields sf1 to sf8 is 1: 2:
Weighting is performed so as to be 4: 8: 16: 32: 64: 128, and the maximum number of times of sustain light emission of each of the subfields sf1 to sf8 is set. Since 256 levels of luminance can be set for each color of RGB by a combination of lighting / non-lighting in subfield units, the number of colors that can be displayed is 25.
The 6 ^3. It is not necessary to display the subfields sf1 to sf8 in the order of luminance weight. For example, optimization such as placing the subfield sf8 having a large weight in the middle of the display period can be performed.

The sub-field period Tsf allocated to each of the sub-fields sf1 to sf8 is for the purpose of securing a reset period TR for equalizing the charged state of the entire screen, an address period TA for erasing addressing, and a luminance according to the gradation level. And a sustain period TS for maintaining a lighting state by applying a voltage specific to the present invention. In each subfield period Tsf, the lengths of the reset period TR and the address period TA are constant regardless of the luminance weight, but the length of the sustain period TS increases as the luminance weight increases.

In the reset period TR, a first step of applying a positive voltage pulse Pr to the sustain electrode X, a positive voltage pulse Prx to the sustain electrode X, and a negative voltage pulse to the sustain electrode Y Pry
Is applied, wall charges having a predetermined polarity are formed in the “last time lit cell” lit in the immediately preceding subfield and the “last time non-lit cell” not lit. That is, after inverting the polarity of the wall charge of the previously lit cell, all the cells are subjected to a two-stage process of forcibly generating a discharge by applying a voltage about twice the lighting sustain voltage to the previously non-lit cell. Charge evenly. Voltage pulse Prx,
When Pry is applied, no discharge occurs because the wall charge reduces the applied voltage in the previously lit cell. In the first step, the address electrode A is biased to a positive potential of about 50 to 120 V to prevent unnecessary discharge between the address electrode A and the sustain electrode X.

Subsequent to the second step, a positive voltage pulse Prs is applied to the sustain electrode Y to increase surface uniformity in all the cells in order to improve the uniformity of charging. The charging polarity is reversed by this surface discharge. After that, the potential of the sustain electrode Y is gradually reduced to a predetermined value in order to avoid the loss of charge.

In the address period TA, each row is sequentially selected one by one from the first row, and a negative scan pulse Py is applied to the corresponding sustain electrode Y. At the same time as selecting the row, the address pulse Pa of the positive polarity is applied to the address electrode A corresponding to the cell which does not need to be lit (the non-lit cell this time).
Is applied. Address pulse Pa in the selected row
In the cell to which is applied, the counter discharge occurs between the sustain electrode Y and the address electrode A, and the wall charges of the dielectric layer 17 disappear. At the time of the application of the address pulse Pa, positive wall charges exist near the sustain electrode X.
The address pulse Pa is canceled by the wall voltage, and no discharge occurs between the sustain electrode X and the address electrode A. Such erasing addressing is suitable for high-speed operation, because it does not require the regeneration of charges unlike the writing method. The address time per row is about 1.3 μs.

In the sustain period TS,
To prevent unnecessary discharge, the address electrode A is biased to a positive potential, and a positive sustain pulse Ps1 is first applied to all the sustain electrodes X. Subsequently, a sustain pulse Ps1 is sequentially applied to the sustain electrode Y and the sustain electrode X. Thereafter, a sustain pulse Ps is alternately applied to the sustain electrodes Y and the sustain electrodes X.

In the present embodiment, the pulse width w1 of the first to third sustain pulses Ps1 applied at the start stage of the sustain period TS is larger than the pulse width w of the other fourth and subsequent sustain pulses Ps. Is also short. This makes it difficult for surface discharge to occur in the non-lighted cells this time,
Even if it occurs, the wall charge is not re-formed because the voltage application time is short. On the other hand, in the cells lit this time, since an appropriate amount of wall charges exists at the end of the addressing, surface discharge occurs. The pulse width w1 may be selected so that sufficient wall charges remain in the lighting cell this time for maintaining the lighting thereafter.

FIG. 4 is a drive voltage waveform diagram during a sustain period TS according to the second embodiment. In the present embodiment, in order to prevent erroneous lighting of the non-lighting cell this time, the sustain period TS
The peak value Vs' of the predetermined number of sustain pulses Ps2 at the start stage of the above is changed to the peak value Vs of the sustain pulse Ps at the subsequent stage.
Lower than Practical range of peak value difference is 5-20V
It is.

In the example of FIG. 4A, only the peak value of the first sustain pulse Ps2 applied to the sustain electrode X is low. In the example of FIG. 4B, the peak values of the first to third sustain pulses Ps2 are lower than others.
As the number of times of application of the sustain pulse Ps2 having a low peak value is increased, erroneous lighting can be more reliably prevented, but it is disadvantageous in securing the luminance of the currently lit cell. In a subfield having a small luminance weight, the influence of erroneous lighting is small, but a decrease in luminance is conspicuous. Therefore, for example, only a first subfield having a small luminance weight and a first to a second subfield having a large luminance weight are used. A sustain pulse Ps2 having a low peak value for each subfield up to the fifth, and so on.
Can be selected. The number of sustain pulses Ps2 applied to all subfields may be common. Note that such selection of the number of applied voltages can be similarly performed when the above-described pulse width is changed.

In the above embodiment, the address pulse P is used to reduce the deterioration of the phosphor due to the address discharge.
a is defined as positive polarity, and the polarity of other pulses is set.
An example was given in which the driving circuit was simplified by applying a positive sustain pulse to only one of the sustain electrodes, but the present invention is not limited to this. That is, the polarity of the applied voltage can be changed.

[0028]

According to the first to third aspects of the present invention,
It is possible to prevent erroneous lighting during the lighting maintenance period and to realize a high-quality display without flicker.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a plasma display device according to the present invention.

FIG. 2 is a perspective view showing an internal structure of the PDP.

FIG. 3 is a diagram showing a field configuration and a driving sequence.

FIG. 4 is a drive voltage waveform diagram in a sustain period TS according to a second embodiment.

[Description of Signs] 1 PDP C cell SC screen Ps, Ps1, Ps2 Sustain pulse (voltage pulse) TS sustain period (lighting sustain period) w, w1 Pulse width Vs, Vs' peak value

Claims (3)

[Claims] In a lighting sustain period after wall charges are charged to all cells constituting a screen and only the cells which do not need to be lighted are erased from the wall charges, lighting is commonly performed for all the cells. A method of driving an AC-type PDP that periodically applies a voltage pulse, wherein a pulse width of a certain number of the voltage pulses to be applied at a start stage of the lighting sustain period is shorter than other voltage pulses. To drive an AC-type PDP. 2. A method for charging all the cells constituting a screen during a lighting maintenance period after erasing the wall charges only for cells which do not need to be lit, to maintain lighting for all the cells. A method of driving an AC-type PDP that periodically applies a voltage pulse, wherein a peak value of a certain number of the voltage pulses applied at a start stage of the lighting sustain period is lower than other voltage pulses. To drive an AC type PDP. 3. The method of driving an AC type PDP according to claim 1, wherein the predetermined number is one, two, or three.