JPH11103577A - Inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relatively simply reduce a wiring inductance between a main capacitor and an inverting element, by adopting as the main capacitor a plurality of capacitors having capacitances and withstand voltages divided at respective inverting elements of a main circuit, and dispersively disposing the respective capacitors near at hand at the respective elements and directly connecting them. SOLUTION: Capacitors CM1 , CM2 having relatively small capacitances and low withstand voltages are connected in parallel near at hand at respective IGBTs. That is, a main capacitor is dispersed to a plurality of capacitors CM1 , CM2 having the capacitances and withstand voltages divided at the respective IGBTs. The capacitors CM1 , CM2 are connected between collectors and emitters of the IGBG. According to this structure, since the capacitors CM1 , CM2 are dispersed at the respective IGBT elements, its size can be reduced by decreasing the capacitance and by half the withstand voltage. Thus, the capacitors CM1 , CM2 are disposed near at hand at the IGBT to shorten a length of wirings therebetween, and hence parasitic inductance therebetween can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-capacity inverter which forms a main circuit by connecting inverting elements in parallel or the like, and more particularly to a main capacitor for protecting the inverting element from surge voltage breakdown and an inversion. The present invention relates to a connection method with an element.

[0002]

2. Description of the Related Art As a capacitor component of a main circuit of an inverter, there is a main capacitor provided in a DC circuit. In a large-capacity inverter, a main capacitor is combined into a capacitor bank at one location, and DC power is supplied to an inverse conversion element such as an IGBT by a bus bar.

The main circuit of the inverter is an IGBT
In order to suppress the surge voltage generated between the collector and the emitter due to the high-speed switching of the inverse conversion element, a snubber circuit combining a capacitor, a resistor and a diode is provided. There are various configurations of this snubber circuit as shown in FIG. 3, but a structure is employed in which a capacitor is connected in series with a diode and connected in parallel with an inversion element. In a large-capacity inverter, the circuit configuration shown in FIG. 1C is often used because of the advantage that the amount of heat generated by the snubber resistor is small.

[0004]

The main circuit of the inverter is configured, for example, for one phase in FIG. This configuration corresponds to (c) of FIG. 3, and an IGBT is used for the inverse conversion element.

In this configuration, wiring for connecting an IGBT or a capacitor is directly related to a measure against a surge voltage applied to an inversion element such as an IGBT. In particular, a MOS gate device such as an IGBT has a very high switching speed, so that the current change rate di / dt of the collector current I _C becomes extremely high at the time of turn-on or turn-off switching.
On the other hand, the wiring of the main circuit parasitic inductance L _M, L _S is always present.

Due to the existence of this parasitic inductance, I
During switching of the GBT, surge voltages ΔV _CE1 and ΔV _CE2 expressed by the following equations are generated between the collector and the emitter at the turn-off timing as shown in FIG. In the figure, I _C
Is the collector current, V _CE is the collector-emitter voltage,
I _OFF is the current to be cut off at turn-off, and V _CC is the voltage of the main capacitor.

[0007]

ΔV _CE1 = L _S × di / dt ΔV _CE2 = √ (L _M / C _S ) × I _{OFF According to the} above equation, the surge voltage applied to the IGBT depends on the parasitic inductance L existing in the wiring of the main circuit. _M , L _S and the current change rate di / dt. Therefore, the following measures are taken to protect the IGBT from surge voltage breakdown.

(A) The wiring inductance is reduced.

(B) The current change rate is reduced.

Of these methods, the method (B) can be easily realized by increasing the gate resistance, but causes an increase in switching loss and lowers the inherent high-speed switching performance of the IGBT. .
In particular, in high frequency applications, there is a limit due to securing dead time and the like.

On the other hand, in the method (A), since the snubber circuit can be relatively reduced in size, the wiring inductance L _S itself can be reduced relatively easily. However, capacitors, etc. when connecting a capacitor bank and an IGBT busbars is relatively large, the reduction of the inductance L _M is difficult in the wiring length increases accordingly. In order to suppress the increase in the parasitic inductance, the following measures are taken.

(C) The arrangement positions of the capacitor bank and the IGBT are brought as close as possible.

(D) Use a twisted pair wire, a parallel conductor, or the like to bring the reciprocating line closer.

However, the method (C) has structural limitations. Further, in the method (D), it is difficult to ensure insulation performance between conductors, and there is a difficulty in manufacturing to obtain the structure.

An object of the present invention is to provide an inverter having a structure that can relatively easily reduce the wiring inductance between a main capacitor and a reverse conversion element.

[0016]

SUMMARY OF THE INVENTION According to the present invention, a surge capacitor due to a parasitic inductance is suppressed by dispersing a main capacitor in the vicinity of an inverting element and obtaining a connection individually with the inverting element. , Characterized by the following structure.

A main circuit is formed by connecting inverting elements in parallel, etc. In an inverter in which a snubber circuit is provided in parallel with each inverting element, a main capacitor serving as a DC power supply is divided for each inverting element in the main circuit. A plurality of capacitors having a capacitance and a withstand voltage are provided, and these capacitors are dispersed and arranged in the immediate vicinity of each of the inversion elements, and are directly connected to the inversion elements.

A main circuit is formed by connecting inverting elements in parallel, etc. In each inverter, a snubber circuit is provided in parallel, and a main capacitor serving as a DC power supply is connected to each inverting element of the main circuit. A plurality of capacitors having a divided capacity and a withstand voltage, each of which has a structure that is integrated into a printed circuit board or a module of each of the snubber circuits, and which is connected through a connection conductor between each of the snubber circuits and the inverse conversion element. It is characterized by a structure for obtaining a connection with

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a one-phase configuration of a main circuit showing an embodiment of the present invention. Portions figure differs from FIG. 4, in place of the configured main capacitor C _M in the capacitor bank, the capacitor CM ₁ of a relatively small capacity and small breakdown voltage,
The point is that CM ₂ is connected in parallel in the latest for each IGBT.

That is, in the conventional structure, a capacitor concentrated as a capacitor bank is distributed to a plurality of capacitors having a capacity and a withstand voltage divided for each IGBT, and each capacitor is directly connected between the collector and the emitter of the IGBT. Structure.

With this structure, the capacitors CM ₁ and CM ₂
Since the IGBTs are dispersed for each IGBT element, the size is reduced by reducing the capacitance and halving the withstand voltage. Accordingly, the wiring length between the IGBTs can be shortened even though the IGBTs are arranged immediately adjacent to the IGBTs, thereby reducing the parasitic inductance therebetween. Can be. That is,
Without intervention parasitic inductance L _M of relatively a large value between conventional main condenser and IGBT, it can suppress a surge voltage V _CE2 of the formula.

Also, when a twisted pair wire is used as the wiring, the withstand voltage of the capacitors CM ₁ and CM ₂ is not higher than the voltage V _CC.
, It is easy to secure the dielectric strength.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. This figure differs from FIG. 1 in that capacitors CM ₁ and CM ₂ are integrated into a snubber circuit.

In the snubber circuit, a capacitor C _S and a diode D _S are formed as a printed board or a module.
Connected for each GBT. This snubber circuit has a capacitor C
M ₁ and CM ₂ are integrally incorporated, and are connected to the IGBT through connection conductors between each snubber circuit and the inverse conversion element.

According to this structure, in addition to the functions and effects of the structure of FIG. 1, wiring for connecting the capacitors CM ₁ and CM ₂ to the IGBT and the work thereof are not required, and the size of the device is reduced. be able to.

In the above embodiments, the snubber circuit can obtain the same operation and effect even when the circuit configuration is changed to another circuit configuration in FIG.

[0027]

As described above, according to the present invention, the main capacitors are dispersed and arranged in the immediate vicinity of the reverse conversion element so as to be individually connected to the reverse conversion element, thereby suppressing the surge voltage of the reverse conversion element. Therefore, there is an effect that the structure for reducing the parasitic inductance can be realized relatively easily. Further, the reliability of the device itself can be improved and the device can be reduced in size.

[Brief description of the drawings]

FIG. 1 is a main circuit configuration diagram (for one phase) showing an embodiment of the present invention.

FIG. 2 is a main circuit configuration diagram (1) showing another embodiment of the present invention.
Phase).

FIG. 3 is an example of a snubber circuit of an inverse conversion element.

FIG. 4 shows conventional main circuit wiring and parasitic inductance.

FIG. 5 is a switching waveform at the time of turn-off.

[Explanation of symbols]

IGBT ... inverse conversion device CM _1, CM ₂ ... split capacitor L _M, L _S ... resistance of the diode R _S ... snubber circuit of a capacitor D _S ... snubber circuit of the parasitic inductance C _S ... snubber circuit

Claims (2)

[Claims] A main circuit is formed by connecting inverting elements in parallel or the like, and in each inverter, a snubber circuit is provided in parallel. Inverters each include a main capacitor serving as a DC power supply for each inverting element of the main circuit. Multiple capacitors with divided capacity and withstand voltage,
An inverter having a structure in which each of these capacitors is dispersed and disposed in the immediate vicinity of each of the inverse conversion elements and is directly connected to the inverse conversion element. 2. An inverter having a snubber circuit connected in parallel to each of the inverters, wherein a main capacitor serving as a DC power source is provided for each of the inverters in the main circuit. Multiple capacitors with divided capacity and withstand voltage,
An inverter having a structure in which each of these capacitors is integrally incorporated in a printed circuit board or a module of each of the snubber circuits, and which is connected to the inversion element through a connection conductor between each snubber circuit and the inversion element.