JPH11102407A - Differential circuit, ota and squaring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure a wide linear input voltage range by preparing plural differential circuits, including each differential pair where one of two transistors TR to which the differential input signals are applied is driven by a constant current source with the other TR constructing an output part, securing the cross connection between the input parts of the differential circuits and using differential current as the output of an output pair. SOLUTION: The input differential signals are applied to TR M1 and M2 which construct an input pair, and the TR M2 is driven by a constant current source. Then a 1st differential circuit consists of a differential pair having its output part formed by the TR M1, a constant current source Io which drives the differential pair and a TR M3 which supplies a current to the source Io. Similarly, a 2nd differential circuit consists of the TR M4 and M5 which construct an input pair, the source Io and a IR M6 which supplies current to the source Io. The cross connection is secured between the input pairs (TR M1, M2, M4 and M5) and the differential currents of an output pair (output differential currents of TR M1 and M4) are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a differential circuit, and more particularly to a differential circuit formed on a semiconductor integrated circuit and having excellent linearity and a square circuit for squaring a differential input voltage.

[0002]

2. Description of the Related Art For example, the following literature is referred to as a CMOS (Complementary MOS) OTA (Operational Transconductance Amplifier). Reference 1. Nobukazu Takai, Akira Hyogo, Keitaro Sekine "CMOS-O
A Proposal on Linearization of TA "(ECT-95-4), IEICE Electronics Circuit Study Group, January 19, 1995.

As a conventional OTA, a CMOS shown in FIG.
There is OTA.

First, the prior art will be described. However,
In the above document 1, the circuit analysis is insufficient and it is not enough to understand the circuit operation. Therefore, the present inventor independently performs the circuit analysis.

[0005] In FIG. 5, assuming that the matching of elements is good, channel length modulation and the body effect are ignored, and the relationship between the drain current and the gate-source voltage of the MOS transistor follows the square law, the MOS transistor the drain current I _D is represented by the following formula (1).

I _D = β (V _GS −V _TH ) ² (1)

Here, β is a transconductance parameter, and is expressed as β = μ (C _ox / 2) (W / L). Here, μ is the effective mobility of carriers, _Cox is the gate oxide film capacity per unit area, and W and L are the gate width and gate length, respectively. V _GS is a gate-source voltage, and V _TH is a threshold voltage.

In FIG. 5, if V _B = (V ₁ + V ₂ ) / 2 (2) V ₁ -V ₂ = V _i (3), drain currents I _D1 and I _D1 of MOS transistors M1 and M2 are set. _D2 is given by the following equations (4) and (5).

[0009] _{I D1 = β (V i /} 2 + V B -V s -V TH) 2 ... (4) I D2 = β (-V i / 2 + V B -V s -V TH) 2 ... (5)

[0010] The drain current I _D3 of the MOS transistor M3 is given by the following equation (6).

I _D3 = β (V _B −V _S −V _TH ) ² = I _B1 (6)

Here, since I _D1 + I _D2 + I _D3 + I _D4 = I _B (7), the differential output current ΔI is expressed by the following equation (8).

ΔI = I _D1 −I _D2 = 2βV _i (V _B −V _s −V _TH ) = 2V _i (I _B1 / β) ^1/2 (8)

[0014] Therefore, the differential output current ΔI is proportional to the differential input voltage V _i. That is, the OTA operates linearly. However, the MOS transistor M4 has an MO
According S transistors M1, M2 are square law, so that a current flows, which bypasses the current to a constant current I _B. Therefore, the drain current I _D4 of the MOS transistor M4,

[0015] _{I D4 = I B - (I} D1 + I D2 + I D3) = I B -3I B1 -βV i 2/2 ... Motomari and (9), the differential input voltage V in MOS transistor M4
A bypass current including a current component proportional to the square of _i flows.

[0016] than I _D4 ≧ 0, the operation input voltage _{range, | V i | ≦ {2} (I B -I B1) / β} becomes ^1/2 (10).

Further, the midpoint voltage of the input signal V ₁ and V ₂ (V ₁
+ V ₂₎ / 2, in FIG.
As shown in the figure, the differential MOS transistor pair M4, M5,
And two differential circuits consisting of M6 and M7.

[0018]

As described above, the conventional OTA realizes a completely linear operation, but requires a circuit for generating a midpoint voltage of an input signal.

In analog signal processing, OTA and 2
The multiplication circuit is an essential function block that is indispensable. In particular, the need for an OTA or a square circuit having a linear or square characteristic over a wide input range is increasing.

Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a CMOS OT
An object of the present invention is to provide an OTA and a squaring circuit which secures a wide linear input voltage range or a wide input voltage range having a squared characteristic in a CMOS squaring circuit.

[0021]

In order to achieve the above object, according to the OTA of the present invention, a differential input signal is applied to two transistors forming an input pair, one of the transistors is driven by a constant current source, and the other is driven by a constant current source. A pair of transistors comprising an output, a constant current source for driving the differential pair, and a transistor for supplying a current to the constant current source. The inputs are cross-connected, and the difference current is output to the output of the output pair. , And two differential circuits. The squaring circuit of the present invention uses the sum current as the output of the output pair.

[0022]

Embodiments of the present invention will be described below. In a preferred embodiment of the OTA of the present invention, a differential input signal (V _{i in} FIG. 1) is applied to two transistors (M 1 and M 2 in FIG. 1) constituting an input pair, and One transistor (M2 in FIG. 1) is driven by a constant current source ( _{Ib in} FIG. 1), and the other transistor (M1 in FIG. 1) drives a differential pair constituting an output and this differential pair. A constant current source (I _{0 in} FIG. 1);
A first differential circuit including a transistor (M3 in FIG. 1) for supplying a current to a constant current source for driving the differential pair;
It has two differential pairs (M4 and M5 in FIG. 1) constituting an input pair, and a constant current source (I _{b in} FIG. 1) for driving one transistor (M5 in FIG. 1) and a differential pair (FIG. 1). M4, M5 of 1)
Driving a constant current source and (I ₀ in FIG. 1), two differential of the second differential circuit Do from the transistor pouring current to a constant current source (M6 of FIG. 1) which drives the differential pair Circuit and an input pair (transistors M1, M2 and M4, M4
5) are cross-connected, and the input pair of the first differential circuit (M4 and M5 in FIG. 1) is connected to the input pair of the second differential circuit (M4 and M5 in FIG. 1).
1, M2) and a differential current of the output pair (the output difference current I ⁻ = of the transistors M1 and M4) is applied.
I _C1 −I _C4 ).

In a preferred embodiment of the squaring circuit of the present invention, the sum current of the output pairs of the two differential circuits (the sum current of the outputs of the transistors M1 and M4, I ⁺ = (I _C1 +
I _C4 )) is output.

One of the two transistors constituting the differential pair is driven by a constant current, and the third transistor is connected to the tail current of the differential pair, whereby the current can be bypassed, and a floating transistor is realized. You. Therefore, assuming the square law of the MOS transistor,
By cross-connecting the inputs of the two circuits and outputting this differential current with a current mirror circuit, a completely linear OTA can be obtained, and a squaring circuit can be realized by adding currents.

The squaring circuit of the present invention is preferably
In the second embodiment, two tokens forming an input pair
The differential input signal (FIG. 3) is applied to the transistors (M1, M2 in FIG. 3).
V _i) Are applied to form an output pair and a third transistor
The star (M3 in FIG. 3) is a constant current source (I3 in FIG. 3)._bDriven by
The gate receives the input signal (V_i) The midpoint voltage is marked.
Be added. Then, these three transistors (M in FIG. 3)
1, M2, M3) (I in FIG. 3)₀)
This constant current source (I in FIG. 3)₀)
4 (M4 in FIG. 3)
A circuit comprising an output pair (transistors M1, M2 of FIG. 3)
2) sum current (I_D1+ I_D2) Is output. Also the fourth M
OS transistor (M4 in FIG. 3) and current mirror circuit
From the fifth transistor (M5 in FIG. 3)
A square output of the signal voltage is obtained.

[0026]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a circuit diagram of a CMOS circuit according to an embodiment of the present invention.
It is a figure showing composition of TA. Referring to FIG. 1, in a first embodiment of the present invention, a pair of transistors M1 and M1 whose sources are commonly connected and a differential input signal V _i is applied between gates is provided.
The constant current source _Ib is connected to the drain of one transistor M2 to be driven, and the other transistor M2 is driven.
A differential transistor pair to take out the output from the first collector, a constant current source I ₀ for driving the differential transistor pair M1, M2, and connect the source power supply V _DD, a gate to the drain of the transistors M2, the transistor drain M
1, M2 and transistor M3 pouring current commonly connected to the constant current source I ₀ to the constant current source I _0, comprising a first C
It includes a MOS differential circuit and a second CMOS differential circuit having the same configuration as the first CMOS differential circuit. That is, the second
'S CMOS differential circuit, two differential transistor pairs M4, M5 constituting the input pair, a constant current source I _b for driving the one transistor M5, the differential transistor pair M4, M
5 a constant current source I ₀ that drives, a transistor M6 Metropolitan pouring current to the constant current source Io. In each of the input pairs M1, M2 and M4, M5 of the two differential circuits, the gates of the transistors M1, M5 are commonly connected, the gates of the transistors M2, M4 are commonly connected, and the transistors M1, M4 forming an output pair Output difference current (OTA)
Alternatively, a sum current (squaring circuit) is output.

Each C constituting the CMOS OTA
For the MOS differential circuit, the drain currents I _D1 and I _D2 of the transistors M1 and M2 are given by the following equations (11) and (12).

I _D1 = β (V _i + V _GS2 −V _TH ) ² (11) I _D2 = β (V _GS2 −V _TH ) ² = I _b (12)

However, since I _D1 + I _D2 + I _D3 = I _o (13), I _D1 is given by the following equation (14).

I _D1 = βV _i ² + 2βV _i (I _b / β) ^1/2 + I _b = β ｛V _i + (I _b / β) ^1/2 ｝ ² (14)

The drain current I _{D3 of the} transistor M3
Is given by the following equation (15).

[0033] ^{_{I D3 = I o -βV i 2}} -2βV i (I b / β) 1/2 -2I b ... (15)

From I _D3 ≧ 0, the operating input voltage range is

− (I _b / β) ^1/2 − {(I _o −I _b ) / β} ^1/2 ≦ V _i ≦ − (I _b / β) ^1/2 + ΔI _o −I _b ) / Β｝ ¹ / ² … (16)

## EQU1 ##

[0037] Similarly, since the other CMOS differential circuit input voltage is applied in opposite phase, the drain current I _D4 of the transistor M4 is given by the following equation (17).

I _D4 = βV _i ² −2βV _i (I _b / β) ^1/2 + I _b = β ｛V _i − (I _b / β) ^1/2 ｝ ² (17)

From I _D6 ≧ 0, the operating input voltage range is

(I _b / β) ^1/2 − {(I _o −I _b ) / β} ^1/2 ≦ V _i ≦ (I _b / β) ^1/2 + {I _o −I _b ) / β ｝ ^1/2 … (18)

The output in Figure 2 current I _D1, I _D4 (and I _D1- I
_D4 , I _D1 + I _D4 ).

Therefore, the difference current ΔI between I _D1 and I _D4 is obtained by the following equation (19).

[0043] _{ΔI = I D1 -I D4 = 4V} i (I B1 / β) 1/2 ... (19)

Where | V _i | ≦ (I _b / β) ^1/2 (20)

As can be seen from the above equation (19), the differential output current Δ
I is proportional to the differential input voltage V _i in the range of the equation (20).
That is, the OTA operates linearly.

Further, if the sum current of I _D1 and I _D4 is obtained, the following equation (21) is obtained.

I _D1 + I _D4 = 2 (βV _i ² + I _b ) (21)

However, | V _i | ≦ (I _b / β) ^1/2 (20), which is a square circuit.

FIG. 3 shows a configuration of a squaring circuit according to a second embodiment of the present invention. Referring to FIG. 3, in the present embodiment, the midpoint voltage of the input voltage is obtained by dividing the resistance. First configuring the differential pair gates the differential input signal V _i is applied, a second
MOS transistors M1 and M2 form an output pair, the third MOS transistor M3 is connected to and driven by a constant current source _Ib , and has a gate to which a midpoint voltage of the input signal (V _i ) is applied. You. These three transistors M1, M
2, M3 fourth pouring current to the constant current source I ₀ which drives the
And a transistor M5 which forms a current mirror circuit with the fourth MOS transistor and outputs a mirror current of the fourth MOS transistor. Each drain current is obtained as in the conventional technique shown in FIG.

First, the drain currents I _D1 and I _D2 of the transistors M1 and M2 are given by the following equations (21) and (22).

I _D1 = β ｛V _i / 2 + (I _b / β) ^1/2 ｝ ² (21) I _D2 = β ｛V _i / 2− (I _b / β) ^1/2 ｝ ² ... ( twenty two)

The drain current I _{D3 of the} transistor M3
Is given by the following equation (23). I _D3 = I _b (23)

Transistors M1 and M2 forming an output pair
_Taking the sum of the drain currents I _D1 and I _D2 of
Holds.

[0054] _{I D1 + I D2 = βV i} 2/2 + 2I b ... (24)

Where | V _i | ≦ (I _b / β) ^1/2 (20)

As can be seen from the above equation (24), a square circuit is obtained.

Further, in the circuit shown in FIG. 3, the current value I _D4 flowing through the transistor M4 is obtained as follows.

I _D1 + I _D2 + I _D3 + I _D4 = I _o (25)

[0059] a _{since, I D4 = I o - (} I D1 + I D2 + I D3) = I o -3I b -βV i 2/2 ... (26)

However, | V _i | ≦ (I _b / β) ^1/2 (20) is obtained, and a bypass current including a current component proportional to the square of the differential input voltage flows through the transistor M4.

Therefore, as shown in FIG. 3, the transistor M5 operates as a mirror transistor of the transistor M4, and operates as a squaring circuit that outputs a current component proportional to the square of the input voltage.

The relationship between the drain currents I _{D1 to} I _{D4 of the} transistors M _{1 to} M ₄ and the sum current I _D1 + I _D2 in FIG.
As shown in FIG.

[0063]

As described above, according to the present invention, the following effects can be obtained.

The first effect of the present invention is that an OTA that performs a complete linear operation can be realized with a simple circuit configuration.
That's what it means. As a result, an ideal OTA having a completely linear input voltage range was realized.

The reason is that, in the present invention, a floating transistor is equivalently realized, and a difference current is obtained by using an output as a current mirror circuit.

A second effect of the present invention is that a circuit for performing a complete squaring circuit operation can be realized with a simple circuit configuration. As a result, an output current proportional to the square of the input voltage was obtained, and an ideal square circuit was realized.

The reason is that, in the present invention, a floating transistor is equivalently realized and a sum current is obtained by adding outputs.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a drain current of each transistor in the circuit shown in FIG.

FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 4 is a characteristic diagram illustrating a drain current of each transistor in the circuit illustrated in FIG. 3;

FIG. 5 is a diagram illustrating an example of a circuit configuration of a conventional CMOS OTA.

FIG. 6 is a diagram showing a configuration of a conventional CMOS OTA voltage dividing circuit.

[Explanation of symbols]

M1-M6 MOS transistor I ₀ a constant current source V _i input differential voltage

Claims (4)

[Claims] 1. A differential input signal is applied to two transistors forming an input pair, one of the two transistors is driven by a constant current source, and the other transistor is a differential pair forming an output. A constant current source for driving the differential pair, and two differential circuits each including a transistor for flowing a current into the constant current source. The inputs of the differential circuit are cross-connected, and the differential current is output to the output pair. OTA, characterized in that it is an output. 2. A squaring circuit according to claim 1, wherein a sum current of said two differential circuits is used as an output of an output pair. 3. A differential input signal is applied to two transistors forming an input pair to form an output pair, and a third transistor is driven by a constant current source to apply a midpoint voltage of the input signal. A differential circuit comprising a constant current source for driving the three transistors and a fourth transistor for supplying a current to the constant current source, and outputs a sum current of an output pair. 4. A squaring circuit according to claim 3, wherein a fifth transistor constituting a current mirror circuit together with the fourth transistor is used as an output.