JPH1098340A - Btl amplifying circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the high output of a BTL amplifying circuit. SOLUTION: When first and fourth output transistors 15 and 18 are turned on, a voltage at the connecting point of first and second driving transistors 19 and 20 drops and when second and third output transistors 16 and 17 are turned on, a voltage at the connecting point of third and fourth driving transistors 21 and 22 drops. Thereby a voltage difference between the collectors and emitters between first and second input transistors 2 and 3 and first and second current source transistors 13 and 14 is extended to prevent the saturation of the first and second current source transistors 13 and 14. Thus, the saturation voltage of the BTL amplifier circuit is decided by the saturation voltage between the collector and the emitter of the first to fourth output transistors 15 to 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a BTL amplifier circuit which prevents saturation of a transistor and achieves high output.

[0002]

2. Description of the Related Art Conventionally, as a power amplifier circuit, a BTL amplifier circuit that generates signals having phases opposite to each other from an input audio signal and drives a load with a BTL using the respective signals has been known. Such a BTL amplifier circuit is configured as shown in FIG. In FIG. 3, first, a connection point a between the driving transistors 4 and 5 and a connection point b between the output transistors 6 and 7 are connected in common, and a connection point c between the driving transistors 8 and 9 and a connection point d between the output transistors 10 and 11. Are connected in common.

In FIG. 3 having such a configuration, when a negative input signal is applied to the input stage amplifier 1, a negative signal is applied to the first input transistor 2 and a positive signal is applied to the second input transistor 3. Is applied. First input transistor 2
Turns off in response to a negative signal, the drive transistor 4 turns on and the drive transistor 5 turns off. Therefore, the output transistor 6 turns on and the output transistor 7 turns off. When the second input transistor 3 turns on, the drive transistor 8 turns off and the drive transistor 9 turns on. Therefore, the output transistor 10 turns off and the output transistor 11 turns on. Therefore, the output current flows in the order of the output transistor 6, the load 12, and the output transistor 11.

When a positive input signal is applied to the input stage amplifier 1, a positive signal is applied to the first input transistor 2 and a negative signal is applied to the second input transistor 3. When the first input transistor 2 is turned on in response to a positive signal, the drive transistors 4 and 5 are turned off and on, respectively. Therefore, the output transistors 6 and 7 are turned off and on, respectively. When the second input transistor 3 turns off in response to a negative signal, the drive transistors 8 and 9 turn on and off, respectively. Therefore, the output transistor 10
And 11 turn on and off, respectively. Therefore, the output current flows in the order of the output transistor 10, the load 12, and the output transistor 7.

As described above, when the output current flows in the order of the output transistor 6, the load 12, and the output transistor 11, or in the order of the output transistor 10, the load 12, and the output transistor 7, the load 12
It is driving.

[0006]

The BT shown in FIG.
The saturation voltage on the power supply voltage side of the L amplifier circuit is Vce6 (sa
t), Vce4 (sat) + Vbe6, or Vbe4
+ Vce13 (sat) is determined by the largest one. However, Vce6 (sat), Vce4 (s
at) and Vce13 (sat) are the collector-emitter saturation voltages of the output transistor 6, the driving transistor 4 and the current source transistor 13, and Vbe6 and Vce13 (sat)
be4 is a base-emitter voltage of the output transistor 6 and the drive transistor 4. Here, in order to drive the load, the output transistor 6 has a large current supply capability, and the size of the output transistor 6 is large. As the size of the transistor increases, the collector-emitter saturation voltage Vce (sat) decreases, so that Vce6 (sat) and Vb
e6 becomes smaller, and as a result, Vbe + Vce13 (s
at) is the largest. Therefore, the saturation voltage on the power supply voltage side of the BTL amplifier circuit is Vbe4 + Vce13 (sa
t). Similarly, the saturation voltage on the power supply voltage side of the third and fourth output transistors 10 and 11 is based on the base-emitter voltage V
be8 and the collector-emitter saturation voltage Vce14 (sat) of the current source transistor 14.

When the saturation voltage of the BTL amplifier circuit is determined as described above, the upper limit of the output signal swing is equal to the power supply voltage Vcc.
To Vbe4 + Vce13 (sat), and the lower limit is Vbe8 + Vce14 (s
at). Vbe + Vce (sa
t) is not negligible compared to the power supply voltage Vcc, so BTL
There is a problem that the full swing level of the output signal of the amplifier circuit is greatly restricted, and it is not possible to increase the output of the BTL amplifier circuit.

[0008]

SUMMARY OF THE INVENTION The present invention comprises a first and a second input transistor to which input signals having opposite phases are applied, and a first and a second transistor which are driven in accordance with an output signal of the first input transistor. A second driving transistor, a first current source transistor that supplies a bias current to the first and second driving transistors, and a second current source transistor that is SEPP-connected and is driven according to output signals of the first and second driving transistors. A first and a second output transistor, a third and a fourth drive transistor driven in accordance with an output signal of the second input transistor, a second current source transistor for supplying a bias current to the third and the fourth drive transistor, , SEPP-connected, and third and fourth output transistors driven according to output signals of the third and fourth drive transistors, A BTL amplifying circuit that BTL-drives a load by an output signal of the first and second output transistors and an output signal of the third and fourth output transistors, wherein a connection point between the first and second output transistors; A connection point between the third and fourth drive transistors is connected, and a connection point between the third and fourth output transistors and a connection point between the first and second drive transistors are connected. I do.

A resistor connected between the first and second driving transistors and having a connection point connected to a connection point between the third and fourth output transistors;
A resistor is connected between the driving transistors and is connected to a connection point between the first and second output transistors. According to the present invention, when the first and fourth output transistors are turned on, the voltage at the connection point of the first and second drive transistors is reduced, and when the second and third output transistors are turned on, the third and fourth output transistors are turned on. The voltage at the connection point of the fourth drive transistor decreases. Therefore, the voltage difference between the collector and the emitter of the first current source transistor and the second
The voltage difference between the collector and the emitter of the current source transistor can be widened. Therefore, the saturation of the first and second current source transistors can be prevented, and the saturation voltage of the BTL amplifier circuit can be determined by the collector-emitter saturation voltage of the first and third output transistors.

[0010]

FIG. 1 is a diagram showing an embodiment of the present invention. Reference numerals 15 and 16 denote first and second output transistors connected by SEPP (single-ended push-pull), 17 and 18 respectively. Are the third and fourth output transistors connected by SEPP, and 19 and 20 are the first and second output transistors.
A first and a second drive transistor, each of which drives an output transistor and whose connection point a is connected to a connection point d of the third and fourth output transistors 17 and 18;
Reference numerals 21 and 22 drive the third and fourth output transistors, and the third and fourth terminals whose connection point c is connected to the connection point b of the first and second output transistors 15 and 16.
It is a driving transistor. In FIG. 1, the same elements as those in FIG. 3 are denoted by the same reference numerals.

In FIG. 1, when a negative input signal is applied to the input stage amplifier 1, the output signal of the input stage amplifier 1 turns off the first input transistor 2 and turns on the second input transistor 3. Then, similarly to the operation described with reference to FIG. 3, the first and fourth output transistors 15 and 18 are turned on. However, in this case, the connection point a between the first and second drive transistors 19 and 20 and the third and fourth
The connection point d of the output transistors 17 and 18 is connected. When the fourth output transistor 18 is turned on, its collector voltage becomes a value close to the ground level.
Therefore, the emitter voltage of the first drive transistor 19 also becomes a value close to the ground level. First drive transistor 19
Becomes closer to the ground level, the base voltage becomes higher than the ground voltage by Vbe19. Here, Vbe 19 is a base-emitter voltage of the first drive transistor 19. Therefore,
The voltage difference between the collector and the emitter of the first current source transistor 13 increases, and the first current source transistor 13 is less likely to be saturated.

The third and fourth drive transistors 21
And 22 and the connection point b between the first and second output transistors 15 and 16 are connected to each other.
When the output transistor 15 is turned on, the emitter voltage of the fourth drive transistor 22 becomes a value close to the power supply voltage Vcc. Therefore, assuming that the base-emitter voltage of the fourth drive transistor 22 is Vbe22, the collector voltage of the second input transistor 3 is lower than the power supply voltage Vcc by Vbe22. Therefore, the voltage difference between the collector and the emitter of the second input transistor 3 increases, and the second input transistor 3 is hardly saturated.

As the negative input signal becomes larger, the collector voltage of the fourth output transistor 18 further approaches the ground level.
5 further approaches the power supply voltage Vcc, and the first current source transistor 13 and the second input transistor 3
The voltage difference between the collector and the emitter of the transistor widens. Therefore, the first current source transistor 13 and the second input transistor 3 are less likely to be saturated.

Further, since a large output current flows through the load 12 in response to the large input, the collector voltage of the first output transistor 15 increases and the collector voltage of the fourth output transistor 18 decreases due to the voltage drop of the load 12. Then, the voltage difference between the collector and the emitter of the first and fourth output transistors 15 and 18 becomes smaller. This voltage difference is the first
When the voltage becomes lower than the collector-emitter saturation voltage of the fourth and fourth output transistors 15 and 18, the first and fourth output transistors 15 and 18 become saturated. Therefore, for a negative input signal, the saturation voltage of the BTL amplifier circuit of FIG.
It is determined by the saturation voltage between the emitters.

Conversely, when a positive input signal is applied to the input stage amplifier 1, the output signal of the input stage amplifier 1 turns on the first input transistor 2 and turns off the second input transistor 3. Therefore, the second and third output transistors 16 and 17 are turned on. Here, a connection point c between the third and fourth drive transistors 21 and 22 and a connection point d between the first and second output transistors 15 and 16 are connected.
When the second output transistor 16 is turned on, its collector voltage becomes a value close to the ground level. For that reason,
The emitter voltage of the third drive transistor 21 is also close to the ground level. When the emitter voltage of the third drive transistor 21 becomes a value close to the ground level, the base voltage becomes higher by Vbe21 from the value close to the ground. However, Vbe21 is the third drive transistor 2
1 is a base-emitter voltage. Therefore, the voltage difference between the collector and the emitter of the second current source transistor 14 increases.

The first and second driving transistors 19
And 20 and the connection point d of the third and fourth output transistors 17 and 18 are connected.
When the output transistor 17 is turned on, the emitter voltage of the second drive transistor 20 becomes a value close to the power supply voltage Vcc. Therefore, assuming that the base-emitter voltage of the second drive transistor 20 is Vbe22, the collector voltage of the first input transistor 2 becomes lower than the power supply voltage Vcc by Vbe20. Therefore, the voltage difference between the collector and the emitter of the first input transistor 2 is widened, and the first input transistor 2 is hardly saturated.

As the positive input signal increases, the collector voltage of the second output transistor 16 further approaches the ground level, and the collector voltage of the third output transistor 17 approaches the power supply voltage Vcc. Thereby, the second current source transistor 14 and the first input transistor 2
Since the voltage difference between the collector and the emitter of the second driving transistor 14 further increases, the second driving transistor 14 and the first input transistor 2 are not saturated.

In addition, since a large output current flows through the load 12 in response to a large input, the collector voltage of the third output transistor 17 increases and the collector voltage of the second output transistor 16 decreases due to the voltage drop of the load 12. Then, the voltage difference between the collector and the emitter of the second and third output transistors 16 and 17 is reduced. This voltage difference is the second
When the voltage becomes lower than the collector-emitter saturation voltage of the third output transistors 16 and 17, the second and third output transistors 16 and 17 become saturated. Therefore, for a positive input signal, the saturation voltage of the BTL amplifier circuit of FIG.
It is determined only by the emitter saturation voltage.

FIG. 2 is a diagram showing another embodiment of the present invention. Reference numerals 23 and 24 denote first and second driving transistors 1 and 2, respectively.
Resistors 25 and 26 are connected between the emitters of the third and fourth driving transistors 21 and 22;
This is a resistor for adjusting the idling current. The connection point a 'between the resistors 23 and 24 is connected to the connection point d, and the connection point c' between the resistors 25 and 26 is connected to the connection point b.

In FIG. 2, when the first and fourth output transistors 15 and 18 are turned on, the emitter current of the first drive transistor 19 flows to the fourth output transistor 18 via the resistor 23. First drive transistor 19
As the base voltage of the first driving transistor 19 increases, the emitter current of the first driving transistor 19 tends to increase as the current flowing through the first and fourth output transistors 15 and 18 increases.
When the emitter current is to be increased, the base-emitter voltage of the first drive transistor 19 is about to increase. However, when the emitter current of the first driving transistor 19 increases, the emitter voltage of the first driving transistor 19 increases due to the voltage drop of the resistor 23. The rate at which the emitter voltage of the first drive transistor 19 increases is substantially the same as the rate at which the base voltage increases. Therefore, the first
The voltage difference between the base and the emitter of the driving transistor 19 does not change, and the emitter current of the first driving transistor 19 does not increase.

On the other hand, part of the collector current of the first output transistor 15 flows to the fourth drive transistor 22 via the resistor 26. The base voltage of the fourth drive transistor 22 decreases, and its emitter current tends to increase. When the current flowing through the resistor 26 is to increase, the emitter voltage of the fourth drive transistor 22 decreases due to the voltage drop of the resistor 26. Therefore, the fourth driving transistor 2
The voltage difference between the emitter and the base of
The emitter current of the driving transistor 22 does not increase.

The second and third output transistors 16
And 17 are on, the third drive transistor 2
1 and the emitter current tends to increase. When the current flowing through the resistor 25 increases, the emitter voltage of the third drive transistor 21 also increases due to the voltage drop of the resistor 25, and the voltage difference between the base and the emitter of the third drive transistor 21 does not change.
Therefore, the emitter current of the third drive transistor 21 does not increase.

When the base voltage of the second drive transistor 20 decreases, the emitter current tends to increase. When the current flowing through the resistor 24 is to increase, the emitter voltage of the second drive transistor 20 decreases due to the voltage drop of the resistor 24, and the voltage difference between the base and the emitter of the second drive transistor 20 does not change. Therefore, the second
The emitter current of the driving transistor 20 does not increase.

Therefore, by inserting the resistors 23 and 24, the emitter current of each drive transistor can be changed. Therefore, there is another effect that the fluctuation of the idling current can be prevented and the deterioration of the distortion factor of the output signal of the BTL amplifier circuit can be prevented.

[0025]

According to the present invention, the saturation voltage of the BTL amplifier circuit can be determined by the saturation voltage between the collector and the emitter of the output transistor, so that the full swing level of the output signal of the BTL amplifier circuit can be increased. And high output can be achieved. In particular, when integrated,
Since the size of the output transistor is increased, the voltage between the collector and the emitter is reduced, and the output can be further increased.

Further, since a resistor is inserted at a connection portion between the drive transistors, a variation in an idling current flowing through the drive transistor can be suppressed, and another effect that a distortion rate of an output signal of the BTL amplifier circuit can be prevented from being deteriorated. Play.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 2 1st input transistor 3 2nd input transistor 13 1st current source transistor 14 2nd current source transistor 15 1st output transistor 16 2nd output transistor 17 3rd output transistor 18 4th output transistor 19 1st drive transistor 20 2nd Driving transistor 21 Third driving transistor 22 Fourth driving transistor 23 to 26 Resistance

Claims (2)

[Claims] A first input transistor to which input signals having phases opposite to each other are applied; a first and a second drive transistor driven in accordance with an output signal of the first input transistor; And a first current source transistor for supplying a bias current to the second driving transistor;
First and second output transistors that are connected and driven according to output signals of the first and second drive transistors, and third and fourth drive that are driven according to output signals of the second input transistor A third transistor and a second current source transistor that supplies a bias current to the third and fourth driving transistors; and a third and fourth transistor that are SEPP-connected and driven in accordance with output signals of the third and fourth driving transistors. An output transistor; and an output signal of the first and second output transistors and the third output transistor.
And BT load by the output signal of the fourth output transistor
An L-driven BTL amplifier circuit, wherein a connection point between the first and second output transistors is connected to a connection point between the third and fourth drive transistors, and a connection point between the third and fourth output transistors. And a connection point between the first and second drive transistors. 2. A resistor connected between the first and second driving transistors, a connection point connected between a connection point of the third and fourth output transistors, and a resistor between the third and fourth driving transistors. 2. A BTL amplifier circuit according to claim 1, further comprising a resistor connected to the first and second output transistors.