JPH1098133A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce dead spaces by placing outer connection means near a semiconductor chip and fixing to exposed one main surface of the chip and outer connecting means with a seal resin, to improve the effective area ratio to a max. SOLUTION: Outer connecting electrode pads on the surface of a semiconductor chip 61 together with are disposed through outer connecting means 62, etc., on the same side as those on the chip back surface, without leading from a seal resin to thereby minimize the seal resin size and make it compact to improve the effective area ratio. The outer connecting means 62, etc., are disposed near the chip 61, corresponding to outer connecting electrode pads for the base and emitter on the chip 16 surface and connected electrically to the base and emitter electrode pads, through Au or Al metal thin wires. This greatly reduces the exterior dimensions of a semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having an improved effective mounting area ratio represented by a ratio of a chip area of the semiconductor device to a mounting area for mounting the semiconductor device on a mounting board such as a printed board.

[0002]

2. Description of the Related Art Generally, a semiconductor device in which a transistor element is formed on a silicon substrate mainly has a structure as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.

As shown in FIG. 3, a transistor element formed on a silicon substrate 11 is, for example, an N-type epitaxial layer 1 serving as a collector region on an N-type silicon substrate 11.
2, a P-type impurity such as boron is diffused into the base region 13.
Is formed, and an N-type impurity such as phosphorus is diffused in base region 13 to form emitter region 14. Base region 13 and emitter region 14 are provided on the surface of silicon substrate 11.
An insulating film 15 having an opening exposing a part of the base region 13 and the exposed emitter region 14 is formed.
A metal such as aluminum is deposited on the base electrode 16,
An emitter electrode 17 is formed. In the transistor having such a configuration, the silicon substrate becomes the collector electrode 18.

As described above, the silicon substrate 1 on which the transistor elements are formed is fixedly mounted on an island 2 such as a copper-based heat sink through a brazing material 5 such as solder, as shown in FIG. The base electrode and the emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged around the substrate 1 by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting a silicon substrate on the island, transfer molding is performed using a thermosetting resin 4 such as an epoxy resin. A semiconductor device having a three-terminal structure is provided by completely covering and protecting a silicon substrate and part of a lead terminal.

[0005]

A resin-molded semiconductor device is usually mounted on a mounting substrate such as a glass epoxy substrate, and is electrically connected to other semiconductor devices and circuit elements mounted on the mounting substrate. It is handled as one component for performing a predetermined circuit operation. FIG. 9 is a cross-sectional view of a semiconductor device mounted on a mounting substrate. Reference numeral 20 denotes a semiconductor device, reference numerals 21 and 23 denote lead terminals for base or emitter electrodes, reference numeral 22 denotes a lead terminal for collector, and reference numeral 30 denotes a mounting substrate. It is.

The mounting area where the semiconductor device 20 is mounted on the mounting board 30 is represented by a region surrounded by the lead terminals 21, 22, and 23 and conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminals as compared with the area of the semiconductor chip having an actual function.

Here, considering the ratio between the area of the semiconductor chip having the actual function and the mounting area as the effective area ratio,
It has been confirmed that a resin-molded semiconductor device has an extremely low effective area ratio. The low effective area ratio means that
When the semiconductor device 20 is used for connection with another circuit element on the mounting board 30, most of the mounting area becomes a dead space which is not directly related to a semiconductor chip having a function. If the effective area ratio is small, the dead space on the mounting substrate 30 increases as described above, which hinders the high-density and miniaturization of the mounting substrate 30.

In particular, this problem appears remarkably in a semiconductor device having a small package size. For example, as shown in FIG. 10, the maximum size of a semiconductor chip mounted on the SC-75A outer shape of the EIAJ standard is 0.40 mm × 0.40 mm.
mm is the largest. When this semiconductor chip is connected to metal lead terminals by wires and resin-molded, the overall size of the semiconductor device becomes 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is 2.56 mm, assuming that it is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of this semiconductor device is about 6.25. %, And most of the mounting area is a dead space that is not directly related to the area of the semiconductor chip having functions.

The problem relating to the effective area ratio is particularly prominent in a semiconductor device having a very small package size and a large chip size as described above. However, the semiconductor chip is wire-connected with metal lead terminals and resin-molded. A similar problem arises with a resin-sealed semiconductor device. In recent years, mounting substrates used in electronic devices, for example, portable information processing devices such as personal computers and electronic organizers, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. There is also a tendency for high-density and small-sized mounting boards to be used.

However, in the above-mentioned prior art resin-encapsulated semiconductor device, as described above, the mounting area for mounting the semiconductor device has a large dead space. Has been one of the factors that hindered the miniaturization of the system. Incidentally, Japanese Patent Application Laid-Open No. 3-248551 is a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to a base, an emitter, and a collector electrode of a semiconductor chip 40 are formed in order to minimize a mounting area when a resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, and 43 are formed so as not to be led out from the side surface of the resin mold 44 and to be flush with the side surface of the resin mold 44.

According to this structure, the lead terminals 41, 4
The mounting area can be reduced by the extent that the leading end portions of 2, 43 are not led out, and the effective area ratio can be slightly improved. However, in the above-described semiconductor device, the tip end of the lead terminal connected to the semiconductor chip is formed by the resin mold 44.
Since it is bent at the corner of the bottom of the resin, it has a structure that can sufficiently withstand the stress during the bending process, so each lead terminal embedded in the resin mold must have a sufficient length, As a result, the resin mold size becomes larger than the semiconductor chip size to be mounted, and the effective area ratio does not decrease. Furthermore, each lead terminal connected to a semiconductor chip is required, and material cost and a manufacturing process become complicated, and there is a problem that manufacturing cost cannot be reduced.

In order to maximize the effective area ratio, as described above, the semiconductor chip is directly mounted on the mounting board, so that the semiconductor chip area and the mounting area are almost the same and the effective area ratio is maximized. . As one prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-6-338504, a flip chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is mounted on a mounting substrate. A 47 face-down bonding technique is known (see FIG. 12). In this prior art, a gate (base) electrode, a source (emitter) electrode, and a drain (collector) electrode are usually formed on the same main surface of a silicon substrate such as a MOSFET, and a current or voltage path is formed in a lateral direction. It is mainly used for horizontal semiconductor devices that generate relatively little heat.

However, in a vertical semiconductor device such as a transistor device in which a silicon substrate becomes one of the electrodes, each electrode is formed on a different surface, and a current path flows in a vertical direction, the above-mentioned flip chip technology is used. It is difficult to do. As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-7-38334, a semiconductor chip 53 is mounted on a conductive pattern 52 formed on a mounting substrate 51 by die. Conductive pattern 5 bonded and placed around semiconductor chip 53
A technique for connecting the electrodes of the semiconductor chip 53 and the semiconductor chip 53 with wires 54 is known (see FIG. 13). In this prior art, the above-described silicon substrate can be used for a semiconductor chip such as a transistor having a vertical structure in which one electrode forms one electrode.

The wire 54 for connecting the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold wire, and therefore, the peel strength (tensile force) of the bonding joint connected to the gold wire by bonding. Is preferably performed in a heating atmosphere at about 200 ° C. to 300 ° C. However, when a semiconductor chip is die-bonded on an insulating resin-based mounting substrate, the mounting substrate may be distorted when heated to the above-mentioned temperature, and a chip capacitor and a chip resistor mounted on the mounting substrate may be distorted. Since the solder for fixing other circuit elements is melted, the wire bonding connection is performed at a heating temperature of about 100 ° C. to about 150 ° C.,
There is a problem that the peel strength of the bonding portion is reduced.

In this prior art, usually, the die-bonded semiconductor chip is covered and protected with a sealing resin such as an epoxy resin, so that the decrease in peel strength is caused by shrinkage of the epoxy resin during thermosetting or the like. There is a problem that is peeled off. The present invention has been made in view of the above-mentioned circumstances, and the present invention arranges external connection electrodes for a base, an emitter, and a collector of a semiconductor device on the same plane, and has a semiconductor chip area and a mounting board. Provided are a semiconductor device in which an effective area ratio, which is a ratio to a mounting area of a semiconductor device to be mounted, is maximized, and a dead space of a mounting area is minimized, and a manufacturing method thereof.

[0016]

The present invention employs the following constitution and manufacturing method to solve the above-mentioned problems. That is, a semiconductor device of the present invention includes a semiconductor chip having at least an active element formed in a semiconductor substrate, and external connection means provided on a surface of the semiconductor chip and electrically connected to an electrode pad. The connection means is arranged near the semiconductor chip, and is fixed with a sealing resin while exposing one main surface of the external connection means and the semiconductor chip.

Here, the main surface of the external connection means and one main surface of the semiconductor chip are arranged on the same plane. Further, an electrode pad for a base electrode and an emitter electrode is provided on the surface of the semiconductor chip, and the external connection means is arranged corresponding to the electrode pad.

Next, a method for manufacturing a semiconductor device according to the present invention
A plurality of semiconductor chips and a plurality of external connection means provided on the surface of the semiconductor chip and electrically connected to the electrode pads are arranged regularly on an insulating resin layer formed on one main surface of the support substrate. Die bonding, electrically connecting an electrode pad provided on the surface of the semiconductor chip and the external connection means with a wire, coating a sealing resin on one main surface of the support substrate, and forming the semiconductor chip and After fixing the external connection means, the support substrate is peeled off so as to expose the surfaces of the semiconductor chip and the external connection means, and at least one semiconductor chip and the external connection means connected to the semiconductor chip are separated. It is characterized in that it is divided individually in the sealing resin region that includes.

As described above, according to the semiconductor device of the present invention, the external electrodes for making an electrical connection with the external connection means disposed near the semiconductor chip and for mounting and fixing on a mounting board such as a wiring board are provided. A metal lead terminal for connecting an external electrode for mounting the semiconductor chip, as in a conventional semiconductor device, by fixing with a sealing resin to expose one main surface of the semiconductor chip and the external connection means to be formed. Is unnecessary, and since it is desired that the lead terminals and other lead terminals connected to the surface electrodes of the semiconductor chip be led out of the sealing mold resin, the external dimensions of the semiconductor device can be significantly reduced.

Further, according to the method of manufacturing a semiconductor device of the present invention, a semiconductor chip and external connection means are mounted on a support substrate, electrically connected and fixed with a sealing resin, and then the support substrate is peeled off at least. By dividing the semiconductor chip into individual encapsulation resin areas including one semiconductor chip and external connection means connected to the semiconductor chip, metal lead terminals as in conventional semiconductor devices can be eliminated, thereby reducing production costs. And mass production can be realized.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described. As shown in FIG. 1, the semiconductor device of the present invention includes a semiconductor chip 61 on which active elements are formed, external connection means 62 and 63 for making an electrical connection with a surface electrode of the semiconductor chip 61, And a sealing resin 80 for fixing the external connection means 62 and 63.

An active element such as a transistor is formed on the semiconductor chip 61. For example, as shown in FIG.
An N− type epitaxial layer 12 is formed on a single crystal silicon substrate 11 by an epitaxial growth technique, and active elements such as transistors are formed on the semiconductor substrate 11. The present invention is particularly suitable for a device having a so-called vertical structure having external connection electrodes on the front and back surfaces of the semiconductor chip 61. FIG. 3 is a cross-sectional view of the general transistor described above. For example, a transistor having an N− type epitaxial layer 12 as a collector region is formed. P such as boron (B)
The island-shaped base region 13 having a predetermined depth is formed by selectively thermally diffusing the mold impurities.

After the formation of the base region 13, a photoresist is formed again on the semiconductor substrate 11, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively heated in the base region 13 exposed by the photoresist. The diffusion forms the emitter region 14 of the transistor. When forming the emitter region 14, a ring-shaped guard ring N + type diffusion region surrounding the base region 13 may be formed in some cases.

The base region 1 is formed on the surface of the semiconductor substrate 11.
An insulating film 15 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing the three surfaces and an emitter contact hole exposing the emitter region surface is formed. Base region 13 and emitter region 14 exposed by base contact hole and emitter contact hole
A base electrode 16 and an emitter electrode 17 and a pad (not shown) for external connection of these electrodes are formed on the base electrode 16 and the emitter electrode 17 selectively deposited by a metal material such as aluminum. A metal plating process is performed on the back surface of the semiconductor substrate 11 to be used as the collector electrode 18.

A feature of the present invention is that the external connection electrode pads (base electrode, emitter electrode) provided on the front surface side of the semiconductor chip 61 are led out of the sealing resin via the external connection means 62 and 63. Semiconductor chip 6 without doing
One of the back surfaces is arranged on the same side as the external connection electrode (collector electrode), and the size of the sealing resin is minimized to make it compact to improve the effective area ratio.

The external connection means 62 and 63 correspond to the semiconductor chip 61 so as to correspond to the number of external connection electrode pads for base and emitter provided on the surface of the semiconductor chip 61.
(See FIG. 2). External connection means 62,
The electrical connection between 63 and the base and emitter electrode pads of the semiconductor chip 61 is made by a wire made of a thin metal wire such as gold or aluminum.

The external connection means 62 and 63 are made of copper, invar,
The material is not particularly limited as long as it is made of a conductive material such as a metal piece such as tellurium or a silicon chip made of a silicon material. In the present embodiment, a silicon chip is used in consideration of workability and cost. The semiconductor chip electrically connected by wires and the external connection silicon chips 62 and 63 are fixed with a thermosetting sealing resin such as an epoxy resin. At this time, the back surface of the semiconductor chip 61 serving as the collector electrode and the back surfaces of the external connection silicon chips 62 and 63 serving as the emitter electrode and the base electrode are arranged on the same plane.

As described above, according to the present invention, unlike a conventional semiconductor device, a metal lead terminal for connecting an external electrode for mounting a semiconductor chip is not required, and the lead terminal and the surface electrode of the semiconductor chip are not required. Since the other lead terminals connected to the semiconductor device are led out of the sealing mold resin, the external dimensions of the semiconductor device can be significantly reduced. More specifically, the semiconductor device of the present invention has a structure in which the back side of the semiconductor chip is directly connected to the mounting substrate, and the external connection means connected to the surface electrode of the semiconductor chip is a silicon chip. The metal lead terminal connected to the chip can be eliminated.

The following is a description of a method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG.
A plurality of semiconductor chips 61 and silicon chips 62 and 63 are regularly arranged on an insulating resin layer 71 made of polyimide resin or the like on one main surface. The support substrate 70 is made of a material having relatively good thermal conductivity. For example, a thin substrate having a thickness of about 0.3 mm to 1.2 mm made of copper, aluminum, ceramics, glass epoxy, or the like is used. Used. A polyimide resin having a thickness of about 2 μ to 5 μ is adhered on the supporting substrate 70 at a heating temperature of about 300 ° C. to about 400 ° C.

The semiconductor chip 61, the silicon chip 62,
63 is mounted on the support substrate 70 in a state where the support substrate 70 is heated to a heating temperature lower than the above-mentioned heating temperature, for example, about 200 ° C. to about 300 ° C. If the heating temperature at this time is higher than the initial heating temperature, the adhesive force becomes too high when the semiconductor chip 61 is die-bonded onto the insulating resin layer 71, which adversely affects peeling of the support substrate 70 described later. .

In this embodiment, the external connection means 62, 6
3 uses a silicon chip as described above. The size of the silicon chips 62 and 63 depends on the size of the semiconductor chip. For example, when the size of the semiconductor chip is 0.40 mm × 0.40 mm, the size of the silicon chip is about 0.25 mm × 0.25 mm. Just design. Accordingly, similarly to the semiconductor chip 61, the silicon wafers of the silicon chips 62 and 63 can be individually formed by a known dicing technique. In the silicon chips 62 and 63 used in this embodiment, high-concentration impurities are diffused from the surface to the opposite main surface for the purpose of reducing the internal resistance.

Each chip is individually picked up from the individually formed silicon wafer on the support substrate 70 by a die bonding apparatus, and is regularly arranged in a region designated on the support substrate 70 as shown in FIG. Then, a plurality of semiconductor chips 61 and silicon chips 62 and 63 are die-bonded. In this embodiment, one semiconductor chip 61 and silicon chips 62 and 63 corresponding to the semiconductor chip 61 are die-bonded on a support substrate 70 so as to form a triangle. The two die-bonded chips are temporarily fixed on the support substrate 70 by the adhesive force of the insulating resin layer 71 formed on the support substrate 70.

After mounting both chips on the support substrate 70,
As shown in FIGS. 1 and 2, the base and emitter electrode pads formed on the surface of the semiconductor chip 61 and the silicon chips 62 and 63 for external connection are wire-bonded to each other with a thin metal wire such as gold, aluminum or the like. Make a static connection. Next, as shown in FIG. 6, a thermosetting sealing resin 80 such as an epoxy resin is
The heat treatment is performed at a temperature of 0 ° C. to about 200 ° C.
The plurality of semiconductor chips 61 and the plurality of silicon chips 62 and 63 mounted on the substrate 0 are fixed with a sealing resin 80.
At this time, the semiconductor chip 61, the silicon chips 62 and 63
The thickness of the sealing resin 80 is taken into consideration so that the surface of the sealing resin 80 is not exposed.

After fixing both chips with the sealing resin 80,
As shown in FIG. 7, the support substrate 70 in close contact with the sealing resin 80 is separated from the sealing resin 80. Sealing resin 80
Is performed by using a solvent to perform scientific peeling or by mechanically peeling the support substrate 70 while heating the supporting substrate 70 to about 150 ° C. to about 200 ° C. to reduce the adhesive strength of the resin layer. The support substrate 70 is peeled off, and the semiconductor chip 61, the silicon chip 62,
After exposing the surface of 63, a region including at least one semiconductor chip 61 fixed with sealing resin 80 and silicon chips 62 and 63 connected to the semiconductor chip 61, specifically, for example, Arrow line shown in FIG. 7 and FIG.
1 is cut by using a cutting device such as a dicing device to separate the sealing resin 80 in the dotted line area shown in FIG.
Can be manufactured.

When the effective area ratio of the semiconductor device of the present invention is compared with that of the conventional semiconductor device, the chip size of the semiconductor device described in the conventional example is 0.40 mm × 0.40.
When the semiconductor chip 61 is connected to a metal lead terminal by a wire and molded with a resin, the overall size of the semiconductor device becomes 1.6 mm × 1.6 mm. Chip area is 0.1
The mounting area for mounting the semiconductor device is 2.56 mm2 with respect to 6 mm2, assuming that the mounting area is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of the conventional semiconductor device is about 6.25%
Met.

On the other hand, in the semiconductor device of the present invention,
Even if the chip size is the same, metal lead terminals are not required, so that the size of the sealing resin 80 is set to 1.0 mm × 1.0
mm, the area of the semiconductor device is 1.00 mm 2, and the effective area ratio is 16. %, Which is about 2.5 times, and the dead space of the mounting area to be mounted on the mounting board can be reduced, which can contribute to downsizing of the mounting board.

In the present embodiment, the semiconductor chip 61 and the silicon chips 62, 6
3 is arranged so as to form a triangle, but if both chips are arranged on a straight line, the effective area ratio can be further improved. According to the above-described method for manufacturing a semiconductor device of the present invention, the semiconductor chip 61 and the external connection means are mounted on the support substrate 70, and are electrically connected to each other.
After fixing at 0, the support substrate 70 is peeled off and divided into individual portions in a sealing resin 80 region including at least one semiconductor chip 61 and external connection means connected to the semiconductor chip 61, whereby the conventional structure is obtained. A metal lead terminal such as a semiconductor device is not required, so that production cost can be reduced and mass production can be realized.

In this embodiment, the transistor is formed on the semiconductor chip 61. However, the present invention is not limited to a vertical device or a horizontal device that generates a relatively small amount of heat. For example, a device such as a power MOSFET, IGBT, or HBT may be used. It is needless to say that the formed semiconductor chip 61 can be applied to the present invention.

[0039]

As described above in detail, according to the semiconductor device of the present invention, the semiconductor device is electrically connected to the external connection means disposed near the semiconductor chip, and is mounted and fixed on a mounting board such as a wiring board. By fixing with a sealing resin to expose a main surface of a semiconductor chip and an external connection means to be an external electrode for performing external electrode connection for mounting the semiconductor chip as in a conventional semiconductor device. In order to eliminate the need for metal lead terminals and to lead the lead terminals and other lead terminals connected to the surface electrodes of the semiconductor chip out of the encapsulation molding resin, the external dimensions of the semiconductor device are significantly reduced. Can be. As a result, the external dimensions of the semiconductor device can be significantly reduced, and unnecessary dead space when mounted on the mounting substrate can be eliminated, which can greatly contribute to miniaturization of the mounting substrate.

Further, according to the method of manufacturing a semiconductor device of the present invention, a semiconductor chip and external connection means are mounted on a support substrate, electrically connected and fixed with a sealing resin, and then the support substrate is peeled off at least. By dividing the semiconductor chip into individual encapsulation resin areas including one semiconductor chip and external connection means connected to the semiconductor chip, metal lead terminals as in conventional semiconductor devices can be eliminated, thereby reducing production costs. And mass production can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 2 is a diagram showing a back surface of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view of a general transistor.

FIG. 4 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 5 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 6 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 7 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a cross-sectional view of a conventional semiconductor device.

FIG. 9 is a cross-sectional view of a conventional semiconductor device mounted on a mounting substrate.

FIG. 10 is a plan view of a conventional semiconductor device.

FIG. 11 is a plan view of a conventional semiconductor device.

FIG. 12 is a cross-sectional view of a conventional semiconductor device mounted on a mounting substrate.

FIG. 13 is a cross-sectional view of a conventional semiconductor device mounted on a mounting board.

Claims (4)

[Claims] A semiconductor chip having at least an active element formed in a semiconductor substrate; and external connection means provided on a surface of the semiconductor chip and electrically connected to an electrode pad. A semiconductor device which is arranged near a semiconductor chip and is fixed with a sealing resin while exposing the external connection means and one main surface of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein said external connection means and one main surface of said semiconductor chip are arranged on the same plane. 3. The semiconductor device according to claim 1, wherein an electrode pad for a base electrode and an emitter electrode is provided on a surface of said semiconductor chip, and said external connection means is arranged corresponding to said electrode pad. . 4. An insulating resin layer formed on one main surface of a support substrate, comprising a plurality of semiconductor chips and a plurality of external connection means provided on the semiconductor chip surface and electrically connected to electrode pads. Die bonding so as to be arranged in a row, and electrically connect the electrode pads provided on the surface of the semiconductor chip and the external connection means with wires, and cover one main surface of the support substrate with a sealing resin. After fixing the semiconductor chip and the external connection means, the support substrate is peeled off so as to expose the surfaces of the semiconductor chip and the external connection means, and the at least one semiconductor chip is connected to the semiconductor chip. A method of manufacturing a semiconductor device, wherein the semiconductor device is divided individually in the sealing resin region including external connection means.