JPH1093064A - Solid-state image-sensing element - Google Patents
Solid-state image-sensing elementInfo
- Publication number
- JPH1093064A JPH1093064A JP8243367A JP24336796A JPH1093064A JP H1093064 A JPH1093064 A JP H1093064A JP 8243367 A JP8243367 A JP 8243367A JP 24336796 A JP24336796 A JP 24336796A JP H1093064 A JPH1093064 A JP H1093064A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- epitaxial layer
- semiconductor substrate
- solid
- ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 230000004888 barrier function Effects 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 230000000779 depleting effect Effects 0.000 claims abstract description 4
- 238000003384 imaging method Methods 0.000 claims description 20
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000005513 bias potential Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、固体撮像素子、特
にオーバーフローバリアを成し半導体基板及び光電変換
部とは逆導電型のエピタキシャル層を有する縦型オーバ
ーフロードレイン方式の固体撮像素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a vertical overflow drain type solid-state imaging device which forms an overflow barrier and has an epitaxial layer of a conductivity type opposite to that of a semiconductor substrate and a photoelectric conversion portion.
【０００２】[0002]
【背景技術】固体撮像素子として、受光部での余剰の電
荷を基板側に排出するようにした、所謂縦型オーバーフ
ロードレイン方式の固体撮像素子が知られており、基板
側への電荷の流れに対しての障壁となるオーバーフロー
バリアは従来においては高エネルギーのイオン注入によ
り基板表面から深いところに形成するようにしていた。2. Description of the Related Art As a solid-state imaging device, a so-called vertical overflow drain type solid-state imaging device in which excess charge in a light receiving section is discharged to a substrate side is known. Conventionally, the overflow barrier serving as a barrier is formed deep from the substrate surface by high-energy ion implantation.
【０００３】しかし、イオン注入によれば、オーバーフ
ローバリアを最大でも５μｍ程度の深さのところにしか
できず、オーバーフローバリアの形成位置の深さを深く
することに限界がある。However, according to ion implantation, the overflow barrier can be formed only at a depth of about 5 μm at the maximum, and there is a limit in increasing the depth of the overflow barrier formation position.
【０００４】一方、固体撮像素子として可視光のみなら
ず近赤外線に対しても感度を有するものの要求がある
が、そのような固体撮像素子はオーバーフローバリアの
深さをより深くする必要があり、イオン注入による形成
方法によっては必要な深さにすることが不可能乃至困難
である。そこで、エピタキシャル層によりオーバーフロ
ーバリアを形成することにより、バリアの深さを任意の
深さにすることが試みられた。On the other hand, there is a demand for a solid-state imaging device having sensitivity not only to visible light but also to near-infrared light. In such a solid-state imaging device, it is necessary to make the overflow barrier deeper. It is impossible or difficult to achieve the required depth depending on the formation method by implantation. Therefore, attempts have been made to make the depth of the barrier arbitrary by forming an overflow barrier using an epitaxial layer.
【０００５】[0005]
【発明が解決しようとする課題】ところが、そのような
固体撮像素子には、図３に示すように、ウェハをスクラ
イブによりチップ化したときスクライブ面にエピタキシ
ャル層によるＰＮ接合が露出し、半導体基板・接地間で
のリーク電流が生じるという新たな問題が生じた。However, in such a solid-state imaging device, as shown in FIG. 3, when a wafer is chipped by scribing, a PN junction by an epitaxial layer is exposed on a scribe surface, and the semiconductor substrate and the semiconductor substrate are exposed to light. There is a new problem that a leakage current occurs between the grounds.
【０００６】図３において、１はＮ型半導体基板、２は
エピタキシャル層からなるＰ型オーバーフローバリア、
３はＰ+ 型チャンネルストッパ、４はＮ型半導体領域の
周辺部分、５はスクライブ面であり、基板１とオーバー
フローバリア２との間のＰＮ接合に基板バイアス電圧Ｖ
ｓｕｂによるリーク電流が流れる。スクライブ面５は荒
れた面なので、そのリーク電流の大きさは正常な動作を
阻むほど大きい。In FIG. 3, 1 is an N-type semiconductor substrate, 2 is a P-type overflow barrier made of an epitaxial layer,
Reference numeral 3 denotes a P + type channel stopper, 4 denotes a peripheral portion of an N type semiconductor region, 5 denotes a scribe surface, and a substrate bias voltage V is applied to a PN junction between the substrate 1 and the overflow barrier 2.
A leak current due to the sub flows. Since the scribe surface 5 is a rough surface, the magnitude of the leak current is large enough to prevent normal operation.
【０００７】このような問題が生じるのは次の理由によ
る。即ち、従来のようにオーバーフローバリアを、イオ
ン注入により形成した場合には、マスク越しにイオン注
入することによりイオン注入場所を選択し、スクライブ
面にオーバーフローバリアと、基板等とによるＰＮ接合
が露出しないようにすることができるが、エピタキシャ
ル層により形成した場合には、オーバーフローバリアが
全面的に形成されてしまうことになり、該バリアと、基
板等とによるＰＮ接合がスクライブ面に露出することを
避けることは不可能であるからである。[0007] Such a problem occurs for the following reason. That is, when the overflow barrier is formed by ion implantation as in the related art, the ion implantation site is selected by ion implantation through a mask, and the PN junction between the overflow barrier and the substrate or the like is not exposed on the scribe surface. However, when formed by an epitaxial layer, an overflow barrier is formed over the entire surface, and the PN junction between the barrier and the substrate is prevented from being exposed on the scribe surface. It is impossible.
【０００８】そこで、本願発明者はオーバーフローバリ
アを成すエピタキシャル層が（換言すると、エピタキシ
ャル層と基板等との間のＰＮ接合が）スクライブ面に露
出してもリーク電流が流れないようにすべく模索し、オ
ーバーフローバリアのスクライブ面に露出する部分を完
全空乏化することによりそれを成すことができるという
着想を得たうえでさらに考察を重ねて本発明を成すに至
った。Therefore, the present inventor has sought to prevent leakage current from flowing even when the epitaxial layer forming the overflow barrier (in other words, the PN junction between the epitaxial layer and the substrate or the like) is exposed on the scribe surface. However, the inventors of the present invention obtained the idea that this can be achieved by completely depleting the portion of the overflow barrier that is exposed on the scribed surface.
【０００９】即ち、本発明はオーバーフローバリアを成
し半導体基板及び光電変換部とは逆導電型のエピタキシ
ャル層を有する縦型オーバーフロードレイン方式の固体
撮像素子において、オーバーフローバリアを成すエピタ
キシャル層のスクライブ面への露出部におけるリーク電
流をなくすことを目的とする。That is, the present invention relates to a vertical overflow drain type solid-state imaging device having an overflow barrier and an epitaxial layer of a conductivity type opposite to that of a semiconductor substrate and a photoelectric conversion portion. The purpose of the present invention is to eliminate the leakage current in the exposed part of the above.
【００１０】[0010]
【課題を解決するための手段】請求項１の固体撮像素子
は、素子周辺近傍に上記半導体基板および光電変換部と
同じ導電型のリング状領域を形成し、該リング状領域及
び上記半導体基板と、上記オーバーフローバリアを成す
エピタキシャル層との間に、上記半導体基板と上記リン
グ状領域との間を完全空乏化する電圧を印加するように
してなることを特徴とする。According to a first aspect of the present invention, there is provided a solid-state imaging device, wherein a ring-shaped region having the same conductivity type as that of the semiconductor substrate and the photoelectric conversion portion is formed in the vicinity of the device. A voltage for completely depleting the space between the semiconductor substrate and the ring-shaped region is applied between the epitaxial layer forming the overflow barrier and the epitaxial layer.
【００１１】従って、請求項１の固体撮像素子によれ
ば、リング状領域及び半導体基板と、オーバーフローバ
リアを成すエピタキシャル層との間に印加された電圧に
より素子周辺近傍に設けたリング状領域と基板との間が
完全空乏化するので、スクライブ面に露出する、エピタ
キシャル層と半導体基板等との間のＰＮ接合には電位差
の存在しない状態になり、延いてはリーク電流が流れな
い。Therefore, according to the solid-state imaging device of the first aspect, the ring-shaped region and the substrate provided in the vicinity of the device by the voltage applied between the ring-shaped region and the semiconductor substrate and the epitaxial layer forming the overflow barrier. Is completely depleted, so that there is no potential difference at the PN junction between the epitaxial layer and the semiconductor substrate, etc., which is exposed on the scribe surface, so that no leak current flows.
【００１２】[0012]
【発明の実施の形態】以下、本発明を図示実施の形態に
従って詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
【００１３】図１（Ａ）、（Ｂ）は本発明固体撮像素子
の第１の実施の形態を示すもので、（Ａ）は平面図、
（Ｂ）は（Ａ）のＢ−Ｂ′線視拡大断面図であり、図２
は動作時のポテンシャル等高線を示す断面図である。FIGS. 1A and 1B show a first embodiment of a solid-state imaging device according to the present invention, wherein FIG.
FIG. 2B is an enlarged sectional view taken along line BB ′ of FIG.
FIG. 4 is a cross-sectional view showing potential contours during operation.
【００１４】図において、１はＮ型半導体基板、２はエ
ピタキシャル層からなるＰ型オーバーフローバリアで、
半導体表面から例えば２〜５μｍ程度あるいはそれ以上
の深さのところに形成され、厚さは例えば１μｍ乃至そ
れ以下である。該バリア２の不純物濃度は例えば１０15
／ｃｍ3 程度である。３はＰ+ 型チャンネルストッパ、
４はＮ型半導体領域の周辺部分、５はスクライブ面であ
る。In the figure, 1 is an N-type semiconductor substrate, 2 is a P-type overflow barrier composed of an epitaxial layer,
It is formed at a depth of, for example, about 2 to 5 μm or more from the semiconductor surface, and has a thickness of, for example, 1 μm to less. The impurity concentration of the barrier 2 is, for example, 10 15
/ Cm 3 . 3 is a P + type channel stopper,
4 is a peripheral portion of the N-type semiconductor region, and 5 is a scribe surface.
【００１５】６は素子の上記Ｎ型半導体領域の周辺部分
４の表面部において周辺近傍に、具体的には例えば素子
側面（スクライブ面）５から１０μｍ程度内側に寄った
ところに形成されたリング状のＮ+ 型領域である。この
ように、リング状のＮ+ 型領域６を有するのが本固体撮
像素子の特徴であり、そして、使用時には、該Ｎ+ 型領
域６に、半導体基板１に印加される基板バイアス電圧Ｖ
ｓｕｂが印加されるようになっている。それ以外の点で
は図３に示す固体撮像素子と特に異なるところはない。
勿論、オーバーフローバリア２への接地電位（０Ｖ）の
付与はチャンネルストッパ３を通じて為される。Reference numeral 6 denotes a ring formed on the surface of the peripheral portion 4 of the N-type semiconductor region of the element, in the vicinity of the periphery, specifically, for example, at a position inward of the element side surface (scribed surface) 5 by about 10 μm. N + type region. As described above, the solid-state imaging device is characterized by having the ring-shaped N + -type region 6. In use, the substrate bias voltage V applied to the semiconductor substrate 1 is applied to the N + -type region 6.
The sub is applied. In other respects, there is no particular difference from the solid-state imaging device shown in FIG.
Of course, the ground potential (0 V) is applied to the overflow barrier 2 through the channel stopper 3.
【００１６】従って、使用時における素子周辺部のポテ
ンシャル等高線は図２に示すようになり［Ｖ１＝Ｖｓｕ
ｂ・１／５（例えばＶｓｕｂが１５Ｖの場合には３Ｖ）
の等高線、Ｖ２＝Ｖｓｕｂ・２／５（例えばＶｓｕｂが
１５Ｖの場合には６Ｖ）の等高線、・・・］、リング状
のＮ+ 型領域６と基板１との間が完全空乏化され、エピ
タキシャル層２からなるオーバーフローバリア２と、基
板１及びＮ型半導体領域４との間のＰＮ接合には電位差
が生じない。従って、そのＰＮ接合のスクライブ面５へ
の露出部が荒れていてもその間には電位差が生じていな
いのでリーク電流は流れない。Therefore, the potential contours at the periphery of the device during use are as shown in FIG. 2 [V1 = Vsu
b 1/5 (for example, 3 V when Vsub is 15 V)
, A contour line of V2 = Vsub · 2/5 (for example, 6 V when Vsub is 15 V),...], The space between the ring-shaped N + type region 6 and the substrate 1 is completely depleted, and epitaxial No potential difference occurs at the PN junction between the overflow barrier 2 composed of the layer 2 and the substrate 1 and the N-type semiconductor region 4. Therefore, even if the exposed portion of the PN junction on the scribe surface 5 is rough, no leakage current flows because no potential difference occurs between the exposed portions.
【００１７】しかして、本固体撮像素子によれば、オー
バーフローバリア２を選択的形成が不可能なエピタキシ
ャル層により形成することがリーク電流の発生のおそれ
を伴うことなく可能になる。Thus, according to the present solid-state imaging device, it is possible to form the overflow barrier 2 from an epitaxial layer that cannot be selectively formed without causing a risk of generating a leak current.
【００１８】従って、オーバーフローバリア２の深さ、
広がり等不純物濃度の深さ方向のプロファイルの設計の
自由度が顕著に高まり、オーバーフローバリア２を深く
することにより近赤外線に対する感度の高い近赤外線用
固体撮像素子を簡単に実現することができる。Therefore, the depth of the overflow barrier 2,
The degree of freedom in designing the profile in the depth direction of the impurity concentration such as the spread is remarkably increased, and by making the overflow barrier 2 deep, a solid-state imaging device for near infrared having high sensitivity to near infrared can be easily realized.
【００１９】[0019]
【発明の効果】請求項１の固体撮像素子によれば、オー
バーフローバリアを成すエピタキシャル層との間に印加
された電圧により素子周辺近傍に設けたリング状領域と
基板との間が完全空乏化するので、スクライブ面に露出
する、エピタキシャル層と基板等との間のＰＮ接合には
電位差のない状態になり、延いてはリーク電流が流れな
い。According to the solid-state imaging device of the first aspect, the voltage between the epitaxial layer forming the overflow barrier and the substrate is completely depleted between the ring-shaped region provided in the vicinity of the device and the substrate. Therefore, there is no potential difference at the PN junction between the epitaxial layer and the substrate, etc., which is exposed on the scribe surface, and no leak current flows.
【図１】（Ａ）、（Ｂ）は本発明固体撮像素子の第１の
実施の形態を示すもので、（Ａ）は平面図、（Ｂ）は
（Ａ）のＢ−Ｂ′線視拡大断面図である。FIGS. 1A and 1B show a first embodiment of a solid-state imaging device according to the present invention, in which FIG. 1A is a plan view, and FIG. 1B is a view taken along line BB ′ of FIG. It is an expanded sectional view.
【図２】使用時における周辺部のポテンシャル等高線を
示す断面図である。FIG. 2 is a cross-sectional view showing potential contours in a peripheral portion during use.
【図３】背景技術の問題点を示す断面図である。FIG. 3 is a cross-sectional view showing a problem of the background art.
１・・・基板、２・・・オーバーフローバリア、５・・
・スクライブ面、Ｖｓｕｂ・・・基板バイアス電圧。1 ... substrate, 2 ... overflow barrier, 5 ...
-Scribe surface, Vsub ... substrate bias voltage.
Claims (2)
及び光電変換部とは逆導電型のエピタキシャル層を有す
る縦型オーバーフロードレイン方式の固体撮像素子であ
って、 素子周辺近傍に上記半導体基板および光電変換部と同じ
導電型のリング状領域を形成し、 上記リング状領域及び上記半導体基板と、上記オーバー
フローバリアを成すエピタキシャル層との間に、上記半
導体基板と上記リング状領域との間を完全空乏化する電
圧を印加するようにしてなることを特徴とする固体撮像
素子1. A vertical overflow drain type solid-state imaging device having an epitaxial layer of an opposite conductivity type to a semiconductor substrate and a photoelectric conversion unit, forming an overflow barrier, wherein the semiconductor substrate and the photoelectric conversion unit are provided near the periphery of the device. Forming a ring-shaped region having the same conductivity type as that of the above, and completely depleting the space between the semiconductor substrate and the ring-shaped region between the ring-shaped region and the semiconductor substrate and the epitaxial layer forming the overflow barrier. A solid-state imaging device characterized in that a voltage is applied.
イアス電位を、上記オーバーフローバリアを成すエピタ
キシャル層にはこれと同じ導電型のチャンネルストッパ
を介して接地電位を与えるようにしてなることを特徴と
する請求項１記載の固体撮像素子2. The substrate bias potential is applied to the ring-shaped region and the semiconductor substrate, and the ground potential is applied to the epitaxial layer forming the overflow barrier via a channel stopper of the same conductivity type as the epitaxial layer. The solid-state imaging device according to claim 1,
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24336796A JP3584629B2 (en) | 1996-09-13 | 1996-09-13 | Solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24336796A JP3584629B2 (en) | 1996-09-13 | 1996-09-13 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1093064A true JPH1093064A (en) | 1998-04-10 |
| JP3584629B2 JP3584629B2 (en) | 2004-11-04 |
Family
ID=17102794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24336796A Expired - Fee Related JP3584629B2 (en) | 1996-09-13 | 1996-09-13 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3584629B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006147758A (en) * | 2004-11-18 | 2006-06-08 | Sony Corp | Solid state imaging device and its manufacturing method |
| JP2006147757A (en) * | 2004-11-18 | 2006-06-08 | Sony Corp | Solid state imaging device and its manufacturing method |
| CN104362164A (en) * | 2014-11-21 | 2015-02-18 | 北京思比科微电子技术股份有限公司 | Back lighting type image sensor structure capable of improving saturation throughput |
-
1996
- 1996-09-13 JP JP24336796A patent/JP3584629B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006147758A (en) * | 2004-11-18 | 2006-06-08 | Sony Corp | Solid state imaging device and its manufacturing method |
| JP2006147757A (en) * | 2004-11-18 | 2006-06-08 | Sony Corp | Solid state imaging device and its manufacturing method |
| JP4561328B2 (en) * | 2004-11-18 | 2010-10-13 | ソニー株式会社 | Solid-state imaging device and manufacturing method thereof |
| CN104362164A (en) * | 2014-11-21 | 2015-02-18 | 北京思比科微电子技术股份有限公司 | Back lighting type image sensor structure capable of improving saturation throughput |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3584629B2 (en) | 2004-11-04 |
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