JPH1090368A - Semiconductor integrated circuit and its verifying method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To verify a semiconductor integrated circuit in timing during the course of failure detecting tests by latching the input value to a storage element from a combinational circuit other than the storage element in accordance with a prescribed clock change at and after the next time. SOLUTION: Each scan register 110-112 has a mode terminal M2 and can decide the timing between set data and the output data of the circuit corresponding to the set data. Mode terminals M2 are terminals for switching the mode to a test mode and, when the test mode is set, test data terminals TD and test clocks TCK operate and outputs the data obtained by performing prescribed logical operation, such as the inversion, etc., on held data at the first changing time of a clock CK when the clock CK changes two or more times. For a prescribed clock change at and after the second time, the input value to a storage element from a combinational circuit other than the storage element is latched. Therefore, a semiconductor integrated circuit can be verified in timing during the course of failure detecting tests.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of fault detection of a semiconductor integrated circuit, and more particularly to verification including timing of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, various LSIs represented by ASICs have been required to have higher integration and higher functions due to the trend toward higher performance and lighter and smaller electronic devices. The above-mentioned LSI such as an ASIC produces a pattern for a photomask pattern through function, logic design, circuit design, layout design, etc., produces a photomask using this, and then reduces and projects the pattern of the photomask onto a wafer. It is manufactured through a long process of transferring by exposure etc. and performing the process of manufacturing a semiconductor device, but as a final process of manufacturing, it is necessary to detect manufacturing defects such as disconnection and short circuit inside LSI. , And an LSI tester. In the LSI test, the LSI is actually operated, the output from the LSI is compared with an expected value prepared in advance, and if the values match, it is regarded as a non-defective product.
If they do not match, this is a step of determining a product as a defective product. The test pattern is a pattern of an input signal to the LSI and an expected output signal used in the LSI test. The detection rate of the defect inside the LSI based on the test pattern is called a failure detection rate. When a test is performed with a pattern having a low failure detection rate, the possibility of being shipped as a product without finding a defective portion inside the LSI increases. Therefore, the higher the failure detection rate is, the better.

When the scale of a circuit integrated in an LSI increases, an enormous number of patterns are required for inspection of the LSI in a normal operation. For this reason, in the process of designing an LSI, a method of inserting a test circuit for improving the fault detection rate inside the LSI and using a short pattern to obtain a high fault detection rate has been adopted at present. Although a large number of test circuits and test methods have been proposed for improving the fault detection rate, a scan method test method is generally known. In this scan method, a shift register is constituted by the storage elements for all the storage elements inside the LSI, data is directly and serially set from the outside to each storage element, and the storage elements based on the set data are used. By latching the outputs of combinational circuits other than the above, and serially outputting the latched signals to the outside, the inside of the LSI can be observed and the fault detection rate is improved.

FIG. 6 shows an example of a conventional scan-type test method, which shows the configuration of a test circuit, and will be briefly described.
FIG. 7A is a symbol diagram of the register, and FIG.
Shows an example of an equivalent circuit of a register. here,
The registers used in the scan system test shown in FIGS. 6 and 7 are called scan registers. In general, a conventional scan register inputs data to a basic register (flip-flop) as shown in FIG. SI terminal (referred to as signal input terminal or test data terminal TD), M (Mode terminal) for separating operation modes, and clock TCK (test clock) for shifting data
And a shift register is formed by a plurality of scan registers. In FIG. 7B, M (Mod
The (e terminal) determines whether or not to enter the test mode, and D and CK denote a data input and a clock (system clock) when not in the test mode. Note that in FIG. 7B, S represents a selector, which selects D, CK, and TCK in response to M.
Make a selection. In FIG. 7B, Q indicates an output, and QB indicates an inverted output. When the test mode is set, the scan registers 610, 611, and 612 form a shift register, and a predetermined value (data) is stored in each register by the SI signal in synchronization with the test clock TCK.
Is set. An output from a logic circuit (combinational circuit) corresponding to a state where a predetermined value (data) is set in each register is latched by each register, and the value (data) latched by each register is sequentially output. Output to S0 (signal output terminal). Thereby, the output of the logic circuit is obtained. After the data setting by the SI signal is completed, the mode is returned to the normal mode, and the output of the logic circuit for each set data is latched in each flip-flop (register). At this time, the test data (TD) is at the timing. Since the operation is not taken into consideration, the operation is performed with a sufficient time margin compared with the normal operation. FIG. 8 shows an example of the operation of each terminal in the test mode in the circuit shown in FIG.

[0005]

SUMMARY OF THE INVENTION However, LSI
Due to the miniaturization, higher integration, and higher functionality of LSIs, the complexity of the LSI processing process and the speeding up of the operation clock have increased the requirements for timing in LSI design and fabrication. As described above, the test method of the conventional test scan method has a higher fault detection rate for a logic circuit between storage elements than a fault detection method using only a test pattern.
Although it could be improved, timing verification could not be performed. In a high-speed operation test using a normal pattern, it was practically impossible to perform a timing test on all signals inside the LSI. The present invention is intended to provide a method capable of performing timing verification in a failure detection test method using a test scan method under such circumstances.

[0006]

According to the semiconductor integrated circuit of the present invention, a shift register is formed by predetermined storage elements in the semiconductor integrated circuit, and at the time of testing a failure detection, the shift register is synchronized with a test clock TCK. The shift data is set in each storage element, and the output of the combinational circuit other than the storage element corresponding to the set shift data data is latched by the predetermined storage element, and the latched signal is serially output to the outside. A semiconductor integrated circuit provided with a scan detection test circuit of a scan type capable of performing a predetermined logic such as inverting an output with respect to held data by a first clock change with respect to two or more changes of a system clock CK. An output according to the operation is output, and a memory element from a combinational circuit other than the memory element is output in response to a predetermined clock change after the second time. It said predetermined storage device to latch the input value to is characterized in that is formed. The above-mentioned predetermined logical operation is an inversion operation, and the output of the storage element is inverted in synchronization with the system clock CK, and the shift of the shift register formed by the predetermined storage elements is performed. At least one of the data is used as a data inversion enable signal, and output inversion is controlled in synchronization with the system clock CK.

A method for verifying a semiconductor integrated circuit according to the present invention is a scan type failure detection test method using the semiconductor integrated circuit according to the present invention, wherein an output signal value from each storage element used for the test is determined by a system clock CK. The logic operation result of each circuit is latched by each of the storage elements, and the output thereof is shifted out after a predetermined time in synchronization with the system clock CK.

[0008]

According to the semiconductor integrated circuit of the present invention having such a configuration, it is possible to provide a method capable of performing timing verification in a scan failure detection test method. For details, see System Clock C
In response to two or more changes in K, an output is output at the first clock change according to a predetermined logical operation such as inversion of the held data and stored for the second and subsequent predetermined clock changes. This is achieved by latching the input value to the storage element from a combinational circuit other than the element. That is, this is achieved by latching the output value from the logic circuit corresponding to the data set in each register (flip-flop) in each register at a predetermined cycle (timing) and sequentially outputting the value. ing. The above-described predetermined logical operation is an inversion operation, and the output of the storage element is inverted in synchronization with a system clock operated at the same speed (clock rate) as that used in the actual system, thereby providing a flip-flop. From the output to the input latch timing of the flip-flop of the next stage at the actual rate, and the timing verification by the scan method is enabled. Further, at least one of the shift data of the shift register formed by the predetermined storage elements is used as a data inversion enable signal, and the control of the output inversion is performed in synchronization with the clock. Masking and the like can be prevented, and more accurate timing verification can be performed. Further, the semiconductor integrated circuit verification method of the present invention is a scan type fault detection test method using the semiconductor integrated circuit of the present invention. In the scan type fault detection test method, verification including timing can be performed. And

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a semiconductor integrated circuit method according to the present invention, FIG. 2A is a diagram showing a symbol diagram of a scan register (register) used in the embodiment, and FIG. FIG. 3 shows a schematic configuration of the scan register. FIG. 3 is a timing chart when a failure detection test is performed on the semiconductor integrated circuit shown in FIG.
1, 2, and 3, 110, 111, and 112 are registers (storage elements), 120 is a logic circuit (combination circuit), and D, TD, CK, TCK,
M, M2, Q, QB, and S are a data terminal, a test data terminal, a clock (system clock), a test clock, a mode terminal, a mode terminal, an output terminal, a non-output terminal, and a selector, respectively. Note that terminals M, M2, D, TD,
Signals corresponding to CK and TCK are M, M2, D, SI, C
K and TCK.

The semiconductor integrated circuit of this embodiment is a semiconductor integrated circuit having a scan type fault detection test circuit. The registers 110, 111, and 112 shown in FIG. ), The failure test can be performed by determining the timing of the set data and the output data from the corresponding circuit. The basic configuration of the semiconductor integrated circuit of this embodiment is the same as that of the conventional semiconductor integrated circuit capable of performing a scan-type test shown in FIG. Each of the registers 110, 111, and 112 used in this embodiment has an M2 terminal unlike the register used in the conventional scan failure detection test circuit shown in FIG. The timing with output data can be determined. The mode terminal M is a terminal for switching to the test mode. In the case of the test mode,
The test data TD terminal and the test clock TCK operate, and the data terminal D and the clock CK do not operate. Also,
If this device does not use the M2 terminal, it goes without saying that a normal scan test can be performed.

When the mode terminal M2 is enabled, the output data is inverted at the edge of the first rising edge of the system clock CK, and the normal input data is latched at the second rising edge of the system clock CK. is there. Note that the data change operation of inverting the output data at the edge at the first rising edge of the system clock CK may be selectively performed. Also, the result of performing some logical operation instead of inversion may be used. For example,
When selectively inverting a signal, a signal in which the QB output of the flip-flop F / F input to the selector S in FIG. It is sufficient to use the F / F. Further, as shown in FIG. 4, a scan flip-flop F / F using one of the shift registers as an enable signal for data inversion is used. The setting as to whether or not to perform the inversion may be performed together. When a scan is used only for some of the flip-flops F / F (this is called a partial scan), if the number of normal F / Fs included between the scan flip-flops F / F is fixed, normal data is latched. 2 times the number of clocks
You may use what was made more than once.

In the case of this embodiment, for simplicity, an output obtained by inverting the output with respect to the held data at the first clock change with respect to two changes of the test clock is output and stored for the second clock change. It is said that the input value from the combinational circuit other than the element to the storage element is latched. However, the output is output by inverting the output with respect to the held data at the first clock change, and the predetermined clock number change at the second and subsequent times. It goes without saying that the input value to the storage element from the combinational circuit other than the storage element can be latched.

Next, a method of verifying a semiconductor integrated circuit of the present invention using the semiconductor integrated circuit of this embodiment shown in FIG. 1 will be briefly described. FIG. 3 is a timing chart showing the operation of the circuit when the scan test is executed. In the semiconductor integrated circuit shown in FIG. 1, first, each flip-flop 110, 11
1. Set the data in 112. Here, as the data to be set, an inverted signal of the pattern actually used for the circuit test is input. In addition, when it is selectively inverted,
When outputting other logical operation results, input as necessary. After the completion of the data setting, M is switched to the normal operation and M2 is switched to the test operation, and the system clock is operated twice. The input data Db is inverted by the first clock change and input to the logic circuit. The timing of this input reflects clock skew and the like in actual operation. At the rise of the next clock (second clock), the output 0 of the logic circuit for the input data D is set in each scan flip-flop (F / F). This data latch also reflects the same timing as the actual operation, and a signal or the like which is not in time for the operation in the actual operation is not latched with a correct value, so that an LSI speed operation failure can be detected. The output of the latched data, the input of the next data, and the like can be performed in the same manner as in the conventional semiconductor integrated circuit shown in FIG.

In the semiconductor integrated circuit of the above-described embodiment, the test considering the timing is performed on a verification pattern of a portion that is strict in terms of timing, and the other patterns are tested by the conventional test method that does not consider the timing. You may go. Of course, a test considering timing may be executed for all patterns. These selections can be appropriately made at the mode terminal M2.

Registers (flip-flops F / F) A, B, C, similar to the scan register used in the above embodiment.
The simple logic circuit shown in FIG. 5A using D will be described more specifically with an example of circuit operation and an input pattern. This circuit performs a timing test on the paths A to O. At this time, consider the case where the output changes from 0 to 1 when the signal A changes from 0 to 1, and FIG.
As shown in (b), a value is set for each input A, B, C, D. When the mode is switched and the clock signal is operated after the end of the data set, each signal is inverted, and the output O performs a predetermined change. If this change is made in time for the next clock, the correct value 1 is latched. At this time, if the value can be selectively inverted for each flip-flop F / F, the method of setting the input B to 0 and not changing the input B can more accurately perform the timing test of the buses A to O.

[0016]

As described above, the present invention meets the demand for timing accuracy in LSI design and fabrication accompanying high integration and high functionality of an LSI, and a timing scan method in a test scan type fault detection method. Verification can be performed. More specifically, the conventional test scan test method can improve the fault detection rate for a logic circuit between storage elements as compared with the fault detection method using only test patterns, but performs timing verification. While this was not possible, the present invention made this possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor integrated circuit according to an embodiment;

FIG. 2 is a diagram showing a scan register used in the semiconductor integrated circuit according to the embodiment;

FIG. 3 is a timing chart when the semiconductor integrated circuit of the embodiment is tested.

FIG. 4 is a schematic diagram of a configuration of a scan register capable of performing inversion.

FIG. 5 is a diagram for explaining an operation in a simple logic circuit;

FIG. 6 is a diagram showing a conventional semiconductor integrated circuit.

FIG. 7 is a diagram showing a scan register used in a conventional semiconductor integrated circuit.

FIG. 8 is a timing chart when a conventional semiconductor integrated circuit is tested.

[Explanation of symbols]

110, 111, 112 Register (storage element) 120 Logic circuit (combination circuit) D Data terminal TD Test data terminal CK clock (system clock) TCK test clock M, M2 mode terminal Q output terminal QB counter output terminal S selector 610, 611 , 612 register (storage element) 620 logic circuit (combination circuit)

Claims (4)

[Claims] A shift register is formed by predetermined storage elements in a semiconductor integrated circuit.
In synchronization with the test clock TCK, shift data is set in each storage element of the shift register, and the output of a combinational circuit other than the storage element corresponding to the set shift data data is latched by the predetermined storage element. A semiconductor integrated circuit having a scan type failure detection test circuit capable of serially outputting a latched signal to the outside, wherein an output is provided by a first clock change in response to two or more changes of a system clock CK. An output according to a predetermined logical operation such as inversion of the held data is output, and an input value to a storage element from a combinational circuit other than the storage element is latched for a predetermined clock change after the second time. A semiconductor integrated circuit, wherein the predetermined storage element is formed. 2. The semiconductor integrated circuit according to claim 1, wherein the predetermined logical operation is an inversion operation, and the output of the storage element is inverted in synchronization with the system clock CK. 3. The method according to claim 2, wherein at least one of shift data of a shift register formed by predetermined storage elements is used as a data inversion enable signal, and output inversion is controlled in synchronization with a system clock CK. A semiconductor integrated circuit characterized by performing: 4. A scan failure detection test method using a semiconductor integrated circuit according to claim 1, wherein an output signal value from each storage element used for the test is inverted in synchronization with a system clock CK. , System clock CK
A semiconductor integrated circuit verification method, wherein the logic operation result of each circuit is latched in each of the storage elements and the output is shifted out after a predetermined time in synchronization with the operation.