JPH1083972A - Method of forming low-resistance silicide layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a silicide layer which is lessened enough in resistance even if it is set smaller than 0.5μm in width. SOLUTION: A laminate composed of a polysilicon layer and a titanium layer laid on the polysilicon layer is subjected to a rapid thermal annealing(RTA) treatment for the formation of a silicide layer 20g. Unreacted titanium is removed, and then the silicide layer 20g is lessened in resistance through a RTA treatment. An interlayer insulating film 30 of PSG, BPSG or the like is formed covering the silicide layer 20g, and then the silicide layer 20g is made to undergo an RTA treatment again so as to be lessened in resistance. The above RTA treatment is primarily carried out for hardening the insulating film 30, so that this forming method is not increased in number of processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS type IC.
The present invention relates to a method of forming a low-resistance silicide layer suitable for use as an electrode or a wiring of an (integrated circuit) or the like, and particularly to a rapid thermal annealing (Rapid Thermization) for lowering the resistance of a silicide layer.
al Anneal (hereinafter abbreviated as RTA)) is performed before and after the formation of the insulating film covering the silicide layer, thereby enabling a sufficient reduction in resistance.

[0002]

2. Description of the Related Art Conventionally, as a method of forming a low-resistance silicide layer, a silicide layer is formed by performing a silicidation heat treatment on a laminate in which a silicide forming metal layer such as Ti (titanium) is laminated on a polysilicon layer, and then a silicide layer is formed. It is known that a layer is subjected to a heat treatment for lowering resistance.

[0003]

According to the above-described conventional method, when the RTA process is used as the silicidation heat treatment and the RTA process is used as the resistance lowering heat treatment, it is sufficient if the width of the silicide layer is about 25 μm. Although it is possible to lower the resistance, it has been found that when the width of the silicide layer is reduced to 0.5 [μm] or less, the reduction in resistance becomes insufficient.

An object of the present invention is to provide a novel low-resistance silicide layer forming method capable of sufficiently reducing the resistance even when the width of the silicide layer becomes 0.5 [μm] or less.

[0005]

According to a method of forming a low-resistance silicide layer according to the present invention, a low-resistance silicide layer is formed on a first insulating film covering a substrate.
Forming a stack including a polysilicon layer and a silicide-forming metal layer overlapping the polysilicon layer; forming a silicide layer by subjecting the stack to a first rapid thermal annealing process; A step of lowering the resistance of the silicide layer by performing a second high-speed thermal annealing process; and after the second high-speed thermal annealing process, a second process is performed by covering the silicide layer on the first insulating film. Forming a second insulating film and, after forming the second insulating film, performing a third high-speed thermal annealing process on the silicide layer to lower the resistance of the silicide layer.

In the method of the present invention, the high-speed thermal annealing process performs the temperature raising and lowering operations in a short time of the order of seconds, and can be typically performed using a lamp annealing apparatus. For example, when a silicide layer having a width of 0.5 [μm] is formed using Ti as a silicide-forming metal, the second rapid thermal annealing process is performed at 800 to 1000 μm.
When performed at [° C], the sheet resistance is 26 to 8 (Ω / □)
After forming a second insulating film such as PSG or BPSG, a third high-speed thermal annealing
When performed at [° C.], the sheet resistance is 10 to 4 (Ω / □).
To a degree. Further, the third rapid thermal annealing process is used as a baking process for the second insulating film, so that an increase in the number of steps can be avoided.

[0007]

1 to 8 show an embodiment in which the present invention is applied to a method of manufacturing a MOS type IC. Steps (1) to (8) corresponding to the respective drawings will be sequentially described. I do.

(1) After forming a field insulating film 12 having an element hole 12A on the surface of a Si (silicon) substrate 10, a gate insulating film 14 is formed on the silicon surface in the element hole 12A.
To form Then, after forming a poly-Si (silicon) layer 16 on the gate insulating film 14 according to the gate pattern, using the field insulating film 12 and the stack of the gate insulating film 14 and the poly-Si layer 16 as a mask, ions of impurities for determining conductivity type are formed. By performing the implantation process, ion implantation regions S ₁₁ and D ₁₁ for source and drain with relatively low concentration are formed.

Next, side spacers 18a and 18b of silicon oxide or the like are formed on the side of the poly-Si layer 16 on the side of the ion-implanted regions S ₁₁ and D ₁₁ respectively. 14 is removed on the ion implantation regions S ₁₁ and D ₁₁ . Then, the lamination of the field insulating film 12, the gate insulating film 14, and the poly-Si layer 16, the gate insulating film 14, and the side spacers 18a, 18
By performing ion implantation of the impurity for determining the conductivity type using the layer b as a mask, ion implantation regions S ₁₂ and D ₁₂ for source and drain with relatively high concentration are formed.

(2) On the field insulating film 12, an element hole 12A, a poly-Si layer 16, and side spacers 18a, 18
and a Ti layer 20 is formed by a sputtering method so as to cover b.
In this embodiment, the thickness of the Ti layer 20 is set to 30 as an example.
[Nm].

(3) The Ti layer 20 is formed by the first RTA process.
And the Ti layer 20 and the ion implantation regions S ₁₂ and D ₁₂ to react with each other.
The titanium silicide layer 20g overlapping the layer 16 and the titanium silicide layer 2 overlapping the ion implantation regions S ₁₂ and D ₁₂ respectively.
0s and 20d are formed. The first RTA process is 500
This is carried out at a relatively low temperature of not less than [° C.] and not more than 700 to 800 [° C.].
The test was performed under the conditions of 0 ° C. and 30 seconds.

(4) Next, unreacted Ti which has not been silicided in the step of FIG. 3 is removed, for example, using H ₂ SO ₄ and H ₂ O _2.
Is removed from the upper surface of the substrate by using the above solution. This is to prevent unreacted Ti from reacting with silicon diffused on the side spacers 18a and 18b in the next step to form silicide, thereby preventing a short circuit between the gate and the source or drain.

Thereafter, the resistance of the silicide layers 20g, 20s, 20d is reduced by a second RTA process. Second R
TA processing is 700-800 [° C] or more and 1000 [° C]
The following is performed at a relatively high temperature. Heat treatment exceeding 1000 ° C. is not preferable because it affects the distribution of implanted impurities.

The following Table 1 shows that when the width (length in the source-drain direction) of the silicide layer 20g is 25 μm, the processing conditions in the second RTA process are variously changed. 2 shows the results of making samples corresponding to the above, and measuring the sheet resistance [Ω / □] of the silicide layer 20g for each sample.

[0015]

[Table 1] According to Table 1, it can be seen that the resistance was substantially sufficiently reduced under the condition of 850 to 1000 [° C.].

On the other hand, Table 2 below shows that the second RTA is obtained when the width of the silicide layer 20g is 0.5 [μm].
The processing conditions in the processing are variously changed to prepare samples corresponding to each processing condition, and the silicide layer 20 is prepared for each sample.
3 shows the results of measuring the sheet resistance [Ω / □] of the g.

[0017]

[Table 2] According to Table 2, it can be seen that the reduction in resistance is not sufficient.

(5) Ion implantation regions S ₁₁ , S ₁₂ , D ₁₁ ,
Heat treatment for activating the implanted impurity D _12. This heat treatment is performed at 850 to 1000 [° C.] as an example. As a result, relatively low-concentration source and drain regions 22 and 24 corresponding to the ion-implanted regions S ₁₁ and D ₁₁ , and relatively high-concentration source and drain regions 26 corresponding to the ion-implanted regions S ₁₂ and D ₁₂ , respectively. And 28 are obtained. The heat treatment for activating the implanted impurities is as follows.
It may be performed before the Ti layer forming step of FIG.

(6) Next, an interlayer insulating film 30 is formed to cover the field insulating film 12 and the transistor portion T including the silicide layers 20g, 20s, 20d. CVD (chemical vapor deposition) as the insulating film 30
After a PSG (phosphosilicate glass) film having a thickness of 100 nm is formed by the CVD method, a BPSG (boron-phosphosilicate glass) film having a thickness of 500 nm is formed on the PSG film by the CVD method. did.

Thereafter, the resistance of the silicide layers 20g, 20s, 20d is reduced by a third RTA process. Third R
The TA process is used as a baking process for the insulating film 30. Therefore, the conventional low-temperature and long-time baking process for the insulating film 30 is not required.

The following Table 3 shows that, when the width of the silicide layer 20g was 0.5 [μm], the processing conditions in the second RTA processing were variously changed, and samples corresponding to each processing condition were prepared. 900 [℃] 10 for each sample above
After performing the third RTA process under the conditions of [sec], the sheet resistance [Ω / □] of the silicide layer 20g is provided for each sample.
3 shows the results of the measurement.

[0022]

[Table 3] According to Table 3, even if the processing conditions of the second RTA processing are the same as those shown in Table 2, it is found that the resistance is sufficiently reduced by performing the third RTA processing. Recognize.

(7) Source and drain connection holes 30s and 30d are provided in the insulating film 30 by well-known photolithography and selective dry etching, and FIG.
As shown in (1), a connection hole 30g for a gate is provided.

(8) Insulating film 30 and connection holes 30g, 30
s and 30d are covered with a wiring material such as an Al alloy by a sputtering method or the like, and the deposited layer is patterned by photolithography and selective dry etching to form source and drain wiring layers 32s and 32d.
And a wiring layer 3 for a gate as shown in FIG.
Form 2 g. The wiring layers 32g, 32s, 32d are connected to the silicide layers 20g, 20s, 20d via the connection holes 30g, 30s, 30d, respectively.

According to the above-described embodiment, the resistance of the silicide layer 20g is sufficiently reduced as shown in Table 3 by performing the RTA process for reducing the resistance before and after the formation of the insulating film 30. Can be. Further, since the third RTA process is used as a baking process for the insulating film 30, the number of steps does not increase.

The present invention is not limited to the above embodiment, but can be implemented in various modified forms. For example, the following changes are possible.

(1) Although the upper layer of the polysilicon layer is silicided and the lower layer is left as a polysilicon layer, the entire polysilicon layer may be silicided.

(2) An example in which side spacers are provided on a patterned polysilicon layer to perform silicidation has been described. However, a laminate in which a silicide-forming metal layer is stacked on a polysilicon layer is patterned according to a desired electrode or wiring pattern. Post silicidation may be performed.

[0029]

As described above, according to the present invention, it is possible to sufficiently lower the resistance by performing the RTA process for lowering the resistance of the silicide layer before and after the formation of the insulating film covering the silicide layer. Therefore, the effect of realizing a low-resistance silicide electrode or wiring can be obtained. Further, there is an advantage that the number of steps is not increased and the steps are simple.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a substrate showing a first ion implantation step, a side spacer formation step, and a second ion implantation step in a method of manufacturing a MOS IC according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a substrate showing a Ti layer forming step following the step of FIG. 1;

FIG. 3 is a cross-sectional view of a substrate showing a silicidation RTA process following the process of FIG. 2;

FIG. 4 is a substrate cross-sectional view showing an unreacted Ti removing step and a resistance lowering RTA processing step following the step of FIG. 3;

FIG. 5 is a substrate cross-sectional view showing an impurity activation heat treatment step following the step of FIG. 4;

6 is a cross-sectional view of the substrate showing an interlayer insulating film forming step and a resistance lowering RTA processing step subsequent to the step of FIG. 5;

FIG. 7 is a cross-sectional view of the substrate showing a connection hole forming step following the step of FIG. 6;

FIG. 8 is a cross-sectional view of a substrate showing a wiring layer forming step following the step of FIG. 7;

FIG. 9 is a cross-sectional view of the substrate along the extension direction of the gate electrode.

[Explanation of symbols]

10: silicon substrate, 12: field insulating film, 14:
Gate insulating film, 16: poly-Si layer, 18a, 18b: side spacer, 20: Ti layer, 20g, 20s, 20
d: titanium silicide layer, 22: low concentration source region, 2
4: low concentration drain region, 26: high concentration source region, 2
8: high concentration drain region, 30: interlayer insulating film, 32 g,
32s, 32d: wiring layers, S _11, D _11: low-concentration ion implantation region, S _12, D _12: high-concentration ion implantation region.

Claims (1)

[Claims] A step of forming a laminate including a polysilicon layer and a silicide-forming metal layer overlying the polysilicon layer on a first insulating film covering the substrate; Performing a process to form a silicide layer; performing a second high-speed thermal annealing process on the silicide layer to reduce the resistance of the silicide layer; and after the second high-speed thermal annealing process, Forming a second insulating film on the first insulating film so as to cover the silicide layer; and, after forming the second insulating film, performing a third rapid thermal annealing process on the silicide layer. Thereby lowering the resistance of the silicide layer.