JPH1083387A - Integer converting operation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress deterioration in operation precision by performing right- shift operation with a specific-bit rounding function for an output result. SOLUTION: A maximum bit detecting circuit 101 detects the number Mx of bits that can represent a maximum value of x(i) as to each block and a prescaling part 102 multiplies real-number constants c(i) and x(i) to obtain p(i). A carry part 103 multiplies p(k) by 2 raised to (M+Cn-Mx-k)th power. At this time, (k) is an integer which is larger than 0 and less than (Mp+Cn-Mx). Then Mp is the number of bits to be operated into an integer and Cn is a constant. Then an integer converting operation part 104 rounds the output of the carry part 103 to obtain an integer, thereby finding an integer P(i) consisting of <=Mp bits. Further, an arithmetic part 105 adds respective P(i)'s and integrates them with the constant. Further, a carry part 106 carries the output of the arithmetic output by (Mp+Cm-Mx-k) bits through right-shift operation with a rounding function.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an integer conversion method in IDCT.

[0002]

2. Description of the Related Art A conventional 8-point IDCT calculation method (Y.Ar
Ai et al., Trans IEICE, E71, pp. 10
95-1097, Nov'88) is shown in FIG.

The pre-scaling unit 201 integrates the DCT coefficient x (i) and a constant c (i) to obtain p (i). Here, c (i) is a real number calculated by (Equation 1).

[0004]

(Equation 1)

FIG. 2B shows the details of the arithmetic section 202. This is an algorithm that obtains eight results y (i) by performing an integration 5 times and a summation 29 times using each p (i).
Although all the operations here correspond to real numbers, the output y
When (i) is an integer, each y (i) is rounded to an integer.

Next, a general image decoding method will be described with reference to FIG.
It is shown in (c). In the Huffman decoding unit 203, the input bit sequence is Huffman decoded to obtain h (i), and the inverse quantization unit 2
At 04, a DCT coefficient x (i) is obtained by multiplying h (i) by the scale factor Q (i). When Q (i) is represented by the product of the initial value Q0 (i) and the variable α, if a value obtained by multiplying Q0 (i) by c (i) is prepared in advance, FIG.
Can be eliminated. As a result, the calculation of the 8-point IDCT can be performed with only 5 integrations and 29 additions.

FIG. 2 is a diagram showing an example in which this is expanded to 8 × 8 points.
(D). In the pre-scaling unit 205, x
The product p (i, j) of (i, j) and c (i) × c (j) is obtained and input to the arithmetic unit 206 for each i row. Arithmetic unit 206
Then, the same processing as in FIG. 2B is performed, and if k is an integer from 0 to 7, the input p (k) corresponds to p (i, k), and the output y (k) is pr (i , K). pr
(I, j) is input to the arithmetic unit 207 every j columns. The arithmetic unit 207 performs the same processing as in FIG. 2B, where the input p (k) corresponds to pr (k, j) and the output y (k) is y
(K, j).

In FIG. 2B, the input p (i) is Mp
If y (i) is an integer obtained by rounding the operation result to a rounded integer, assuming that the DCT coefficient x (i, j) is always a number that can be represented by M bits, p (i, j) is 2 If the value multiplied by (Mp−M + 2) is rounded to an integer, the value can be represented by Mp bits.

Here, if Mp is sufficiently large, there is little deterioration in the calculation accuracy due to the conversion to an integer, but if Mp is limited, the accuracy standard of the IDCT calculation of IEEE (Std118)
0-1990, Dec6'90) may not be satisfied.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to suppress the deterioration of the calculation accuracy due to converting the input to the calculation unit into an integer.

[0011]

In order to solve the above-mentioned problem, the number of bits Mx that can represent the maximum value of the DCT coefficient x (i, j) in one block is obtained, and 2 of p (i, j) is obtained. The value multiplied by (Mp−Mx + 2) is rounded to an integer. As a result, the accuracy of (M-Mx) bits for each block can be improved as compared with the related art.

FIG. 1 shows the configuration of the present invention. FIG. 1 (a)
In, the input block is composed of elements x (0) to x (n). The maximum bit detector 101 detects the number of bits Mx that can represent the maximum value of x (i) for each block. The prescaling unit 102 multiplies a real constant c (i) by x (i), and divides the result by p
(I). In the carry unit 103, p (i) and 2
Multiplied by (Mp + Cn-Mx-k). At this time, k
Is an integer of 0 or more and (Mp + Cn-Mx) or less. Mp
Is the number of bits to be converted into an integer, and Cn is a constant that gives a number less than or equal to 1 so that the value obtained by multiplying c (i) by 2 to the power of Cn is closest to 1. In the integer conversion unit 104, the carry unit 103
Is rounded to an integer, and an integer P within Mp bits
Find (i). The arithmetic unit 105 performs addition and integration of each P (i) with a constant. Carry-down unit 106
In (2), the output of the operation unit is lowered by (Mp + Cn-Mx-k) bits by a right shift operation with a rounding function.

In FIG. 1B, the configuration of one input block and the processing of the maximum bit detector 101 are the same as those in FIG. 1A. In the prescaling unit 107, the multiplication is M
Limited to p-bit integers. C (i) is an integer obtained by multiplying c (i) by 2 to the power of (Mp + Cnm).
Here, m is an integer of 1 or more and (Mp + Cn) or less.
The multiplication of C (i) and x (i) is performed, and the carry-down unit 108 performs (Mx +
km) carry down the bits. Here, k is 0 or more (M
(p + Cn-Mx). The output of the carry unit 108 is defined as P (i).
At 06, the same processing as in FIG.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, two examples in which the present invention is applied to a two-dimensional IDCT and the number of inputs to the arithmetic unit is 16 will be described.

FIG. 3 shows an embodiment of the present invention. The input block is composed of 64 elements x (i, j), and the maximum bit detector 301 detects the number of bits Mx that can represent the maximum value of the elements in the block. Prescaling unit 3
In 02, x (i, j) is multiplied by C (i, j). Here, C (i, j) is a constant obtained by rounding a value obtained by multiplying the product of c (i) and c (j) by 2 to the 17th power. c (i) and c (j) are real constants obtained by (Equation 1). In the carry unit 303, P (i, j) is obtained by a right shift operation with a rounding function of (Mx-1) bits, and is input to the operation unit 304 for every i rows. The arithmetic unit 304 has the same configuration as that of FIG. Here, the input p (i) in FIG. 2B is a 16-bit integer, and y (i) is a result obtained by rounding the calculation result to an integer. Assuming that k is an integer from 0 to 7, the input p (k) in FIG.
(I, k), and the output y (k) of FIG.
(Pr (i, k)). Output Pr of arithmetic unit 304
(I, j) is input to the arithmetic unit 305 every j columns. The operation unit 305 has the same configuration as that of FIG.
(K) corresponds to Pr (k, j) and output y (k) is Y
(K, j). In the lowering section 306, Y
A right shift operation with a rounding function of (16 + 2−Mx) bits is performed on (i, j).

FIG. 4 shows another embodiment of the present invention. The input block is composed of 64 elements x (i, j), and the maximum bit detection unit 401 determines the number of bits Mx representing the maximum value of the element in the block, and the number of bits representing the maximum bit value in the i-th row. Mr (i) is detected. In the pre-scaling unit 402, x (i, j) and C (i, j)
Multiply by Where C (i, j) is c (i) and c (i, j)
This is a constant obtained by rounding a value obtained by multiplying the product of (j) by 2 to the power of (17 + Cr (i)). c (i) and c (j) are real constants obtained by (Equation 1), and Cr (i) is i
Is an integer of 1 when i is 6, 2 when i is 7, and 0 otherwise. In the carry unit 403, P (i, j) is obtained by a right shift operation with a rounding function of (Mr (i) -1) bits, and is input to the operation unit 404 for every i rows. The arithmetic unit 404 performs the same processing as in FIG.
If k is an integer from 0 to 7, the input p (k) is P
(I, k) and the output y (k) corresponds to Pr (i, k). The carry-down unit 405 performs a right shift operation with a rounding function of (Cr (i) + Mx-Mr (i)) bits on Pr (i, j) to obtain Pr2 (i, j), and performs an operation for every j columns Input to the unit 406. The arithmetic unit 406 performs the same processing as in FIG. 2B as in the previous embodiment, and if k is an integer from 0 to 7, the input p (k) is Pr2 (k,
j), and the output y (k) corresponds to Y (k, j). The carry unit 407 performs a right shift operation with a rounding function of (16 + 2−Mx) bits on the output result Y (i, j) of the operation unit 406.

[0017]

According to the present invention, even when the operation unit is a dedicated LSI and cannot be changed, the average operation accuracy can be improved by the preceding and following processes.

Further, since the number of input bits to the operation unit can be reduced, the circuit scale when the operation unit is made into a dedicated LSI can be reduced.

Further, when the present invention is applied to a two-dimensional IDCT, even if the input to the arithmetic unit is 16 bits, the accuracy criterion of IEEE is satisfied. Thus, if the operation unit can be configured by a 16-bit operation unit, the IDCT operation can be performed by a processor having a special instruction capable of processing 16 bits in four parallel, and the image decoding processing by the processor can be further accelerated.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an integer operation method which is a basic configuration of the present invention.

FIG. 2 is a diagram showing a conventional technique.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a diagram showing another embodiment of the present invention.

[Explanation of symbols]

101, 301, 401... Maximum bit detector, 10
2, 107, 201, 205, 302, 402 ... pre-scaling unit, 103 ... carry unit, 104 ...
-Integer unit, 105, 202, 206, 207, 30
4, 305, 404, 406... Arithmetic unit, 106, 1
08, 303, 306, 403, 405, 407 ...
Carry-over unit, 203 ... Huffman decoding unit, 204 ...
Inverse quantization unit.

Claims (11)

[Claims] An element x (i) constituting one block is an integer, and a linear operation is performed using a multiplication result p (i) of each x (i) and a real number constant c (i), and N In the operation algorithm that outputs the results, the element x in the block
(I) Find the number of bits Mx that can represent the maximum value of
The number of bits when (i) is converted to an integer is Mp, the maximum value of c (i) multiplied by 2 to the power of Cn is Cn, and an integer that gives a value of 1 or less, which is closest to 1, is 0 or more ( Mp + Cn-M
x) An integer less than or equal to 2 (Mp + Cn-Mx-k) multiplied by p (i) and then rounded to an integer,
(I), an algorithm consisting of a linear operation using P (i) is executed, and a right shift operation with a rounding function of (Mp + Cn-Mx-k) bits is performed on N output results. Integer arithmetic method. 2. In claim 1, when multiplying x (i) and c (i) by an Mp-bit integer operation, m is an integer of 1 or more and (Mp-Cn) or less, and c (i) is 2 (Mp
+ (Cn-m) raised to the power of (Mpm) bits and converted to an integer by rounding to C (i), and C (i)
Multiplied by x (i), a right shift operation with a rounding function of (Mx + km) bits is performed, and then the same operation algorithm as in the first term is executed, and (Mp + Cn) is performed on N output results. -Mx-k) An integer operation method characterized by performing a right shift operation with a bit rounding function. 3. A method according to claim 1, wherein one block is composed of an N × N matrix, each element is x (i, j), and the result of multiplying each element by c (i, j) is p (i, j). , J), an algorithm consisting of a linear operation is executed for every i rows, and the result is subjected to the same algorithm in the column direction.
The maximum value of (i, j) is obtained, the number of bits Mx capable of expressing the value is obtained, and the number of bits when p (i, j) is converted to an integer is set to the maximum value of Mp, c (i, j). Cn, k are integers that give a value of 1 or less, the value obtained by multiplying 2 to the power of Cn is closest to 1
Is an integer not less than 0 and not more than (Mp + Cn-Mx), a value obtained by multiplying 2 to the power of (Mp + Cn-Mx-k) and p (i, j) is rounded to an integer, and after executing the row direction algorithm, mr is An integer greater than or equal to 0, a right shift operation with a rounding function of mr bits is performed, and then an algorithm in the column direction is executed. For the N × N output results, (Mp + Cn−M
(x-k-mr) Integer conversion method characterized by performing a right shift operation with a function of rounding bits. 4. The method according to claim 1, wherein x (i, j) and c
When the multiplication of (i, j) is performed by Mp integer operation, c (i,
j) multiplied by 2 to the power of (Mp + Cnm) is converted to an integer of (Mpm) bits to obtain C (i, j).
After multiplying (i, j) and x (i, j), (Mx + k−
m) Perform a right shift operation with a rounding function of bits and execute an algorithm in the row direction, then perform a right shift operation with a round function of mr bits, and then execute an algorithm in the column direction to obtain N × N An integer operation method characterized by performing a right shift operation with a rounding function of (Mp + Cn-Mx-k-mr) bits on an output result. 5. The method according to claim 1, wherein (Mp + Cn-Mx-km)
r) Perform a right shift operation on bits, and then. An integer operation method characterized by performing a right shift operation of mr bits on a result of executing an algorithm in a column direction. 6. The method according to claim 1, wherein the input x (i, j)
, The maximum value of the element is obtained for each i row, the number of bits Mr (i) capable of expressing the value is obtained, and k (i) is set to 0 or more (Mp
+ Cn-Mr (i)) and an integer less than or equal to 2 (Mp + Cn-Mr (i) -k (i)) and p (i,
j) is rounded to an integer, and the result of executing the row direction algorithm is calculated as (Mp + Cn-M) for every i rows.
r (i) -k (i) -mr) performing a right shift operation with a rounding function of bits, and then performing a right shift operation with a rounding function of mr bits on the result of executing an algorithm in a column direction. An integer operation method characterized by the following. 7. The method according to claim 1, wherein C (i, j) and x
After multiplying by (i, j), (Mr (i) + k
(I) -m) The result of performing a right shift operation with a rounding function of bits and executing an algorithm in the row direction is compared with (Mp + Cn-Mr (i) -k (i) -mr) bits for every i rows. An integer conversion method comprising performing a right shift operation with a rounding function, and then performing a right shift operation with a rounding function of mr bits on a result of executing an algorithm in a column direction. 8. The method according to claim 1, wherein a value obtained by multiplying the maximum value of c (i, j) in each i-th row element by 2 to the power of Cr (i) is:
If it is less than or equal to the maximum value of the entire matrix of c (i, j), 2 (Mp + Cn + Cr (i) -Mr (i) -k
(I)) The result of multiplying the power to p (i, j) is rounded to an integer, and the result of executing the row direction algorithm is calculated as (Mp + Cn + Cr (i) -Mr (i) -k (i)- mr) perform a right shift operation with bit rounding function,
Then, the result of executing the column-wise algorithm,
An integer operation method characterized by performing a right shift operation with an mr bit rounding function. 9. The method according to claim 1, wherein c (i, j) is 2
Multiplied by (Mp + Cn + Cr (i) -m) to the value (M
C (i, j) is an integer converted to (pm) bits.
After multiplying C (i, j) and x (i, j), a right shift operation with a rounding function of (Mr (i) + k (i) -m) bits is performed for each row, and an algorithm in the row direction is obtained. For the execution result, (Mp + Cn + Cr (i) -Mr
(I) -k (i) -mr) performing a right shift operation with a rounding function of bits and then performing a right shift operation with a rounding function of mr bits on the result of executing the algorithm in the column direction. Integerization algorithm featured. 10. The method according to claim 1, wherein (Mp + Cn + C
r (i) + Mx-Mr (i) -k (i) -mr) performs a right-shift operation with a rounding function of bits, and then executes the algorithm in the column direction to obtain the result of (mr-M
x) An integer operation method characterized by performing a right shift operation with a bit rounding function. 11. A method according to claim 1, wherein a value before execution of the algorithm in the column direction is Pr (i, j),
After executing r (i, j) down to a number within Mp2 bits and then executing the column direction algorithm, Pr (i, j)
j), the maximum bit Mc (j) in each j column is determined, and Mc
When (j) is equal to or more than Mp2, Pr (i, j) is changed to (Mc
(J) -Mp2) A right shift operation with a rounding function of bits is performed, and then, a result of executing an algorithm in a column direction is added to a right-side with a rounding function of (mr-Mc (j) + Mp2-Mx) bits. An integer operation method characterized by performing a shift operation.