JPH1091614A - Method for converting idct into integer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute Arai's algorithm (Trans IEICE, E71, pp. 1095-1097, Nov '88) by 16-bit integer operation. SOLUTION: In the row algorithm (a) of 8×8 IDCT, a carry-down number is determined in accordance with the input values of all WAZANKIs (calculator for old Japanese mathematics), and when carry-down is required, WAZAN (old Japanese mathematics) is executed after the carry-down and the carry-down value of a result is determined in accordance with the input values of integrators 101 to 104. An integrator 105 executes normal integration. In column algorithm (b), d6, d13, d14, d24, and d31 are found out by WAZAN followed by input judgement, and in other cases, normal WAZAN is executed. Integrators 106 to 109 similarly execute integration followed by input judgement and an integrator 110 executes normal integration. Consequently the method can be applied to a processor for executing the parallel processing of 16-bit unit. When the number of operation bits is reduced, an area for forming an exclusive LSI can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for converting an IDCT into an integer in an IDCT operation circuit.

[0002]

2. Description of the Related Art A conventional 8-point IDCT calculation method (Y.Ar
Ai et al., Trans IEICE, E71, pp. 10
95-1097, Nov'88) is shown in FIG.

In FIG. 2A, a prescaling section 201 multiplies a DCT coefficient x (i) and a constant c (i) to obtain p (i), and inputs this to an arithmetic section 202.
Here, i is an integer from 0 to 7, and c (i) is a real number defined by (Equation 1).

[0004]

(Equation 1)

In equation (1), SQRT (2) is a square root of 2.

FIG. 2B shows the details of the arithmetic unit 202.
Here, black circles indicate adders, and squares indicate integrators that perform integration with constants described therein. b1 to b5 are constants defined by (Equation 2) to (Equation 6).

[0007]

(Equation 2)

[0008]

(Equation 3)

[0009]

(Equation 4)

[0010]

(Equation 5)

[0011]

(Equation 6)

When the algorithm is executed only by an integer operation, the integral may be converted to an integer. That is, in each integrator, Mb is an integer, and a value obtained by multiplying b1 to b5 by 2 to the power of Mb is rounded to an integer to prepare constants B1 to B5 in advance. When performing integration, first, integration with the constant is performed,
The result can be converted to an integer by performing a right shift operation with a rounding function of Mb bits.

Next, a general image decoding method will be described with reference to FIG.
It is shown in (c). In the Huffman decoding unit 203, the input bit sequence is Huffman decoded to obtain h (i), and the inverse quantization unit 2
At 04, a DCT coefficient x (i) is obtained by multiplying h (i) by the scale factor Q (i). Q (i) is the initial value Q
0 (i) and the variable α, when Q0 (i) is c
If the value multiplied by (i) is prepared in advance, the integration in the pre-scaling unit in FIG. 2A can be eliminated. Therefore, since the calculation of the eight-point IDCT can be performed only by 5 times of integration and 29 times of addition, this method is known to have the least amount of calculation and to be speeded up.

FIG. 2 shows an extension of this to 8 × 8 points.
(D).

In the pre-scaling unit 205, x
The product p (i, j) of (i, j) and c (i) × c (j) is obtained, and this is divided for every i rows. k is an integer from 0 to 7,
The eight elements p (i, k) in the i-th row are input to the arithmetic unit 206.

The arithmetic unit 206 converts p (i, k) into p (k)
And performs the same processing as in FIG. Output y
(K) is substituted for pr (i, k), and this is repeated for all eight rows to obtain 64 pr (i, j). pr (i,
j) is divided into j columns, and eight elements pr (k,
j) is input to the arithmetic unit 207.

The arithmetic unit 207 calculates pr (k, j) as p
(K) and execute the same processing as in FIG. 2 (b).
The output y (k) is substituted for Y (k, j), and this is repeated for all eight columns to output 64 Y (i, j).

On the other hand, the movement of executing a picture decoding process by a processor has recently become active, and products provided with special instructions for picture processing have been developed. Among them, a processor capable of simultaneously executing four 16-bit operations in parallel using a 64-bit operation processor is also planned.

If the above-mentioned 8 × 8 IDCT can be executed by 16-bit operation, 4-parallel processing becomes possible and the speed can be further increased.

Also, MPEG2 (Moving Pic)
cure Experts Group part2)
Was revised in November 1995 (Technical Corrigendum 2
for ISO / IEC 13818-2, ISO / I
EC DIS 13818-4). This means that when the execution result of the IDCT is (−256) or less (−384) or more, (−256) is output, and when it is 255 or more and less than 384 (255), −385 or less or 384 or more is output. In the case of, the output value is not specified.

When this standard is applied to the 8 × 8 IDCT, if the number of bits of the input p (i, j) to the arithmetic unit 206 in FIG. 2D is Mp bits, the arithmetic unit 206 and the arithmetic unit 207 (Mp + 2)
A bit is needed.

[0022]

However, the IEEE I
DCT calculation accuracy criterion (Std1180-1990, D
To satisfy (ec6'90), p (i, j) needs at least 16 bits. This is the operation unit 206,
In 207, it means that a maximum of 18 bits are required, which causes a problem that it is not suitable for 4-parallel processing.

[0023]

In order to solve the above problem, in FIG. 2 (b), for an arithmetic unit which outputs a calculation result of 17 bits or more, the size of the input value to the arithmetic unit is determined by the following formula. It is determined whether to carry down. As a result, if a carry is required, the calculation is performed after the carry is previously carried out. This makes it possible to always set the operation result to a value within 16 bits.

FIG. 1 shows the configuration of the present invention.

FIG. 1A shows a row algorithm section of the 8 × 8 IDCT. The input p (k), d1 to d31 and s0 to s7 indicating the result of the intermediate operation, and the output y (k) are integers of 16 bits or less. Here, k is an integer of 0 to 7.

The clip operation shown in FIG. 3 is used for all the additions in the row algorithm section.

In FIG. 3, z1 and z2 are integers within 16 bits, and sft (z1) and sft (z2) are z
1, z2, the number of carry down to the present.

The comparison unit 301 calculates sft (z1) and sft (z1).
The larger of (z2) is substituted for sftM. Then sft
d (z1) and sftd (z2) are obtained by (Equation 7).

[0029]

(Equation 7)

The determination unit 302 converts z1 into sftd (z1)
When any of the bits z2 shifted right by sftd (z2) bits is 16 bits, sftd (z1),
1 is added to sftd (z2) and sftM.

The carry unit 303 converts z1 into (sftd (z
1) Bit) The result of right shift operation with rounding function is Z1
Then, the value obtained by performing z2 (sftd (z2) bits) right shift operation with a rounding function is assigned to Z2. Arithmetic unit 304
Outputs the result z3 of the sum of Z1 and Z2.

The history adding unit 305 adds sf (z3) to sf (z3).
Substitute tM.

In FIG. 3, when z3 = z1 + z2 is obtained, the determination unit 3 only determines when the polarities of z1 and z2 are the same.
02 is operated. When z3 = z1−z2 is obtained, the determination unit 302 is operated only when the polarities of z1 and z2 are different. This operation is defined as a clip operation.

Further, the summation executed without operating the determination unit 302 is defined as summation with history.

In FIG. 1A, when d1 to d8 are obtained by clipping, 0 is substituted for sft (p (k)).

Next, the integrating section 10 in the row algorithm section
1 to 105 will be described. Integrator 10 of FIG.
4 is shown in FIG.

In the constant section 401 of FIG. 4, the constant b1 defined by (Equation 2) is multiplied by 2 to the power of Mb1, and the result is rounded to obtain a constant B1. The integration result of B1 and d6 is D1
6, and the carry-down unit 402 sets this to sf (d1
6) Right shift operation with bit rounding function is performed to obtain d16. Here, sf (d16) is a value obtained in the determination unit 403. In the determination unit 403, sf (d1
Mb1 is substituted as the initial value of 6). Also, d1
Sft (d16) is the number of bits lowered to obtain 6.
And sft (d6) is substituted as an initial value. d6
Is obtained, and when the number of bits is 16 and sft (d6) is 0, sf (d16), sf
One is added to t (d16).

In the integrating section 102 shown in FIG.
Is changed to b2 defined by (Equation 3), and Mb1 is changed to Mb2.
Then, the input d6 is replaced with d4, and B2 and D15 are obtained. Also, Mb2 is set in sf (d15), and sft (d1
5) Substitute sft (d4) as an initial value. When d4 is 16 bits and sft (d4) is 0, the determination unit 403 adds 2 to sf (d15) and sft (d15), and when d4 is 16 bits and sft (d4) is 1, Alternatively, when d4 is 15 bits, 1 is set to sf
(D15), and added to sft (d15). Carring part 4
02 performs a right shift operation on D15 with a rounding function of sf (d15) bits to obtain d15.

In the integrating unit 103, B3 and D22 are obtained by replacing b1 in FIG. 4 with b3 defined by (Equation 4), Mb1 with Mb3, and input d6 with d14. Also, sf
(D22) is Mb3, and sft (d22) is sft (d
14) is assigned as an initial value. The determination unit 403 calculates d1
If 4 is 16 bits, 1 is sf (d22), sf
Add to t (d22). The carry unit 402 sets D22 to s
right shift operation with round function of f (d22) bits and d2
Get 2.

In the integrating unit 104, B4 and D12 are obtained by replacing b1 in FIG. 4 with b4 defined by (Equation 5), Mb1 with Mb4, and input d6 with d3. Also, sf
(D12) is Mb4, and sft (d12) is sft (d
3) is substituted as an initial value. The determining operation of determining section 403 is the same as that of integrating section 101, and carry-down section 402 sets D12 to s
right shift operation with round function of f (d12) bits and d1
Get 2.

In the integrating section 105, B5 and D22 are obtained by replacing b1 in FIG. 4 with b5 defined by (Equation 6), Mb1 with Mb5, and input d6 with d13. Also, sf
(D22) is Mb5, and sft (d22) is sft (d
13) is assigned as an initial value. At this time, the determination unit 40
No. 3 performs no determination operation, and sf (d22) and sft (d2
Do not update 2). The carry unit 402 sets D22 to sf (d
22) Right shift operation with bit rounding function is performed to obtain d22.

The output y (k) of the row algorithm is s
ft (y (k)) bits have been carried down. Therefore,
Before inputting to the column algorithm section, sft (y (k))
Performs a bit left shift operation.

FIG. 1B shows an 8 × 8 IDCT column algorithm unit.

P (k), d0-d31, s0-s7, y
(K) is an integer within 16 bits. Where k is 0
It is assumed to be an integer of up to 7.

For the addition, d1 to d5, d7, d8,
When obtaining s1, s0, s2, s4, and s6, normal addition is used, and sft (d1) to sft (d5), sft
(D7), sft (d8), sft (s1), sft
(S0), sft (s2), sft (s4), sft
Substitute 0 for (s6). d6, d13, d14, d
The clip operation described in the row algorithm section is used for 24 and d31, and the summation with history is used for d23, s3, s5, and s7.

In the carry unit 111, d23 is sf
It is updated by a left shift operation of t (d23) bits.

In the carry section 112, s7 is sft
(S7) The bit is updated by a left shift operation.

In the carry unit 113, s3 is sft
Updated by (s3) bit left shift operation.

In the carry section 114, s5 is sft
It is updated by a left shift operation of (s5) bits.

When obtaining y (k), ordinary addition is used.

Regarding the multiplication, the multiplication unit 106
D16 is output by the same processing as in 1, and the integrating section 110 outputs d21 by the same processing as the integrating section 105.

The integrating section 107 outputs d15 by the same processing as that of the integrating section 102 except for the judging operation. At this time, when d4 is 16 bits, 2 is determined as s.
f (d15) and sft (d15), and d4 becomes 15
In the case of a bit, 1 is set to sf (d15) and sft (d1
5) is added.

The accumulator 108 outputs d22 by the same processing as that of the accumulator 103 except for the determination operation. The determination operation at this time is that d14 is 16 bits and sft
When (d14) is 0, sf (d22) and sft (d2
1 is added to 2).

The accumulator 109 outputs d12 by the same processing as that of the accumulator 104 except for the determination operation. At this time, when d3 is 16 bits, sf (d1
2), 1 is added to sft (d12).

[0055]

FIG. 5 shows a first embodiment of the present invention.

In FIG. 5A, first, a 12-bit DCT coefficient x (i, j) represented by an 8 × 8 matrix is input to the pre-scaling unit 501. Here, i and j are 0
It is assumed to be an integer of up to 7.

In prescaling section 501, maximum value detecting section 502 detects the maximum value of each i row of x (i, j), and when the number of bits that can represent this is 12, carry number SCL (i ) Is substituted for 0, and when it is 11, 1 is set to 1
If it is within 0 bits, 2 is substituted.

In the integrating section 503, (c (i) × c
A value obtained by multiplying (j)) by 2 to the 17th power is rounded to an integer, and the result is a constant C (i, j), and the result of integration with x (i, j) is X (i, j). Here, c (n) is (Equation 1)
Is a constant defined by

The result of converting X (i, j) to 16 bits by a right shift operation with a rounding function of (11-SCL (i) -Cr (i)) bits in the carry unit 504 is Pr
(I, j). Here, Cr (i) is replaced by Cr (7)
= 2, Cr (6) = 1, otherwise 0.
Next, 64 elements of Pr (i, j) are divided for every i rows, and eight elements Pr (i, k) in the column direction are input to the row algorithm unit 505.

The details of the row algorithm unit 505 are shown in FIG.
(B), the element Pr (i, k) for each i-th row is represented by p
Substitute (k). Here, k is an integer of 0 to 7.

For the addition, d1 to d31, s0 to s
7 is obtained by using the above-described clip operation. Here, when determining d5 and d6, only p (2) is used for the determination of carry-down. Similarly, when obtaining d1 and d3, determination is made only with p (1).

After obtaining s0 to s7, a right shift operation with a 1-bit rounding function is performed, and sft (s0) to sft (sft)
Add 1 to 7). y (0) to y (7) are obtained by summing with a history.

For the integration, the integration units 509 to 513
Performs the same operation as the integration units 101 to 105 in FIG. Here, Mb1 to Mb5 are set to 13.

The output y (k) of the row algorithm unit 505,
sft (y (k)) is input to the carry unit 506.

In the carry unit 506, (SCL (i) + Cr (i) -sf) is applied to the eight elements y (k) in the i-th row.
The result of the right shift operation with the rounding function of (t (y (k))) bits is defined as Pr2 (i, k). 64 Pr2 (i, j), which are the results of all eight rows, are obtained, divided into j columns, and eight elements Pr2 (k, j) in the row direction are input to the column algorithm unit 507.

FIG. 1 shows details of the column algorithm unit 507.
(B). First, an element Pr2 (k, j) for each j column
To p (k). When d6 is obtained by the above-described clipping operation, only p (2) is used for the determination of carry-down. Other operations are the same as those of the column algorithm unit described above, and Mb1 to Mb5 are set to 13. After obtaining y (k), it substitutes for Pc (k, j) and inputs it to the carry unit 508.

In carry-down section 508, Pc of all columns
A right shift operation with a 6-bit rounding function is performed on (k, j). If the result is -256 or less, the result is -256,
If it is 255 or more, it is clipped to 255 to make it 9 bits, and Y (i,
j) is obtained.

Next, a second embodiment of the present invention is shown in FIG.

In FIG. 6A, first, a 12-bit DCT coefficient x (i, j) represented by an 8 × 8 matrix is input to a pre-scaling unit 601. Here, i and j are 0
-7.

In the prescaling section 601, the maximum value detecting section 602 detects the maximum value of 64 elements of x (i, j). When the number of bits that can represent this value is 8 or less, a value obtained by subtracting the number of bits from 8 is set as SCL_B.

The maximum value detecting section 603 detects the maximum value among the eight elements x (i, k) for each i row shifted left by SCL_B bits. Here, k is an integer of 0-7. The number of bits that can represent this value is n, SCL (i) = 12−n when n> 9, and SCL (i) = 11−n when 10>n> 7.

In the integrating section 604, (c (i) × c
A value obtained by multiplying (j)) by 2 to the 17th power is converted to a rounded integer to obtain a constant C (i, j), and an integration result X (i, j) with x (i, j) is output. Here, c (n) is a constant defined by (Equation 1).

The carry-down unit 605 converts X (i, j) to 16 bits by a right shift operation with a rounding function of (11-SCL_B-SCL (i) -Cr (i)) bits to Pr (i, j). j). Here, Cr (i) is
Cr (7) = 2, Cr (6) = 1, and other integers of 0. Next, the 64 elements of Pr (i, j) are divided every i rows, and the eight elements Pr (i, k) in the column direction are input to the row algorithm unit 606.

The details of the row algorithm unit 606 are shown in FIG.
(A). The element Pr (i, k) of each i-th row is p (k)
Substitute for d5, d6, d1 and d3 are obtained by the same method as the row algorithm of the first embodiment. Otherwise, it is the same as the row algorithm described above, and Mb1 to Mb5 are 13
And y (k) and sft (y (k)) are output.

In the carry-down section 607, sft (y
The maximum value in (k)) is obtained, and this is substituted for sftM. If sftM is equal to or more than (SCL (i) + Cr (i)), y (k) is right-shifted with (sftM-sft (y (k))) bits rounding function, otherwise rounding function To the right shift operation without Pr2 (i,
k). Also, sftM is subtracted from SCL (i) to update SCL (i). This is performed for all eight rows to find 64 Pr2 (i, j) and eight updated SCL (i). Then, Pr2 (i, j) is changed to j
Each column is divided, and eight elements Pr2 (k, j) in the row direction and eight SCL (k) are input to the maximum value detection unit 608.

In the maximum value detecting section 608, for each j column, eight elements Pr2 (k, j) are converted into (SCL (k) +
The maximum value among the values shifted right by Cr (k) +2) bits is obtained. A value obtained by subtracting the number of bits that can represent this value from 14 is set as SCL_c (j), and is set to 2 when the number is 2 or more. This is performed for all eight columns, and eight S
Find CL_c (j).

In the lowering section 609, for each j column,
Pr2 (k, j) is right-shifted with (2 + SCL (k) + Cr (k) -SCL_c (j)) bit rounding function, and is substituted for Pc (k, j).

In the column algorithm section 610, Pc
Substitute (k, j) for p (k). FIG. 6B shows the details of the column algorithm unit.

For the addition, d1 to d23, s1, s
When obtaining 0, s2, s4, and s6, perform normal addition,
sft (d1) to sft (d23), sft (s1),
sft (s0), sft (s2), sft (s4), s
Substitute 0 for ft (s6). The clip operation described above is used for d24 and d31. For s3, s5, and s7, the above-described summation with history is used.

In the carry section 626, s7 is sft
(S7) The bit is updated by a left shift operation.

In the carry section 627, s3 is sft
Updated by (s3) bit left shift operation.

In carry section 628, s5 is sft
It is updated by a left shift operation of (s5) bits.

Regarding the integration, the integrating section 621 outputs d16 by the processing except for the judging operation from the integrating section 101 of FIG. 1A described above. The accumulating section 624 also outputs d12 by the processing excluding the determining operation from the accumulating section 104 of FIG.

The accumulator 622 operates as shown in FIG.
D15 is output by the same processing as that of the integrating unit 102 in (a). The determination operation at this time is to add 1 to sf (d15) and sft (d15) when d4 is 15 bits or more.

The accumulator 623 operates as shown in FIG.
D22 is output by the same process as the integration unit 108 in (b). The determination operation at this time is to add 1 to sf (d22) and sft (d22) when d14 is 16 bits.

The accumulating section 625 corresponds to the accumulating section 10 shown in FIG.
D21 is output by the same processing as in step 5. After obtaining y (k), it is substituted for Pc2 (k, j),
Enter 1

In the carry unit 611, the eight elements Pc2 (k, j) in each j column are converted to (4 + SCL_B + SCL_c
(J)) Right shift operation with bit rounding function is performed. If the result is less than or equal to -256, the result is clipped to -256, and if it is more than 255, 255 is substituted into Y (k, j). This is performed for all eight columns, and 64 output results of 8 × 8 IDCT, Y
(I, j) is obtained.

Next, a third embodiment of the present invention is shown in FIG. In this embodiment, it is assumed that the function of determining the number of carry-downs according to the magnitude of the input value to the arithmetic unit and the rounding function in the middle of the arithmetic algorithm are excluded, and the number of bits required in this case is reduced. The method of reduction is shown. Therefore, 1
Use an integer of 6 bits or more.

In FIG. 7A, first, a 12-bit DCT coefficient x (i, j) represented by an 8 × 8 matrix is input to the pre-scaling unit 701. Here, i and j are 0
It is assumed to be an integer of up to 7. In the integrating unit 702, (c
A value obtained by multiplying (i) × c (j)) by 2 to the 16th power is rounded to an integer C (i, j), and x (i, j)
And outputs the integration result X (i, j). Where c
(N) is a constant defined by (Equation 1). Carrying part 7
In 03, a value obtained by right-shifting X (i, j) by 5 bits is set to Pr (i, j). Pr (i, j) is 21
It is a bit integer. Next, 64 elements of Pr (i, j) are divided every i rows, and 8 elements Pr in the column direction
(I, k) is input to the row algorithm unit 704. Here, k is an integer from 0 to 7.

The details of the row algorithm unit 704 are shown in FIG.
(B). First, the element Pr (i, k) of each i row is p
Substitute (k). Here, black circles indicate adders. The integrators 706 and 708 output a value obtained by performing an 8-bit right shift operation on the result of integration with 362. Integrator 707
Outputs a value obtained by performing an 8-bit right shift operation on the result of integration with 669. The integrator 709 outputs a value obtained by performing an 8-bit right shift operation on the result of integration with 277. Integrator 71
0 outputs a value obtained by performing an 8-bit right shift operation on the result of integration with 196. The carry unit 711 obtains 19-bit y (k) by a 2-bit right shift operation,
Substitute (i, k). All additions and accumulations in the row algorithm require at least 23 bits.

After executing the row algorithm for all eight rows, Pc (i, j) is divided into j columns, and eight elements Pc (k, j) in the row direction are input to the column algorithm unit 705.

The details of the column algorithm unit 705 are shown in FIG.
It is shown in (c). First, the element Pc (k, j) of each j column is p
Substitute (k). Here, black circles indicate adders. The carry unit 712 performs a 1-bit right shift operation. The integrators 713 to 717 correspond to the integrators 706 to 706 in FIG.
The same operation as that of the integrator 710 is performed. The carry unit 718 performs an 8-bit right shift operation with a rounding function. The result is -2
If it is 56 or less, -256; if it is 255 or more, it is 25.
By clipping to 5, 9-bit y (k) is obtained. Further, this is substituted for Y (k, j). At least 2 for all addition and multiplication in the column algorithm section
Requires 0 bits.

The column algorithm is executed for all eight columns, and
The 64 output results Y (i, j) of the × 8 IDCT are obtained.

[0094]

According to the present invention, the 8 × 8 IDCT is 16
Since it can be executed by an integer operation of bits, it is possible to execute four 16-bit operations in parallel at the same time.
Can be processed by a bit processor. In this case, the computation amount of the IDCT is reduced to about 1/4.

Also, since the number of bits required for the operation can be reduced, the 8 × 8 IDCT
Is composed of a dedicated LSI, the number of wirings and the number of flip-flops can be reduced, and the area of the LSI can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a row algorithm and a column algorithm of 8 × 8 IDCT according to the present invention.

FIG. 2 is a diagram showing a conventional IDCT algorithm.

FIG. 3 is a diagram illustrating a configuration of a summing unit according to the present invention that always sets a result to a value within 16 bits.

FIG. 4 is a diagram illustrating a configuration of an integrating unit that always sets a result to a value within 16 bits according to the present invention.

FIG. 5 is a diagram showing a first embodiment of the present invention.

FIG. 6 is a diagram showing a second embodiment of the present invention.

FIG. 7 is a diagram showing a third embodiment of the present invention.

[Explanation of symbols]

························ 101 to 110 ······················
-Operation unit, 203 ... Huffman decoding unit, 204 ...
Inverse quantization unit, 205... Prescaling unit, 20
6,207: arithmetic unit, 301: comparison unit, 302
··· Judgment unit, 303 ··· Carry down unit, 304 ··· Operation unit, 305 ··· History adding unit, 401 ··· Constant unit,
402: carry-down unit, 403: judgment unit, 501
..Pre-scaling section, 502... Maximum value detecting section,
503: accumulation unit, 504, 506, 508: carry unit, 505: row algorithm unit, 507 ...
Column algorithm part, 509 to 513...
1: Prescaling unit, 602, 603, 608
... Maximum value detector, 604 ... Integrator, 605,6
07, 609, 611: carry-down unit, 606: row algorithm unit, 610: column algorithm unit, 62
1 to 625: accumulation unit, 626 to 628: carry unit, 701: prescaling unit, 702: accumulation unit, 703: carry unit, 704: row algorithm unit, 705... Column algorithm section, 706 to 71
0, 713 to 717: integrating section, 711, 712, 7
18 ... Carry-down part.

Claims (3)

[Claims] 1. A DCT coefficient x (i, j) represented by an 8 × 8 matrix is input to a pre-scaling unit, where i and j are integers from 0 to 7, and n is 1 in the pre-scaling unit. ~
An integer of 7, SQRT (2) is a square root of 2, c (n) is (1/2 × cos (n × π / 16)), c (0) is SQRT (2) / 4, and x (i , J) and (c (i) × c (j)) are output, and the 64 Pr (i, j) are divided into i rows, and On the other hand, k is an integer of 0 to 7 and eight column elements pr
(I, k) is substituted for p (k), and p (k) is input to a row algorithm unit. In the row algorithm unit, p (2) + p (6) is calculated for an operation when k is an even number. d5, p (2) -p (6) is d
6, p (0) + p (4) is d7, p (0) -p (4) is d8
When b1 is SQRT (2), b1 × d6 is d16, d5−d16 is d23, d7 + d5 is s0, d7−d5 is s6, d8−d23 is s4, d8 + d23 is s2, and k is an odd number. , P (1) + p (7) is d1, and p (1) -p (7) is d
3, p (5) + p (3) is d2, p (5) -p (3) is d4
D1−d2 is d14, d1 + d2 is s1, d4−d3 is d13, b2 is (1 / (cos (6π / 16)), b2 × d
4 as d15, b4 as (1 / (cos (2π / 16)), b4 × d
3 as d12, b3 as SQRT (2), b3 × d14 as d22, and b5 as (SQRT (2) / (2 × cos (2π / 1)
6)), b5 × d13 is d21, d21-d15 is d31, d12-d21 is d24, s1-d24 is s5, s5 + d22 is s3, s3 + d3
Let 1 be s7, and for the calculation results of the even and odd parts of k, s0 + s1 is y (0), s0-s1 is y (7), s4 + s5 is y (6), s4-s5 is y (1), s2 + s3 is y (2), s2-s3 is y (5), s6 + s7 is y (4), s6-s7 is y (3), and the output result y (k) of the row algorithm is obtained. y
(K) is substituted for pc (i, k), and this is repeated for all eight rows. After obtaining 64 pc (i, j), the pc (i, j) is divided into j columns. , J, the eight row-directional elements pc (k, j) of column j are substituted for p (k), and p (k) is input to the column algorithm unit. To get y (k),
ID for substituting y (k) for each j column into yc (k, j) and repeating this for all eight columns to obtain yc (i, j)
In the CT algorithm, in the pre-scaling unit, M is set to 16 or 17, and a value obtained by multiplying (c (i) × c (j)) by 2 to the power of M is rounded to C (i, j). , The carry number for each i row is SCL (i), and Cr (i) is
r (7) is an integer of 0 to 2; Cr (6) is 0 to 1
The following integers, and other integers that are 0, (x (i,
j) × C (i, j)) by (M-6-SCL (i) -Cr
(I) Result P of right shift operation with bit rounding function
r (i, j) is output, this is divided for every i rows, Pr (i, k) of the i rows is substituted for p (k), and this is input to the row algorithm section. In addition of integers z1 and z2 within 16 bits, z
Sft is the number of carry bits of 1, z2 up to the present
(Z1) and sft (z2), and the larger of the two is sf
tM, sftd (z1) is (sftM-sft (z1)), sftd (z2) is (sftM-sft (z2)), z1 is sftd (z1) bits, and z2 is sftd (z
2) The result of right shift operation with bit rounding function is Z
1, Z2, and the result of executing the addition of Z1 and Z2 is z3
When the operation of substituting sftM for sft (z3) is a sum with history, and using this, z3, which is the result of (z1 + z2) and (z1-z2), is always within 16 bits, z3 = Z1 + z2, the polarities of z1 and z2 are the same, z1 is sftd (z1) bits, and z2 is sftd (z
2) When any of the right-shifted bits is 16 bits, z1 is (sftd (z1) +1) bits, and z2 is the right-shifted value with rounding function of (sftd (z1) +1) bits to Z1 and Z2. Substituting, (Z1 + Z
2) is performed, and z3 which is always an integer within 16 bits
And perform an operation of substituting (sftM + 1) for sft (z3). The polarities of z1 and z2 are the same, and z1 is sftd
When both (z1) bits and z2 shifted right by sftd (z2) bits are 15 bits or less, or when the polarities of z1 and z2 are different, z1 is sftd (z1) bits, and z2 is sftd (z
2) The right-shifted value with the bit rounding function is Z1,
Substituting into Z2, executing (Z1 + Z2) to obtain z3, sf
When sftM is substituted for t (z3) to obtain z3 = z1−z2, the polarities of z1 and z2 are different, z1 is sftd (z1) bits, and z2 is sftd (z
2) When any of the right-shifted bits is 16 bits, z1 is (sftd (z1) +1) bits, z2 is (sftd (z2) +1) bits, and the right-shifted values with the rounding function are added to Z1 and Z2. Substituting, (Z1-Z
2) is performed, and z3 which is always an integer within 16 bits
And perform an operation of substituting (sftM + 1) for sft (z3). The polarities of z1 and z2 are different, and z1 is changed to sftd (z
1) bits and z2 shifted right by sftd (z2) bits are both 15 bits or less, or when the polarities of z1 and z2 are the same, z1 is sftd (z1) bits, and z2 is sftd ( z
2) The right-shifted value with the bit rounding function is Z1,
Substituting into Z2, executing (Z1-Z2) to obtain z3, sf
The operation method of substituting sftM for t (z3) is a clip operation, substituting 0 for sft (p (k)), performing all the additions in the row algorithm unit by the clip operation, and integrating in the row algorithm unit. , Where b1 is 2 Mb1
B1 is a value obtained by rounding the value obtained by multiplying the power to an integer,
(D6 × B1) is D16, the value obtained by multiplying b2 by 2 Mb2 and rounded to an integer is B2, and (d4 × B
2) is D15, a value obtained by multiplying b3 by 2 to the power of Mb1 and rounded to an integer is B3, and (d14 × B3) is D2.
The value obtained by multiplying 2 and b4 by 2 to the power of Mb4 is rounded to an integer, and the resulting value is B4, and (d3 × B4) is calculated by dividing D12 and b5 by 2
The value obtained by multiplying the value obtained by multiplying the power of
When (d13 × B5) is D21 and d12 is obtained, sf (d12) is Mb4, sft
Substituting sft (d3) for (d12), if d3 is 16 bits and sft (d3) is 0, sf (d1
2), 1 is added to sft (d12), and D1 is added to d12.
2 is substituted with the result of right shift operation with sf (d12) bit rounding function. When d15 is obtained, Mb2 and sft are used for sf (d15).
Substituting sft (d4) for (d15), if d4 is 16 bits and sft (d4) is 0, add 2 to sf (d15) and sft (d15), and d4 is 16 bits, When sft (d4) is 1 or when d4 is 15 bits, 1 is added to sf (d15) and sft (d15), and d1
5 is substituted with the value obtained by performing a right shift operation with sf (d15) bit rounding function on D15. When d16 is obtained, Mb1 and sft are used for sf (d16).
Substituting sft (d6) for (d16), if d6 is 16 bits and sft (d6) is 0, sf (d1
6), 1 is added to sft (d16), and D1 is added to d16.
6 is substituted with the result of right shift operation with sf (d16) bit rounding function, and when d21 is obtained, sf (d21) is Mb5, sft
Substituting sft (d13) for (d21), D21 for d21
21 is substituted with the result of right shift operation with sf (d21) bit rounding function, and when d22 is obtained, sf (d22) is Mb3, sft
Substituting sft (d14) for (d22), d14 becomes 16
In the case of bits, sf (d22) and sft (d22) are 1
Is added to d22, and the value obtained by performing a right shift operation with sf (d22) bit rounding function on D22 is substituted for d22. After obtaining y (k), y (k) is converted to (SCL (i) + Cr
(I) -sft (y (k))) A right-shift operation with a rounding function of bits is substituted for Pc (i, k), and this operation is repeated for all eight rows to obtain 64 Pc (i, j). )
Is obtained, the Pc (i, j) is divided into j columns, and the eight elements Pc (k, j) in the j columns are substituted for p (k), which is input to the column algorithm unit. , In the column algorithm section, regarding the addition, d1 to d5, d7, d8, s1, s
When obtaining 0, s2, s4, and s6, perform normal addition,
sft (d1) to sft (d5), sft (d7), s
ft (d8), sft (s1), sft (s0), sf
0 is substituted into t (s2), sft (s4), and sft (s6), and d6, d13, d14, d24, and d31 are clip operations described in the row algorithm section, d23, s
3, s5, and s7 are used as summations with a history, and d23 is substituted with sft (d23) bits left-shifted, and sft (s0) to s0 are substituted for s0 to s7.
ft (s7) -bit left-shifted operation is substituted,
When obtaining y (k), normal summation is used. For integration, Mb1 to Mb5, B1 to B5, D16,
The definitions of D15, D22, D12, and D21 are the same based on the description of the row algorithm, and d16 and d21 are obtained in the same manner as the row algorithm. When d12 is obtained, Mb4 is set to sf (d12), and sf
Substituting 0 into t (d12), and when d3 is 16 bits,
One is added to sf (d12) and sft (d12), and d1
2 is substituted with a value obtained by performing a right shift operation with sf (d12) bit rounding function on D12, and when d15 is obtained, Mb2 is set to sf (d15) and sf
Substituting 0 into t (d15), and when d4 is 16 bits,
2 is added to sf (d15) and sft (d15), and d4
Is 15 bits, sf (d15), sft (d1
Add 1 to 5), and add d15 to d15 as sf (d15)
Substituting the result of the right shift operation with the bit rounding function to obtain d22, Mb3 and sft are used for sf (d22).
Substituting sft (d14) for (d22), d14 becomes 16
Bit and sft (d14) is 0, sf
(D22), 1 is added to sft (d22), and d22
Is substituted for sf (d22) bits with a right shift operation with a rounding function, and after calculating y (k), y (k) is right shifted with a 6-bit rounding function. If it is less than 256, it is substituted by -256, and if it is more than 255, the value clipped to 255 is substituted into Y (i, k), and this is repeated for all eight columns to obtain Y (i, j). I
Integer method of DCT. 2. The method according to claim 1, wherein the summation in the row algorithm section uses a clipping operation when obtaining d1 to d31 and s0 to s7, and after obtaining s0 to s7, a 1-bit right with rounding function. After performing a shift operation, sft (s0) ~
An IDCT integerization method characterized in that 1 is added to sft (s7) and y (0) to y (7) are obtained by summing with a history. 3. The method according to claim 1, wherein y
After obtaining (k), the maximum value of sft (y (k)) is obtained, and this is substituted for sftM.
(I) + Cr (i)), y (k) is set to (sfM
−sft (y (k))) Right shift operation with a rounding function of bits, and in other cases, a right shift operation without a rounding function is performed, and the result is substituted into Pc (i, k), and the result is substituted from SCL (i). Subtract sftM and repeat for all 8 rows, 64 Pc (i, j), 8 updated SCL
After calculating (i), Pc (i, j) is divided into j columns, and the eight elements Pc (k, j) in each j column are shifted right by (SCL (k) + Cr (k) +2) bits. The maximum value of the shifted values is obtained, and the value obtained by subtracting the number of bits that can represent this from 14 is SCL_c.
(J), and when this is 2 or more, 2 and Pc (k,
j) by itself (2 + SCL (k) + Cr (k) -SCL
_C (j)) to which the right-shifted operation with the bit rounding function is substituted and input to the column algorithm unit.
When obtaining 23, s0, s1, s2, s4, and s6, normal addition is performed, and sft (d1) to sft (d23), s
ft (s0), sft (s1), sft (s2), sf
Substituting 0 into t (s4) and sft (s6) to obtain d31, d
24, a clipping operation is used, and s5, s3, and s7 use a history-added operation. Substitute s3 with the sft (s3) -bit left-shifted operation, and substitute s5 with sft (s
5) Substitute a left-shifted operation of bits, substitute itself for s7 with a left-shifted operation of sft (s7) bits, and use ordinary addition when obtaining y (k).
For integration, D16 is Mb1 bit, D12 is M
b4 bits and D21 are right-shifted with Mb5 bits rounding function as d16, d12 and d21, and sft
(D16), 0 for sft (d12), and sft (d21)
To obtain d15, Mb2 is substituted for sf (d15), and sf
Substituting 0 into t (d15), and when d4 is 15 bits or more, adding 1 to sf (d15) and sft (d15),
Substitute the value obtained by performing a right shift operation with sf (d15) bit rounding function on D15 for d15. When obtaining d22, Mb3 is set to sf (d22) and sf
Substituting 0 into t (d22), and when d14 is 16 bits, adding 1 to sf (d22) and sft (d22),
Substitute the right-shift operation of D22 with the sf (d22) bit rounding function for d22 into d22, obtain y (k), and then convert y (k) to (4 + SCL_c
(J)) A right shift operation with a bit rounding function is performed, and if the result is -256 or less, the result obtained by clipping to -256 and 255 to 255 is substituted into Y (k, j). This method is repeated to obtain Y (i, j), which is an IDCT integer conversion method.