JPH1078914A - Cache control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache control circuit in which even when an error is generated in a cache in a redundant processor element, the error can be prevented from being developed to an incorrectable error without shifting the synchronization of the redundant processor element. SOLUTION: When an error is detected in read data from caches 12 and 22, error detecting and correcting circuits 13 and 23 simultaneously inform interruption generating circuits 14 and 24 of their own processor elements 1 and 2, and the interruption generating circuits 24 or 24 of the other processor elements 2 and 1 that the error is detected through error communication lines 110 and 120. The interruption generating circuits 14 and 24 receive information that the error is detected from the error detecting and correcting circuits 13 and 24, and generate interruption for allowing software to recognizes the generation of the error to MPU 11 and 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache control circuit, and more particularly to a cache control method for a fault-tolerant computer.

[0002]

2. Description of the Related Art Conventionally, in this type of cache control system, a fault tolerant computer equipped with a dual memory is intended to efficiently reflect cache contents in the dual memory without impairing fault tolerability. Used.

That is, in a fault-tolerant computer, each time a cache in a processor element is updated, a sequential write process of reflecting the updated content in one memory element by a write-through method is performed, and the other memory element is updated. , A batch write process for writing all the updated contents of the cache at the time of the checkpoint process.

The above-described cache update processing in the fault tolerant computer is described in Japanese Patent Laid-Open No.
It is described in detail in JP-A-271624.

[0005]

In the conventional cache control system described above, only the memory elements are made redundant, and the case where the processor elements are made redundant is not considered. When the processor element is made redundant, the failure of the processor element itself can be covered by the substitute processor element, so that the above-mentioned checkpoint processing itself becomes unnecessary, and a more efficient system can be constructed. Further, even if one processor element fails, there is no need to recover from the memory.

However, when the processor element is made redundant, an error occurs in only one of the redundant processor elements. Therefore, the operation of correcting the error and writing the corrected data to the cache causes the error to occur. Only the processor element that has occurred. When writing the correction data to the cache of the processor element in which the error has occurred, the cache cannot be accessed from the processor while the writing operation of the correction data is being performed.

Therefore, for example, when a read from the processor to the cache occurs while the processor element in which the error has occurred is writing the correction data,
Read data is immediately returned from the cache to the processor in a processor element in which no error has occurred, but read data can be returned to the processor in the processor element in which an error has occurred until the correction data has been written to the cache. Can not.

As described above, when trying to correct an error and write corrected data to the cache, the synchronization of the redundant processor elements that must operate synchronously is lost. Therefore, when the processor element is also made redundant, even if a correctable error is detected in the cache, a problem arises in that the corrected data cannot be written to the cache. In the prior art, this problem does not occur because the processor elements are not made redundant.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problem, and even if an error occurs in a cache in a redundant processor element, an error which cannot be corrected without shifting the synchronization of the redundant processor element. Another object of the present invention is to provide a cache control circuit that can prevent the development of the cache control circuit.

[0010]

According to the present invention, there is provided a cache control circuit comprising: a cache memory for storing a part of the content of a storage device; and a cache memory for which the storage content does not match the content of the storage device by writing data. A cache control circuit for an information processing system including first and second processor elements operating in synchronism with each other, including a write-back means for writing contents stored in a memory to the storage device; An error detection and correction unit for detecting an error in the read data and correcting the detected error; and the write back unit in response to an error notification output from the error detection and correction unit of another processor element. Instructing means for instructing the storage device to write back the stored content to the first and second storage devices. It is provided on a respective processor element.

Another cache control circuit according to the present invention comprises:
A cache control circuit of an information processing system including a cache memory for storing a part of the contents of a storage device and comprising a first and a second processor element operating in synchronization with each other, wherein a cache control circuit for reading data from the cache memory is provided. Error detection and correction means for detecting an error and correcting the detected error; address holding means for holding a read address of the cache; and correcting the error when the error is detected by the error detection and correction means. Correction data holding means for holding data; and the address holding when at least one of an error notification from the error detection and correction means of the own processor element and an error notification from the error detection and correction means of the other processor element is input. Means for storing the corrected data in the address held by the means. And means for instructing the writing has been data held in the unit to the cache memory to the first and second processor elements, respectively.

As described above, according to the cache control method of the present invention, when an error occurs in the cache of a redundant processor element, an error in the cache can be eliminated without shifting the synchronization of the redundant processor element. Remove.

More specifically, an error detection and correction circuit having a function of detecting an error of read data from a cache and correcting an error of erroneous data, and an error detection and correction circuit of all redundant processor elements And an interrupt generation circuit for generating an interrupt for notifying the software that an error has been detected to flush the cache to the software in accordance with the error notification received from the circuit.

In another method, an error detection / correction circuit having a function of detecting an error in read data from a cache and correcting an error in erroneous data, and an address holding means for holding a cache read address are provided. A correction data holding means for holding read data from a cache in which an error has been corrected when an error is detected by the error detection and correction circuit;
Correction data writing means for issuing an instruction to write data held by the correction data holding means to the cache at an address held by the address holding means in response to an error notification from one or more other processor elements.

[0015] The data in which an error has occurred in the cache by flushing the cache with software by the interrupt generation circuit or writing the correction data to the cache by the correction data writing means without shifting the synchronization of the redundant processor elements. Can be removed.

[0016] This is different from a normal system. In general, even when a correctable error occurs in a cache, a processor element that has been disconnected from service due to a synchronization problem of a redundant processor element as a fault tolerant system. Continuous operation becomes possible, and there is an effect of improving reliability performance.

At present, the capacity of a cache has been increased, and accordingly, the probability that a soft error, which is not a hardware failure due to radiation or the like, occurs in the cache has increased. Soft errors can be completely restored by correcting the errors.

In particular, in a fault-tolerant computer in which reliability is regarded as important, continuing to operate in a redundant configuration by recovering the cache soft error greatly improves the reliability.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In the figure, the processor elements 1 and 2 are duplicated and therefore have exactly the same components. That is, the processor elements 1 and 2 include the MPUs 11 and 21 and the cache 1
2 and 22, error detection and correction circuits 13 and 23, and interrupt generation circuits 14 and 24.

The MPUs 11 and 21 are microprocessors for performing arithmetic processing in the processor elements 1 and 2, respectively. The caches 12 and 22 are cache memories of the MPUs 11 and 21, respectively. Error detection and correction circuits 13 and 23
Is the cache 1 according to the instructions of the MPUs 11 and 21 respectively.
This is a circuit for performing error detection and error correction of data read from the data read from the memory devices 2 and 22.

The error detection and correction circuit 13 includes a cache 12
When an error is detected in the read data from the processor element 1, the interrupt generation circuit 14 in the own processor element 1 and the interrupt generation circuit 24 in the other processor element 2 simultaneously notify that the error has been detected through the error notification line 110. Notice. Similarly, the error detection and correction circuit 23 simultaneously notifies the interrupt generation circuits 14 and 24 via the error notification line 120 that an error has been detected.

When notified of the detection of the error from the error detection and correction circuit 13 or the error detection and correction circuit 23, the interrupt generation circuits 14 and 24 make the MPUs 11 and 21 recognize the software that the error has occurred. To generate an interrupt.

The operation of the first embodiment of the present invention will be described with reference to FIG. Since the processor elements 1 and 2 are duplicated and their components perform exactly the same operation, the operation of the components of the processor element 1 will be basically described. Each element of the processor element 2 corresponds to a component of the processor element 1 having the same name.

In the processor element 1, the MPU 11 performs arithmetic processing. By the load / store in this arithmetic processing, data is read from the main memory (not shown) or data is written to the main memory. A cache 12 is provided to perform this access at high speed. When receiving a read request from the MPU 11, the cache 12 sends the read data to the error detection and correction circuit 13.

The error detection and correction circuit 13 includes a cache 12
Check the data from for errors.
When an error is detected, the error detection and correction circuit 13 notifies the interrupt generation circuit 14 in the own processor element 1 and the interrupt generation circuit 24 in the other processor element 2 at the same time through the error notification line 110, respectively, that the error has been detected. Notice.

If the detected error is a correctable error, the error detection and correction circuit 13 replies the corrected data to the MPU 11. In the case of an uncorrectable error, the processor element 1 becomes a failure and is disconnected from the service, and continues to be operated by the other duplicated processor element 2.

In the interrupt generation circuit 14, the error notification line 11
0 to the cache 2a from the error detection and correction circuit 13.
Will be notified that there was an error in the lead data for
Alternatively, when the error detection and correction circuit 23 notifies the MPU 11 of an error in the read data of the cache 22 through the error notification line 120, the MPU 11 executes an interrupt for notifying the software of the error.

Therefore, the processor elements 1, 2
Even if an error is detected in either one of these, this interrupt is sent to the MPU 11 by the interrupt generation circuit 14.
The interrupt generation circuit 24 simultaneously executes the MPU 21.

At this point, the erroneous data remains stored in the cache of the processor element in which the error was detected. Thus, before proceeding to an uncorrectable error, the software receiving the interrupt performs a full cache flush.

Here, flushing the cache means that the processor executes a write to the cache. If the data in the main memory and the data in the cache do not match, at least the data in the cache does not match. This is a series of operations in which all the data stored in the cache is written back to the main memory so that the data in the main memory matches the data in the cache and all the data in the cache at the time of flushing is invalidated. However, in the present invention, when the cache is flushed, all data to be written back from the cache to the main memory is sent to the main memory through the error detection and correction circuits 13 and 23. Even if an error that can be corrected is detected, all the data in the cache that did not match with the error corrected is written back to the main memory.

FIG. 3 is a block diagram showing the configuration of the second embodiment of the present invention. In the figure, the processor elements 3 and 4 are duplicated similarly to the configuration of the first embodiment of the present invention, and therefore have exactly the same components. That is, the processor elements 3 and 4 are MPU3
1, 41, caches 32 and 42, error detection and correction circuits 33 and 43, address holding means 34 and 44, correction data holding means 35 and 45, and correction data writing means 36 and 46. .

The MPUs 31 and 41 are microprocessors for performing arithmetic processing in each of the processor elements 3 and 4. The caches 32 and 42 are cache memories of the MPUs 31 and 41, respectively. Error detection and correction circuits 33 and 43
Is cache 3 according to the instruction of each of the MPUs 31 and 41.
This is a circuit for performing error detection and error correction of data read from the memory devices 2, 42.

The address holding means 34, 44, MPU3
The read addresses from the caches 1 and 41 to the caches 32 and 42 are held. The correction data holding units 35 and 45 hold the read data returned from the error detection and correction circuits 33 and 43 to the MPUs 31 and 41.

When the error detection and correction circuit 33 notifies the error detection line 33 that the error has been detected via the error notification line 130, the correction data writing means 36 notifies the other processor element 4 that the error has been detected by the processor element 3 itself. The correction data writing means 46 is notified.

The correction data writing means 36 is notified by the error detection and correction circuit 33 that an error has been detected,
Alternatively, when the correction data writing means 46 of the other processor element 4 notifies that an error has been detected in the processor element 4, the address holding means 34
The write to the cache 32 is executed according to the address and data held in the correction data holding unit 35. The correction data writing means 46 has the same function as the correction data writing means 36.

The operation of the second embodiment of the present invention will be described with reference to FIG. Since the processor elements 3 and 4 are duplicated and their components perform exactly the same operation, basically the operation of the components of the processor element 3 will be described. Each element of the processor element 4 corresponds to a component of the processor element 3 having the same name.

In the processor element 3, the MPU 31 performs arithmetic processing. By the load / store in the arithmetic processing, data is read from a main memory (not shown) or data is written to the main memory. A cache 32 is provided to perform this access at high speed. Cache 32
Sends a read data to the error detection and correction circuit 33 when there is a read request from the MPU 31.

The error detection and correction circuit 33 includes a cache 32
Check the data from for errors.
When an error is detected, the error detection and correction circuit 33 notifies the correction data writing means 36 via the error notification line 130 that the error has been detected.

If the detected error is a correctable error, the error detection and correction circuit 33 replies the corrected data to the MPU 31. In the case of an uncorrectable error, the processor element 3 becomes a failure and is disconnected from the service, and continues to be operated by the other duplicated processor element 4.

The address holding means 34 holds a read address from the MPU 31 to the cache 32. At this time, the correction data holding means 35 has the address holding means 34
Is read from the cache 32, and even if there is an error in the read data, the data whose error has been corrected by the error detection and correction circuit 33 is stored.

When the error detection / correction circuit 33 notifies the error detection line 33 that the error has been detected through the error notification line 130, the correction data writing means 46 sends an error to the correction data writing means 46 of the other processor element 4 in its own processor element 3. Report that it was detected. Since the correction data writing means 46 also has the same function, even if an error is detected in the processor element 4, the correction data writing means 36 can recognize the error by the notification from the correction data writing means 46. Upon receiving an error detection notification from the error detection / correction circuit 33 or the correction data writing unit 46, the correction data writing unit 36 writes the data to the cache 32 according to the address of the address holding unit 34 and the data of the correction data holding unit 35.

At this time, even if an error occurs in the processor element 4, since the processor element is duplicated, the addresses held in the address holding means 34 and 44 are always the same, and the corrected data holding means The data held in 35 and 45 and the data in which an error is detected are always the same data because the error has been corrected. Therefore, there is no problem even if the address and data held in the own processor element 3 are used.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing a configuration of the error detection and correction circuit 13 of FIG. In the figure, an error detection and correction circuit 13 includes an error detection circuit 13a, a syndrome generation circuit 13b, a syndrome decoder 13c, an error correction circuit 13d, and an uncorrectable error detection circuit 13e.
It is composed of The error detection and correction circuit 23 has the same configuration as that of the error detection and correction circuit 13 described above.

An example according to the first embodiment of the present invention will be described with reference to FIGS. MP
U11, U21 and caches 12, 22 are as described for the operation of the first embodiment of the present invention described above. The error detection and correction circuits 13 and 23 use ECC for error detection and correction.
FIG. 2 shows an embodiment using (error check & collection) code. Usually, a code capable of correcting a 1-bit error and detecting a 2-bit error is used as the ECC code.

In error detection circuits 13a and 23a (error detection circuit 23a is not shown), bits of all data and all E
The exclusive OR of the CC codes is used to detect whether there is a correctable error. Error detection circuit 13
The results of a and 23a are output to the error notification line 110 or the error notification line 120, and are notified to the interrupt generation circuits 14 and 24.

The syndrome generation circuits 13b and 23b (the syndrome generation circuit 23b is not shown) generate a syndrome according to a predetermined syndrome generation pattern. Syndrome without error,
Usually, it is all "0".

The generated syndrome is decoded by the syndrome decoders 13c and 23c (the syndrome decoder 23c is not shown), and the same number of bits as the read data in which only the bit corresponding to the data in which the error has occurred is "1". Is obtained. As in the case of the syndrome, this decoding result is all “0” when there is no error.

An error correction circuit 13 which takes the exclusive OR of the decoding results of the syndrome decoders 13c and 23c and each bit of the read data from the caches 12 and 22
A correctable 1-bit error is corrected by d and 23d (the error correction circuit 23d is not shown).

Uncorrectable error detection circuits 13e and 23e
(The uncorrectable error detection circuit 23e is not shown) detects whether there is an uncorrectable error of two or more bits. Although no error is detected by the error detection circuits 13a and 23a, the syndrome generation circuits 13b and
If the result of 23b is not all "0" or if the result of the syndrome generation circuits 13b and 23b is an unspecified pattern, it is determined as an uncorrectable error.

If an uncorrectable error is detected, recovery cannot be performed. Therefore, the processor element in which the uncorrectable error is detected is disconnected from the service, and the fault-tolerant system is switched to the other of the duplicated. The processor element is continuing processing.

The error correction by the error detection and correction circuits 13 and 23 is not necessary if there is no error in the data read from the caches 12 and 22. However,
Depending on the system, the correction of the error shown in FIG. 2 may require several clock cycles. In this case, the timing of the reply to the MPUs 11 and 21 differs depending on whether or not the error is corrected.

If the timings of the replies of the MPUs 11 and 21 are different, there arises a problem that the synchronization between the processor element 1 and the processor element 2 is shifted. To prevent this, the error detection and correction circuits 13 and 23 always operate to correct the error. That is, the output results of the error correction circuits 13d and 23d are always returned to the MPUs 11 and 21.

When an error is detected in the read data from the caches 12 and 22 in the error detection and correction circuits 13 and 23, the data after the error correction is rewritten to the caches 12 and 22 in a general system by rewriting the data. ,
The errors existing in the caches 12 and 22 are corrected. However, in a case where the processor elements 1 and 2 are duplicated, if only one of the processor elements in which an error has occurred performs an operation of rewriting the error correction data to the cache, the synchronization of the duplication is lost. The problem occurs.

Here, the interrupt generation circuits 14 and 24 OR the error notification signals of the error notification lines 110 and 120, and
An interrupt is generated in the MPUs 11 and 21. This interrupt is received by the operating system, and when recognizing that an error has been detected in the read data from the cache, it issues an instruction to flush the caches 12 and 22. Instead of rewriting the error-corrected data in the cache, the caches 12 and 22 are flushed at the same time, so that the data containing the error is not stored in the cache without shifting the synchronization of the processor elements 1 and 2.

FIG. 4 is a block diagram showing the configuration of the correction data writing means 36 of FIG. In the figure, the correction data writing means 36 has an error F / F (flip-flop) 3
6a, an address register 36b, and a data register 3
6c and an OR circuit 36d. The correction data writing means 46 has the same configuration as that of the correction data writing means 36 described above.

An example according to the second embodiment of the present invention will be described with reference to FIGS. While the first embodiment of the present invention flushes out the cached data by software to flush out the cached data from the cache, the second embodiment of the present invention provides a method for reading out the cached data when an error occurs. An error occurred in the cache without shifting the synchronization of the duplicated processor element by holding the duplicated data and the address and simultaneously writing the corrected data to the cache in both of the duplicated processor elements. Has a function to correct data.

MPUs 31, 41 and caches 32, 4
2 is as described for the operation of the above-described second embodiment of the present invention. The error detection and correction circuits 33 and 43 have the same configuration as the error detection and correction circuits 13 and 23 of the first embodiment of the present invention, and are as described in the first embodiment of the present invention. When a correctable error is detected by the error detection circuits of the error detection and correction circuits 33 and 43, the error notification line 13
0, 140 is notified to the correction data writing means 36, 46 that an error has been detected.

When an error is detected in the read data from the caches 32 and 42 in the error detection and correction circuits 33 and 43, in a general system, the data after the error correction is rewritten in the cache, and the data is stored in the cache. Correct any existing errors.

However, the processor elements 3,
4 is duplicated, the operation of rewriting the error correction data to the cache in only one of the processor elements in which the error has occurred is performed.
There is a problem that the synchronization of weighting is shifted. In view of this, a configuration is shown in which the correction data is written simultaneously to the caches of both processor elements as well as one of the processor elements, thereby correcting the data existing in the cache without shifting the synchronization of the duplexing. It is shown in FIG.

The address holding means 34 and 44 are provided by the MPU 3
The addresses at the time when the caches 32, 42 are read from the cache memory 1, 41 are held. The correction data holding units 35 and 45 hold data after errors that can be corrected by the error detection and correction circuits 33 and 43 are corrected.

The detailed configuration of the correction data writing means 36, 46 is as shown in FIG. Correction data writing means 3
In step 6, the address held in the address holding means 34 is stored in the address register 36b, and the data held in the correction data holding means 35 is stored in the data register 36c.
To hold. The error notification from the error detection and correction circuit 33 through the error notification line 130 is stored in the error F / F 36a.

The detection of an error in the read data of the cache 32 of the own processor stored in the error F / F 36a is notified to the correction data writing means 46 of the other processor element 4.

The OR circuit 36d ORs the error notification signal of its own processor element stored in the error F / F 36a and the error notification signal from the other processor element 4, and generates an enable signal for writing to the cache 32. . The address to the cache 32 for this write enable signal is stored in the address register 3
6b, and the data is data stored in the data register 36c.

By ORing the error notification of the own processor element 3 and the other processor element 4 by the OR circuit 36d, even if an error occurs in one of the processor elements, the cache is simultaneously cached in both the processor elements 3 and 4. Write instructions to 32 and 42 will be issued.

Since the address held in the address holding registers 34 and 44 and the data held in the correction data holding means 35 and 45 are always equal, even if an error is detected in another processor unit, the own processor unit may be used. Write to the cache using the address and data held in the cache.

As described above, in the duplicated processor element, an error is detected in the read data from the cache, and when it is determined that there is erroneous data in the cache, the duplicated processor element Erroneous data in the cache can be removed without shifting the synchronization of the data.

[0067]

As described above, according to the cache control circuit of the present invention, an error of data read from a cache memory for storing a part of the contents of a storage device is detected and the detected error is corrected. At the same time, the storage contents of the cache memory, whose storage contents have become inconsistent with the contents of the storage device due to the data writing, are written back to the storage device. By instructing the contents to be written back to the storage device, even if an error occurs in the cache in the redundant processor element, it is possible to develop an uncorrectable error without shifting the synchronization of the redundant processor element. The effect is that it can be prevented.

According to another cache control circuit of the present invention, an error in data read from a cache memory storing a part of the contents of a storage device is detected, and the detected error is corrected. When at least one of an error notification from a processor element and an error notification from another processor element is input, the data held in the corrected data holding means is written to the cache memory with the read address held in the address holding means. By giving the instruction, even if an error occurs in the cache in the redundant processor element, it is possible to prevent the occurrence of an uncorrectable error without shifting the synchronization of the redundant processor element. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an error detection and correction circuit of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a correction data writing unit in FIG. 3;

[Explanation of symbols]

 1-4 Processor element 11, 21, 31, 41 MPU 12, 22, 32, 42 Cache 13, 23, 33, 43 Error detection and correction circuit 13a Error detection circuit 13b Syndrome generation circuit 13c Syndrome decoder 13d Error correction circuit, 13e correction Impossible error detection circuit 14, 24 Interrupt generation circuit 34, 44 Address holding means 35, 45 Correction data holding means 36, 46 Correction data writing means 36a Error F / F 36b Address register, 36c Data register 36d OR circuit 110, 120, 130 , 140 Error notification line

Claims (4)

[Claims] 1. A cache memory for storing a part of the contents of a storage device, and a write-back operation for writing back the storage contents of the cache memory whose contents have become inconsistent with the contents of the storage device due to data writing. A cache control circuit of an information processing system including first and second processor elements operating in synchronization with each other, comprising: a return unit; and detecting an error in data read from the cache memory and detecting the detected error. An error detection and correction unit for correcting the error, and an error notification output from the error detection and correction unit of the other processor element. Instruction means for instructing writing back to the first and second processor elements Cache control circuitry, characterized in that it comprises people to. 2. The writing device according to claim 1, wherein the instruction unit outputs an interrupt signal for instructing the storage device to write back the stored content of the cache memory to the storage device. Cache control circuit. 3. The storage device according to claim 2, wherein the write-back unit corrects a correctable error detected by the error detection and correction unit when writing back the mismatched storage content of the cache memory to the storage device. 3. The cache control circuit according to claim 1, wherein the cache control circuit is configured to write back the data. 4. A cache control circuit for an information processing system comprising a cache memory for storing a part of the contents of a storage device and comprising a first and a second processor element operating in synchronization with each other, wherein the cache memory Error detection and correction means for detecting an error in the data read from and correcting the detected error; address holding means for holding the read address of the cache; and when the error is detected by the error detection and correction means. Corrected data holding means for holding data obtained by correcting the error, and at least one of an error notification from the error detection and correction means of the own processor element and an error notification from the error detection and correction means of the other processor element are inputted. At the address held in the address holding means when Cache control circuitry, characterized in that it comprises a means for indicating the data held in the serial correction data holding means and said cache memory in writing as in the first and second processor elements, respectively.