JPH0887424A - Electronic computer - Google Patents

Abstract

PURPOSE: To provide the electronic computer which can recover from a fault at a check point with small memory capacity. CONSTITUTION: Plural processors(PE) 103 and plural storage parts having buffer memories 101 and 102 are mutually connected and one address in one storage part forms a group with one address in each of other storage parts; and the electronic computer is provided with a means which generates parity on the basis of data in corresponding addresses of other storage parts in the same group except one storage part and stores the parity in the corresponding address of the one storage part, a means which stores the buffer 101 of the storage part with data in the write address of the corresponding memory 120 and the difference and address of write data and also writes the write data in the address of the memory when a PE 103 outputs a write request including the write data and address to one of the storage parts, and a means which updates corresponding parity on the basis of the difference and address stored in the buffer 101 when a check point is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic computer,
In particular, the present invention relates to an electronic computer which can create a checkpoint at a predetermined timing and can recover in a short time even if a failure occurs.

[0002]

2. Description of the Related Art With rapid progress of information processing technology in recent years, there is a demand for high reliability as well as a demand for fast processing of a large amount of data. A highly reliable system guarantees that the data being processed will always be consistent in the event of any failure, and that it can continue its operations after recovery from the failure. System. Moreover, it is required that the processing can be restarted in a short time in order to suppress the performance deterioration.

In such a fault-tolerant system requiring high reliability, it is necessary to ensure data consistency even if some kind of failure occurs and prevent the system from going down. Therefore, in the fault-tolerant system, the failure detection is performed at a predetermined timing, and when the failure is detected, the processing to restore the normal state is performed. There are methods such as using an ECC for detecting a fault in a fault tolerant system and comparing the results by duplicating the CPUs. A checkpoint method (reference: “Processor-and Memory”) is used as a means for restoring a normal state after a failure is detected.
-Based Cheekpoint and Roll
back Recovery ”, COMPUTER, F
eb. 1993, p22-31) is known.

In the checkpoint method, the state of the memory is saved at certain intervals. The operation of saving the state of this memory is called "to generate a checkpoint". When a temporary failure due to noise or the like occurs, the failure can be saved by re-executing from the time when the checkpoint was generated immediately before. When a permanent failure such as hardware destruction occurs, some kind of failure processing, for example,
Processing such as shifting the processing on the CPU in which the abnormality has occurred to another normal CPU is performed, and the processing is re-executed from the time when the checkpoint was generated immediately before. In order to save the memory state, it is conceivable to use a spare memory and copy from the original memory to the spare memory at certain intervals.

In the processor cache level method, write data is written only in the cache unless the copyback type cache is replaced.
It uses the property that it is not reflected in memory. That is, in this method, first, the CPU register is stored in the memory, and the cache flush is performed to generate the checkpoint in the memory. When a failure occurs, CP
Recovery is possible by loading the U register from memory and invalidating the cache. This is because when the CPU accesses the data after invalidating the cache, the data is fetched from the memory in which the data image of the immediately preceding checkpoint is formed.

Further, a failure may occur during the cache flush for generating the checkpoint. In this case, the data at the last checkpoint is partially destroyed, so that there is a problem that the above-mentioned method cannot recover the data. Therefore, a method has been proposed in which the memory is duplicated and even if a failure occurs during writing of one memory bank by the cache flush, another memory bank can recover the failure. In this method, first, data is written in the memory bank A by cache flash. Then again
Write data to memory bank B by cache flash. As a result, even if a failure occurs while writing data in the memory bank A, the memory bank B
Holds the data of the previous checkpoint and can be recovered. If a failure occurs while writing data in the memory bank B, the data in the memory bank A can be copied to the memory bank B, an appropriate failure analysis can be performed, and the processing can be continued. However, such a dual memory system has a drawback in that only half of the mounted memory can be actually used.

Another problem with the processor cache level scheme is that it creates a checkpoint each time a cache replacement is required. This is because dirty cache lines are recorded as the amount of change in data from the immediately preceding checkpoint, and are unrecoverable when those cache lines are flushed to memory. Japanese Patent Publication 6-19722
In Japanese Patent Laid-Open Publication No. 2004-242242, a method is proposed in which write data is temporarily stored using a stack memory (FIFO or associative memory) and written to a duplicated memory at the time of checkpoint generation, but the problem is that the memory usage is large. There is a point. Further, the checkpoint generation method using the stack memory has a drawback that a correct checkpoint cannot be generated when the stack memory overflows.

[0008]

As described above, in the electronic computer to which the conventional processor cache level system is applied, there is a problem that recovery cannot be performed if a failure occurs during the flash. In addition, there is a problem that the memory that can be actually used can use only half of the mounted memory in the method in which the method of duplicating the memory is applied.

Further, in the checkpoint generation method using the stack memory, the amount of memory used is large and
If the stack memory overflows, it is impossible to generate a correct checkpoint.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide an electronic computer capable of recovering from a failure from a checkpoint with a small memory usage amount.

[0011]

According to a first aspect of the present invention, a plurality of processors and a plurality of storage units having a buffer area and a memory area are connected to each other, and a memory area of one storage unit is One address is an electronic computer that forms one memory group with one address in the memory areas of the other storage units, and one of the addresses belonging to the same memory group in the memory area of each storage unit is Or a parity is generated based on data stored at a corresponding address in the memory areas of a plurality of storage sections other than the one storage section, and the parity is generated at a corresponding address of the memory area of the one storage section. A means for storing parity, and a memory containing write data and a write address from any of the processors to a memory area of any of the storage sections. When a request for output is output, the data stored in the address in the memory area where the data is written is read, a difference between the read data and the write data is generated, and the difference and the address are Means for storing the write data in the buffer area of the storage unit and writing the write data to the address in the memory area, and the difference stored in the buffer and the difference when the checkpoint is generated. Means for updating the corresponding parity based on the address.

Preferably, the checkpoint is generated when the remaining amount of any one of the buffers reaches a predetermined value. A second aspect of the invention is configured by interconnecting a plurality of processors and a plurality of storage units having a buffer area and a memory area, wherein one address in the memory area of one storage unit is the other storage section. Of the memory areas of the respective memory units, each of which has one address and one memory group. One of a means for generating a parity based on data stored at a corresponding address of the memory areas of the plurality of storage units, and storing the parity at the corresponding address of the memory area of the one storage unit; When a write request including write data and a write address is output from the processor to the memory area of any one of the storage units, Data stored in an address in the memory area where data is written is read, the read data and the address are paired and stored in the buffer area of the storage unit, and the write data is stored in the memory area. Means for writing to an address, and generating a difference between the read data and the write data stored in the buffer, and updating a corresponding parity based on the generated difference and the address stored in the buffer. And means.

According to a third aspect of the present invention, a plurality of processors and a plurality of storage units having a buffer area and a memory area are connected to each other, and one address in the memory area of one storage unit is A computer that forms one address and one memory group in each memory area of each storage unit, and one of the addresses belonging to the same memory group in each memory area of each storage unit
A parity is generated based on the data stored at the corresponding address of the memory areas of the plurality of storage sections other than one storage section, and the parity is generated at the corresponding address of the memory area of the one storage section. When a write request including write data and a write address is output from any of the processors and the memory area of any one of the storage units to store the data in the memory area. A means for reading the data stored in the address, storing the read data and the address in the buffer area of the storage unit, and writing the write data to the address in the memory area; In response to the write request, an address in the memory area of another storage unit that stores the parity corresponding to the write address included in the write request. It reads less stored parity,
The read parity and the address are paired and stored in the buffer area of the storage unit, and a difference between the write data included in the write request and the read parity is generated. A means for storing the address in a pair in the buffer area of the other storage section, and a difference and the address stored in the buffer area of the other storage section when generating a checkpoint And a means for updating the corresponding parity based on the read data and the address stored in the buffer area of the storage unit to which the write request is given.

According to a fourth aspect of the present invention, a plurality of processors and a plurality of storage units having a buffer area and a memory area are connected to each other, and one address in the memory area of one storage unit is A computer that forms one address and one memory group in each memory area of each storage unit, and one of the addresses belonging to the same memory group in each memory area of each storage unit
A parity is generated based on the data stored at the corresponding address of the memory areas of the plurality of storage sections other than one storage section, and the parity is generated at the corresponding address of the memory area of the one storage section. When a write request including write data and a write address is output from any of the processors and the memory area of any one of the storage units to store the data in the memory area. A means for reading the data stored in the address, storing the read data and the address in the buffer area of the storage unit, and writing the write data to the address in the memory area; In response to the write request, the buffer included in another storage unit that stores the parity corresponding to the write address included in the write request In the region, the means for storing the write data and the address storing the corresponding parity in the set, in generating the checkpoint, the parity stored in the memory area having the said other storage unit,
Based on the write data and the address stored in the buffer area of the other storage unit, and the read data and the address stored in the buffer area of the storage unit to which the write request is given Means for updating the corresponding parity.

On the other hand, a fifth aspect of the present invention is configured by interconnecting a plurality of processors and a plurality of storage units having a buffer area and a memory area, and one address in the memory area of one storage unit is A computer that forms one address and one memory group in the memory areas of the other storage sections, and stores any one of the addresses belonging to the same memory group in the memory areas of the respective storage sections. A checksum is generated based on the data stored in the corresponding address of the memory areas of the plurality of storage sections other than the copy, and the checksum is generated in the corresponding address of the memory area of the one storage section. Means for storing, and a line containing write data and a write address from any of the processors to a memory area of any of the storage units. When a request is output, the data stored in the address for writing data in the memory area is read, a difference between the read data and the write data is generated, and the difference is combined with the address. Means for writing the write data to the address in the memory area and storing the write data in the buffer area of the storage unit, and the corresponding checksum based on the difference and the address stored in the buffer. And means for updating.

According to a sixth aspect of the present invention, a plurality of processors and a plurality of storage units having a buffer area and a memory area are connected to each other, and one address in the memory area of one storage unit is A computer that forms one address and one memory group in each memory area of each storage unit, and one of the addresses belonging to the same memory group in each memory area of each storage unit
A checksum is generated based on the data stored at the corresponding address of the memory areas of the plurality of storage sections other than one storage section, and the checksum is generated at the corresponding address of the memory area of the one storage section. When a write request including write data and a write address is output to the memory area of any one of the storage units from the means for storing the sum and the one of the processors, data writing in the memory area is performed. A means for reading the data stored at the address for performing the operation, storing the read data and the address in the buffer area of the storage unit as a pair, and writing the write data at the address in the memory area. , Based on the read data and the address stored in the buffer and the write data stored in the memory area Characterized by comprising a means for updating the corresponding checksum.

[0017]

According to the present invention, first, by providing a parity relationship between data in a plurality of storage units (for example, memory boards), even if the data in the storage unit or one storage unit itself is destroyed, that storage unit is destroyed. To be able to perform data recovery on. As a result, even if the storage unit is destroyed, the computer can be returned to the checkpoint state before the destruction by replacing the storage unit with another one, and high reliability can be obtained.

Furthermore, in the present invention, in addition to the above configuration,
Various ideas have been added to the process for creating checkpoints. In the first invention, when writing data in the memory, the difference between the old data and the new data and the address are stored in the buffer. The parity is updated based on the buffer difference when the checkpoint is generated.

According to the second aspect of the invention, when writing data in the memory, old data and an address are stored in a buffer. To update the parity, the difference between the old data and the new data is sent from the storage unit that has written the data to the storage unit on the parity side.
The storage unit on the parity side updates the parity based on the difference between the data.

In the third invention, when writing data in the memory, old data and an address are stored in a buffer, the storage unit on the parity side also receives the write data, and the difference between the parity and the write data is written back to the parity. When the checkpoint is generated, the difference between the old data and the parity is taken,
Update the parity.

In the fourth invention, when writing data in the memory, old data and address are stored in a buffer, the storage unit on the parity side also receives the write data, and the difference between the parity and the write data is written back to the parity. At the time of checkpoint generation, the parity is updated by taking the difference between the write data and the old data and the parity.

In the fifth and sixth inventions, a checksum is used instead of the parity in the first and second inventions. Here, in the present invention, in a certain data group, when the data changes to new data,
Parity difference (exclusive OR; xor) utilizes the property of being equal to data difference. Data A,
For B and C, the relational expression for the parity P of those data is: P = A xor B xor C The data A changes to A ′, and the relational expression for A ′, B, C and their parity P ′ is , P ′ = A ′ xor B xor C If the xor of the right side and the left side of the above two expressions is taken, P xor P ′ = (A xor B xor C)
xor (A 'xor B xor C). Since the exchange rule is established in the xor operation, P xor P ′ = (A xor A ′) xor
Since (B xor B) xor (C xor C) B xor B = 0 and C xor C = 0, P xor P ′ = A xor A ′ can be derived. From this, it can be said that the parity difference (xor) is the data difference.

Therefore, according to the present invention, even if a failure occurs, the stored difference and data / parity can be used to easily return to the immediately preceding checkpoint.

Here, conventionally, a memory having the same capacity as the memory capacity for storing the data is required to generate the checkpoint, but according to the present invention, when the memory having the capacity N is used for the data, the parity is used. It is possible to generate a checkpoint with only N / (N-1) in total as the memory capacity including the memory capacity for memory. That is, it is possible to efficiently use the mounted memory capacity by allocating only a part of the memory capacity in the system to the parity area and to obtain high reliability. In addition, it is possible to avoid the overhead of creating checkpoints in all the processors each time data is written back from the buffer to the memory in a certain processor.

Further, according to the present invention, the frequency of checkpoint generation can be easily adjusted by adjusting the capacity of the buffer. This point can be adjusted depending on the processing capacity required for the system and the penalty at the time of failure, and the system can be easily constructed according to the purpose.

Since the checkpoint can be created only when the buffer overflows, the execution is restarted after the buffer is empty, data leaks from the buffer, and an incomplete checkpoint occurs. Can be prevented. In addition, bus congestion can be reduced.

Further, the checkpoint generation processing is performed by the CPU.
By doing so, there is no need to make a memory as a master, so that the circuit scale can be reduced. When updating the parity, it is preferable to update the parity while storing the old parity in the buffer. As a result, even if a failure occurs when updating the parity, the updated parity can be returned to the old state parity of the previous checkpoint.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. (Basic Structure) FIG. 1 is a schematic block diagram of an electronic computer according to an embodiment of the present invention.

The electronic computer of this embodiment comprises a plurality of processors 103 and a memory board comprising a plurality of buffers 101 and memories 102 interconnected by a bus 104.

The processor 103 uses the internal register AL
A known material having U or the like can be used. It is assumed that each processor 103 is provided with a cache memory 105.

The memory area of the memory 102 is divided into a plurality of blocks. In addition, in the plurality of memories 102,
It is assumed that one memory space is formed. In this embodiment, as shown in FIG. 2, a set of corresponding memory blocks of the memories 102 _{1 to} 102 ₄ is considered as one memory group (for example, MG1 in FIG. 2), and any one memory block in the memory group is considered. Is assigned as the parity memory. For example, in the memory group MG1 of FIG.
Parity 1 stored in the parity memory is parity 1 = data 11 xor data 12 xor
It is represented by data 13. However, xor represents an exclusive OR.

Basically, one parity memory block may be assigned to one memory group, but as shown in FIG. 2, the parity memory blocks are evenly assigned to each memory 102. Is preferred. This is because each time a write request is made to a certain memory block, the write is also made to the parity memory block. Therefore, if the allocation of the parity memory block is concentrated on a part of the memory, the access may be concentrated on the memory. This is because it can be considered. However, it is free to use a specific memory exclusively for the parity memory due to the circumstances of the system.

The correspondence relationship between each memory group and the memory address for storing the parity in each memory group are tabulated or formulated so that they can be calculated.

The buffer 101 is a storage for temporarily storing data, and can be realized by a FIFO, for example. Each buffer 101 has a plurality of entries as shown in FIG. 3, and each entry stores a pair of difference data and an address and a pair of old data and an address, as described later.

The bus 104 may be an address data multiplex type or a non-multiplex type. A read request or a write request is issued from the processor 103, and the request passing through the cache 105 is sent to a predetermined memory board via the bus 104.

The memory board which has received the write request performs processing for old and new data and old and new parity as described in each embodiment described later. To generate a checkpoint, the contents of all caches 105 are stored in the memory 10
2), the status of all processors 103 is saved, the necessary processing described later is performed based on the information in the buffer 101 of each memory 102, and then the contents of the buffer 101 are deleted.

The checkpoint is generated at the earliest when the area of the buffer 101 overflows (or the area of a predetermined capacity is used up or the remaining capacity reaches a predetermined value) when the processor 103 If the checkpoint is not notified to the user or if the checkpoint is not generated for a long time, the penalty at the time of failure becomes large, so it is preferable to perform it at appropriate time intervals. However, since the buffer 101 is written even when the checkpoint is generated, the checkpoint must be generated before the buffer 101 is completely overflowed.

In this embodiment, it is assumed that a known failure detecting means (not shown) is provided by, for example, the OS. The failure detection unit monitors whether or not a failure has occurred at a predetermined timing, and when it detects a failure, it starts a failure recovery process. When the temporary failure due to noise or the like occurs, the started failure recovery processing is executed again from the time when the checkpoint was generated immediately before.

On the other hand, when a permanent failure such as hardware destruction occurs, after performing some kind of failure processing, for example, processing such as shifting the processing on the CPU where the abnormality has occurred to another normal CPU, It is conceivable to perform a process for re-execution from the time when the checkpoint was generated immediately before.

In the present embodiment, the system having a cache memory has been described in detail as an example, but the present invention is not limited to the system having the cache memory and can be applied to the system having no cache memory. . In this case, in the checkpoint generation processing and the failure recovery processing, it is sufficient to omit the processing related to the cache.

Further, in the present embodiment, the memory board is composed of the buffer 101 and the memory 102, but various embodiments such as a mode in which a processor is also mounted on the memory board are conceivable.

Further, in this embodiment, a system comprising four CPUs and four memory boards is used, but the present invention can be applied without limitation to the number of CPUs and memory boards.

Examples will be described more specifically below.
In the following description, new data or new data refers to data to be stored in the memory 102, and old data or old data is stored in the memory 102 before the storage.
The data stored in. Also, new parity or new parity refers to the corresponding parity after storing new data in the memory 102, and old parity or old parity refers to the corresponding parity stored in the memory 102 at the time of storage. I shall say.

(First Embodiment) First, a first embodiment of the present invention will be described. First, the concept of this embodiment will be described.
FIG. 4 is a conceptual diagram of this embodiment.

In the present embodiment, the old and new data and the old and new parity are operated as follows in the configuration described with reference to FIGS. i) Data When writing new data to the memory 102 ₁ in response to a write request from the processor 103 ₁ , “difference between old data and new data” and “memory 102 ₁ (where old data and new data are stored)” set aside in the buffer 101 ₁ to the address "to the set.

An exclusive OR circuit (xor circuit) 121 can be used to calculate the difference between the old data and the new data. That is, the difference can be calculated by the difference between old and new data = old data xor new data.

New data is written to the address position in the memory 102 ₁ . ii) Parity Although it is necessary to update the corresponding parity by rewriting the above data, in the present embodiment, this parity is updated when the checkpoint is generated.

The new parity is given as new parity = old parity xor difference between old and new data.

[0049] The first time the parity update, the old parity, and the parity storage address and a set of memory 102 in ₂ for storing the parity set aside buffer 101 ₂ of the memory 102 _2.

In the present embodiment, it is possible to easily backtrack to the immediately preceding checkpoint by using the difference information existing in the buffer to recover from the failure, and to easily update the parity using the difference information in this buffer. That is, the difference information in the buffer can be used for both failure recovery and parity update.

In the present embodiment, when a failure occurs, the rollback to the immediately preceding checkpoint is performed and the re-execution is performed, so that there is an advantage that the parity does not always need to be updated at the time of writing data. That is, the creation of the new parity and the storage of the old parity can be postponed until the checkpoint is generated.

FIG. 5 shows the flow of processing for updating the parity. The function of this processing may be realized by dedicated hardware or software processing.
It may be incorporated into S.

First, data (difference between new and old data and address) is read from one entry of one buffer (step S1). The memory board of the corresponding parity and its address are obtained from the address value (step S
2).

The old parity is read from the address (step S3). The difference between the difference and the old parity is taken to generate a new parity, and the parity is updated (step S
4).

The above processing is sequentially applied to all entries in all buffers (step S5, step S).
6). FIG. 6 is a routine for failure recovery. The function of this processing may be realized by dedicated hardware or software processing, or may be incorporated in the OS. This failure recovery processing function is activated when a known failure detection mechanism (not shown) detects a failure.

First, data (difference between new and old data and address) is read from one entry of one buffer (step S11). The difference between the new data at the designated address and the above difference is taken, and the data is returned to the value of the immediately preceding checkpoint (old data) (step S12).

The above processing is sequentially applied to all entries in all buffers (step S13, step S1).
4). After that, for all the memory boards whose data has been destroyed, the difference between each data and parity of the same memory group of the memory boards whose data has not been destroyed is taken, and the data of the board whose data has been destroyed is recovered (step S15, Step S16).

Next, an example of checkpoint generation processing will be described. First, the internal register of the CPU is saved in the memory. Next, the rewritten portion of the cache is flushed. With these, a checkpoint of data can be generated on the memory. As the next step, the old parity is updated to the new parity (the above-described processing of the flowchart of FIG. 5 is performed). That is, the buffer of the other memory board has a difference between the data corresponding to the parity and the old data.
Since the difference between the new data and the old data is equal to the difference between the new parity and the old parity, the parity can be updated to the new parity by reading the difference between the new data and the old data.

As a concrete example, in the configuration of FIG. 1, the address area of the board A is 0 as shown in FIG.
x00000-0x0FFFF, the address area of board B is 0x10000-0x1FFFF, the address area of board C is 0x20000-0x2FFFF, and the address area of board D is 0x30000-0x3FFF.
Consider the case of F. However, 0x indicates that the number following it is a hexadecimal number.

For example, the parity of the data A at the address 0x100 of the board A, the data B at the address 0x10100 of the board B, and the data C at the address 0x20100 of the board C is the address 0x3 of the board D.
It is stored in the address 0100.

The processing for old and new data / parity shown in FIG. 8 will be described. Data A = (0001), Data B = (0010),
If the data C = (0011), the parity to be stored in the board D is the exclusive OR of the three data A, B, and C (0000).

It is now assumed that (0100) is written in the address 0x100 of the board A. In the buffer of board A, the difference between the old data A and the data to be written, that is, (0001) xor (0100) = (010
1) is stored with the address 0x100.

When generating a checkpoint, the processor goes to check the contents of the buffer. 0x in the buffer
Since the change in the data at address 100 is recorded and the difference is (0101), the parity at address 0x30200 is changed to (0000) xor (0101) = (0101). In fact, this new parity is the new data A (0100), data B (0010) and data C.
It is the exclusive OR of (0011).

It should be noted that the old parity (0000) is stored in the buffer in association with the address so that the old parity (0000) can be recovered even if a failure occurs at the time of updating the parity. When all the parity updates have been completed, the buffer is cleared and used as a new checkpoint.

Next, the fault processing shown in FIG. 9 will be described. Consider failure handling when a memory board fails. In this case, it is necessary to restore the data to the data at the time of the previous checkpoint.

First, each board is returned to the old data state according to the difference information existing in the buffer. At that point, an arithmetic relationship in which the difference between the data of each board becomes the parity should be established, and therefore the lost data can be restored by the backward calculation.

As in the previous example, data A (000
1), data B (0010), and data C (0011), when data A is rewritten as (0100), it is assumed that data B currently on board B is broken.

The processor goes to look at the buffer on each board. In the buffer of the board A, it is recorded that the data A at the address 0x100 changes and the difference is (0101).

The difference between the current data A (0100) and its difference (0101) is calculated, and the data A is (000
After writing back 1), data A (0001) and data C
Taking the difference between (0011) and parity D (0000),
The data B (0010) can be recovered.

As described above, in the past, a memory having the same capacity as the memory for storing data was required to generate a checkpoint, but according to this embodiment, N memory boards for data are used. When used, the total memory capacity is N / (N
-1) It is possible to generate a checkpoint with only the memory capacity for one sheet. That is, it is possible to efficiently use the mounted memory capacity by allocating only a part of the memory capacity in the system to the parity area and to obtain high reliability. In addition, it is possible to avoid the overhead of creating checkpoints in all the processors each time data is written back from the buffer to the memory in a certain processor.

Further, by adjusting the capacity of the buffer, it becomes possible to easily adjust the frequency of checkpoint generation. This point can be adjusted depending on the processing power required for the system and the penalty at the time of failure,
It is possible to easily build a system according to the purpose.

Since the checkpoint can be created only when the buffer overflows, the bus congestion can be reduced. Further, since the CPU performs the checkpoint generation process, it is not necessary to use the memory as a master, so that the circuit scale can be reduced.

Such an effect can be similarly obtained in each of the embodiments described later, but the repeated description in each embodiment will be omitted. Here, FIG. 10 shows an example of a circuit for storing the difference between the old data and the new data in the buffer 101. In this circuit, when a write request is given via the bus, first, data is read from the memory 102 at the same address as the write request, and the read data register 60 is read.
Read old data into 4. Then, according to the write request,
At the same time as writing the data to the memory 102, the exclusive OR of the old data in the read data register 604 is xored.
It is calculated by the circuit 603, and the output value of this xor circuit 603 is written in the buffer 101 together with the address.

In the above description, the memory board is divided into the memory and the buffer, but the same memory module may be divided into the buffer area and the memory area. In FIG. 11, the memory module 710 is divided into a buffer area and a memory area.

The procedure for writing data in the configuration of FIG. 11 is shown below. Data is input to the data register 702 and an address is input to the address register 703 from the bus 104. The address is selected by multiplexer 709 and goes to memory module 710. In the memory, the value of that address is read,
A value is entered in the read data register 707.

The value entered in the data register 702 is selected by the multiplexer 705, passes through the buffer 706, and is written in the memory. As the address, the value of the address register 703 is given as in the above. When a DRAM is used as the memory, this operation can be easily realized by using the read / modify / write function.

The xor circuit 704 takes the difference between the output data of the read data register 707 and the output data of the data register 702, and this difference is selected by the multiplexer 705 and becomes the data of the memory module 710. As the address, the value of the stack pointer 708 is selected by the multiplexer 709. This address is an address in the buffer area. Since the address corresponding to the difference data also needs to be registered in the buffer, after the difference data is stored, the value of the address register 703 is selected by the multiplexer and stored in the buffer pointed to by the stack pointer 708.

(Second Embodiment) Next, a second embodiment of the present invention will be described. First, the concept of this embodiment will be described.
FIG. 12 is a conceptual diagram of this embodiment.

In this embodiment, the old and new data and the old and new parity are operated as follows in the configuration described with reference to FIGS. i) Data When writing new data to the memory 102 ₁ in response to a write request from the processor 103 ₁ , the old data is paired with an address and stored in the buffer 101 ₁ .

From the written memory board, x
The difference between the old data and the new data obtained by the OR circuit 121 ₁ is sent to the memory board having the parity. ii) Parity In a memory board that has parity, the old parity is updated to the new parity based on the above difference sent. The new parity is obtained by new parity = old parity xor difference data (= old parity xor old data xor new data).

[0081] old parity, and to address a set is stored in the buffer 101 _2. In this embodiment, at the time of failure,
Old data and old parity are present in the buffer, and the processor can read these data and parity from the buffer and write them to the corresponding memory addresses to recover to the previous checkpoint.

FIG. 13 shows an example of a circuit that realizes this method. The following operations are performed on the memory board on the data side. The bus interface circuit 902 is
When the write request is received, the address line of the memory 102 is driven and the memory read is executed. Since the read data is output to the data line of the memory 102, the read data is stored in the read data register 904, and the buffer 1
The read data is also entered in 01.

When the write request is received, the address line of the memory 102 is driven and the memory write is executed along with the above operation. When writing to the memory 102, at the same time, the difference between the old data stored in the read data register 904 and the write data output to the data line of the memory 102 is calculated, and the request is output to the bus via the bus interface circuit 902.

The memory board on the parity side performs the following operations. The memory board on the parity side receives the request issued on the bus and executes the memory read. Since the read data is output to the data line of the memory 102, the read data is stored in the read data register 904, and the buffer 101 also stores the read data.

The difference between the data received by the request and the data in the read register 904 is written in the memory 102. By these operations, the parity can be updated.

FIG. 14 shows a routine for failure recovery in this embodiment. The function of this processing may be realized by dedicated hardware or software processing, or may be incorporated in the OS. This failure recovery processing function is activated when a known failure detection mechanism (not shown) detects a failure.

First, data (old data and address) is read from one entry of one buffer (step S31). By rewriting the data of the designated address to the old data, the data is returned to the value of the immediately preceding checkpoint (step S32).

The above processing is sequentially applied to all entries in all buffers (step S33, step S3).
4). After that, for all the memory boards whose data has been destroyed, the difference between each data and parity of the same memory group of the memory boards whose data has not been destroyed is taken, and the data of the board whose data has been destroyed is recovered (step S35, Step S36).

FIG. 15 shows an example of the bus interface circuit. In this circuit, first, when a bus request is received, an address enters the address register 1005 and is output as a memory address. In the data write operation, the data is output as memory data via the FIFO 1002 and the write data register 1004. On the other hand, in the operation of sending data, when reading the data in the memory, when reading the buffer where old data exists,
Since the data difference may be transmitted in some cases, these are selected and read data register 1003 and FIFO 1002 are selected.
And then output on the bus. The address of the request when sending the data difference is the address register 1005.
The address of the parity corresponding to the write data is calculated by the address generator 1006 on the basis of the address of (1), and is stored in the address register 1007 for the master mode, and is transmitted at the time of request.

(Third Embodiment) Next, a third embodiment of the present invention will be described. In the method of storing old data in the buffer as in the above-described embodiment, since the difference between the old and new data is sent to the memory board on the parity side from the board on which the writing was performed, two transactions can be performed by one writing. Occur. In this embodiment, the number of transactions generated by one writing is reduced to one.

First, the concept of this embodiment will be described. FIG.
6 is a conceptual diagram of this embodiment. In this embodiment, FIG.
In the configuration described in FIG. 3, the old and new data and the old and new parity are operated as follows.

I) Data When writing new data in the memory 102 ₁ in response to a write request from the processor 103 ₁ , the old data is paired with an address and stored in the buffer 101 ₁ .

Ii) Parity Here, when the law that the difference between old and new parity is equal to the difference between old and new data is expressed by an equation, Pnew xor Pold = Dnew xor
Here, Pnew is new parity, Pold is old parity, Dnew is new data, and Dold is old data.

By transforming this, Pnew = Pold xor Dnew xor
It becomes Dold.

When data is written, a write request is issued on the bus. In this embodiment, the memory board that transfers the data to the memory board of the corresponding address and stores the parity corresponding to the data Forward it to.

For a memory board with parity, x
The OR circuit 121 takes the difference P ′ P ′ = Pold xor Dnew between the old parity and the write data (new data), and writes the P ′ back to the memory.

[0097] the old parity, and to address a set is stored in the buffer 101 _2. According to this method, the transaction of data write is performed only once, and the transfer of the extra difference information can be deleted.

The parity update routine at the time of checkpoint generation in this embodiment is the same as that shown in FIG. That is, the buffer 1 of the board on which the writing was performed
In 01 ₁ , old data exists. The processor reads the old data from the buffer 101 ₁ , sends the old data to the memory board on the parity side, and takes the difference between P ′ and the old data corresponding to the data, so that Pnew = P ′ xor Dold = Pold xor It becomes Dnew xor Dold and can be updated to a new parity.

In this embodiment, the memory board on the parity side stores old parity in the buffer and the memory board on the data side stores old data. Therefore, when a failure occurs, the check point immediately before is restored. It becomes possible to do. The routine for failure recovery is the same as that shown in FIG.

FIG. 17 shows an example of a circuit that realizes this method. In this circuit, first, when the bus interface circuit 1202 receives a write request, it executes a memory read and puts the read data in the buffer 101. Next, execute a memory write to write the data to memory 1.
Write in 02.

In the memory board on the parity side, when the bus interface circuit 1202 receives the write request,
The parity of the corresponding address is read from the memory 102 to the read data register 1204. Next, xor12
Write data and read data register 1204 at 05
The difference of the data is taken and written in the memory 1206.

When a checkpoint is generated, necessary CPU registers are saved, cache flush is performed, and data older than the buffer 101 is stored in the CPU.
Then, the CPU sends a parity update request carrying the old data to the board on the parity side. In the board on the parity side which has received the request, P'is read from the memory into the read data register 1204,
After that, the old data and the read data register 1204 received by the bus interface circuit at xor 1205.
Is taken and written in the memory 1206.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described. First, the concept of this embodiment will be described.
FIG. 18 is a conceptual diagram of this embodiment.

Generally, in this embodiment, when data is written, the memory board on the parity side only performs the process of storing the write data in the buffer. When the checkpoint is generated, the data in the buffer is used. Pnew = Pold xor Dnew xor
Parity update is performed by Dold processing (this processing may be dedicated hardware or software). This can simplify the processing procedure at the time of writing.

More specifically, in the present embodiment, FIGS.
In the configuration described in, the old and new data and the old and new parity are operated as follows. i) Data When writing new data to the memory 102 ₁ in response to a write request from the processor 103 ₁ , the old data and the address are paired and stored in the buffer 101 ₁ .

[0106] In the memory board ii) Parity Parity side, set aside buffer 101 ₂ and the new data to address a set. Memory 1
The old parity is held in 02 ₂ .

When the checkpoint is generated, the buffer 10
After obtaining the old parity from 1 ₁ , the memory 102 ₂ is set to new parity = old parity xor new data xor.
Update with old data.

[0108] the old parity, set aside in the buffer 101 ₂ in the address and the set. In this embodiment, the processing at the time of failure can be restored to the previous checkpoint by the old data existing in the buffer and the old parity stored in the board on the parity side, as in the method described above.

The parity update routine at the time of checkpoint generation is the same as that shown in FIG. In the buffer,
Since the new data or the old data and its address exist, the parity is updated by taking the difference from the corresponding parity.

The routine for recovering from a failure is similar to that shown in FIG. Here, FIG. 19 shows an example of a circuit that realizes this method. Bus interface circuit 140
When receiving the write request, the second memory reads the memory, puts the old data in the buffer 101, and then writes the data. When receiving the write request, the board on the parity side puts the data in the buffer 101. At the time of checkpoint generation, old data is read from the buffer 101 from the data side board, and new data is read from the buffer 101 from the parity side board to obtain the difference from the parity and update the parity. In addition, even if a failure occurs while updating the parity, the old parity is stored in the buffer 101 so that the previous checkpoint can be returned to.
Save it in.

A timer interrupt may be used to activate checkpoint generation. This allows
After a certain period of time, a timer interrupt occurs, and a checkpoint is generated by the interrupt routine.

Frequent writes from the processor
When the buffer 101 of the memory board overflows, failure recovery cannot be performed. Therefore, when the buffer is about to overflow, it is preferable to interrupt the processor from the memory board and generate a checkpoint.

(Other Embodiments) In each of the above-described embodiments, it has been considered that the difference of data is taken as the difference information existing in the parity or the buffer, but the present invention can be implemented by taking the checksum of the data. Is.

It is assumed that the data A on the board A, the data B on the board B, the data C on the board C, and the checksum S on the board D have a relationship of A xor B xor C xor S = 0.

When the data A is rewritten to A ', A'-A is stored in the buffer. When generating the checkpoint, the checksum may be rewritten as S '= S- (A'-A).

Because A'xor B xor C xor S '= A' xor B xor C xor S- (A'-A) = A xor B xor C xor S = 0, the sum of the new data and the new checksum Is 0.

In the event of a failure, broken data can be recovered using the buffer difference information and checksum.
This method can be easily realized by appropriately modifying each of the above-described embodiments. The present invention is not limited to the above-described embodiments, and can be variously modified and implemented without departing from the scope of the invention.

[0118]

According to the present invention, data in a plurality of storage units (for example, memory boards) are related to each other by a parity or a checksum, and the difference information between the data is stored so that the data between the old and new data can be stored. By utilizing the property that the difference of (1) is the same as the difference between the old and new parity (checksum), it is possible to generate a checkpoint and recover the failure by backtracking to the immediately preceding checkpoint.

As a result, according to the present invention, even if the data in the storage unit or one storage unit itself is destroyed, the data in the storage unit can be easily recovered and high reliability can be obtained. In addition, it is possible to generate a checkpoint with a smaller memory capacity than before.

[Brief description of drawings]

FIG. 1 is a schematic system diagram showing an electronic computer according to the present invention.

FIG. 2 is a diagram for explaining a logical configuration given to a plurality of memories in FIG.

FIG. 3 is a diagram for explaining the configuration of the buffer in FIG.

FIG. 4 is a conceptual diagram of a first embodiment of the present invention.

FIG. 5 is a flowchart of a process for updating parity.

[Fig. 6] Flow chart of failure recovery processing

FIG. 7 is a diagram for explaining an example of data and parity stored in a plurality of memories.

FIG. 8 is a diagram for explaining a specific example of each processing procedure of the present embodiment.

FIG. 9 is a diagram for explaining a specific example of failure processing.

FIG. 10 is a diagram showing an example of the internal configuration of the memory board according to the first embodiment of the invention.

FIG. 11 is a configuration diagram of a circuit that realizes a buffer and a memory by dividing a memory module.

FIG. 12 is a conceptual diagram of a second embodiment of the present invention.

FIG. 13 is a diagram showing an example of an internal configuration of a memory board according to a second embodiment of the present invention.

FIG. 14 is a flow chart of failure recovery processing.

FIG. 15 is a diagram showing a configuration example of a bus interface according to a second embodiment of the present invention.

FIG. 16 is a conceptual diagram of a third embodiment of the present invention.

FIG. 17 is a diagram showing an example of an internal configuration of a memory board according to a third embodiment of the present invention.

FIG. 18 is a conceptual diagram of a fourth embodiment of the present invention.

FIG. 19 is a diagram showing an example of an internal configuration of a memory board according to a fourth embodiment of the present invention.

[Explanation of symbols]

101 ... Buffer, 102 ... Memory, 103 ... Processor, 104 ... Bus, 105 ... Cache, 121 ... Exclusive OR circuit (xor circuit), 603 ... Exclusive OR circuit (xor circuit), 604 ... Read data register, 6
05 ... bus interface, 702 ... data register,
703 ... Address register, 704 ... Exclusive OR circuit (xor circuit), 705 ... Multiplexer, 706 ... Tristate buffer, 707 ... Read data register, 708 ... Stack pointer, 709 ... Multiplexer, 710 ... Memory module, 711 ... Memory Controller, 902 ... Bus interface, 904 ... Read data register, 905 ... Exclusive OR circuit (xor circuit), 1002 ... Buffer (FIFO), 1003 ... Bus interface, 1004 ... Read data register,
1005 ... Address register, 1006 ... Address generator, 1202 ... Bus interface, 1204 ...
Read data register, 1205 ... Exclusive OR circuit (xor circuit), 1402 ... Bus interface

Front Page Continuation (72) Inventor Kuninori Tanaka 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research and Development Center, Inc. (72) Inventor Shigeaki Iwasa Komukai Toshiba-cho, Kosaki-ku, Kawasaki-shi, Kanagawa Incorporated company Toshiba Research and Development Center (72) Inventor Hiroshi Sakai 2-9 Suehiro-cho, Ome, Tokyo Stock company Toshiba Ome factory (72) Inventor Takashi Omizo 1 Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Banchi Co., Ltd. Toshiba Research & Development Center

Claims (7)

[Claims] 1. A plurality of processors and a plurality of storage sections each having a buffer area and a memory area are connected to each other, and one address of the memory areas of one storage section is stored in another storage section. An electronic computer that forms one address and one memory group in each memory area, and a plurality of addresses other than one of the memory areas of the memory areas of each memory section that belong to the same memory group. Parity is generated based on the data stored at the corresponding address in the memory area of the storage unit of
A means for storing the parity at a corresponding address in a memory area of one storage section, and a write request including write data and a write address from any of the processors to a memory area of the storage section In this case, the data stored in the address for writing data in the memory area is read, a difference between the read data and the write data is generated, and the difference is combined with the address to generate the difference. A unit for storing the write data in the buffer area of the storage unit and writing the write data in the address in the memory area; and a means for generating a checkpoint based on the difference and the address stored in the buffer. And a means for updating the corresponding parity. 2. The electronic computer according to claim 1, wherein a checkpoint is generated when the remaining amount of any one of the buffers reaches a predetermined value. 3. A plurality of processors and a plurality of storage sections each having a buffer area and a memory area are connected to each other, and one address of the memory areas of one storage section is stored in another storage section. An electronic computer that forms one address and one memory group in each memory area, and a plurality of addresses other than one of the memory areas of the memory areas of each memory section that belong to the same memory group. Parity is generated based on the data stored at the corresponding address in the memory area of the storage unit of
A means for storing the parity at a corresponding address in a memory area of one storage section, and a write request including write data and a write address from any of the processors to a memory area of the storage section In this case, the data stored in the address for writing the data in the memory area is read, the read data and the address are paired and stored in the buffer area of the storage unit, and the write data is stored. Means for writing to the address in the memory area, and generating a difference between the read data and the write data stored in the buffer, based on the generated difference and the address stored in the buffer An electronic computer comprising: means for updating the corresponding parity. 4. A plurality of processors and a plurality of storage sections each having a buffer area and a memory area are connected to each other, and one address of the memory areas of one storage section is stored in another storage section. An electronic computer that forms one address and one memory group in each memory area, and a plurality of addresses other than one of the memory areas of the memory areas of each memory section that belong to the same memory group. Parity is generated based on the data stored at the corresponding address in the memory area of the storage unit of
A means for storing the parity at a corresponding address in a memory area of one storage section, and a write request including write data and a write address from any of the processors to a memory area of the storage section In this case, the data stored in the address for writing the data in the memory area is read, the read data and the address are paired and stored in the buffer area of the storage unit, and the write data is stored. A means for writing to the address in the memory area, and an address-stored parity in a memory area of another storage unit storing a parity corresponding to the write address included in the write request in response to the write request And stores the paired read parity and the address in the buffer area of the storage unit. At the same time, means for generating a difference between the write data and the read parity included in the write request, and storing the difference and the address in the buffer area of the other storage unit, When generating a checkpoint, the difference and the address stored in the buffer area of the other storage unit, and the read stored in the buffer area of the storage unit to which the write request is given. An electronic computer comprising: means for updating the corresponding parity based on the data and the address. 5. A plurality of processors and a plurality of storage sections having a buffer area and a memory area are connected to each other, and one address of the memory areas of one storage section is stored in another storage section. An electronic computer that forms one address and one memory group in each memory area, and a plurality of addresses other than one of the memory areas of the memory areas of each memory section that belong to the same memory group. Parity is generated based on the data stored at the corresponding address in the memory area of the storage unit of
A means for storing the parity at a corresponding address in a memory area of one storage section, and a write request including write data and a write address from any of the processors to a memory area of the storage section In this case, the data stored in the address for writing the data in the memory area is read, the read data and the address are paired and stored in the buffer area of the storage unit, and the write data is stored. A unit for writing to the address in the memory area; and, in response to the write request, the write data in the buffer area of another storage unit that stores the parity corresponding to the write address included in the write request. Generate a checkpoint and a means to store it as a pair with the address storing the corresponding parity In the storage unit to which the parity stored in the memory region of the other storage unit, the write data and the address stored in the buffer region of the other storage unit, and the write request are given. And a means for updating the corresponding parity based on the read data and the address stored in the buffer area of the electronic computer. 6. A plurality of processors and a plurality of storage sections having a buffer area and a memory area are connected to each other, and one address of the memory areas of one storage section is stored in another storage section. An electronic computer that forms one address and one memory group in each memory area, and a plurality of addresses other than one of the memory areas of the memory areas of each memory section that belong to the same memory group. Generate a checksum based on the data stored at the corresponding address in the memory area of
Means for storing the checksum at a corresponding address in a memory area of the one storage unit, and write data including write data and a write address from one of the processors to a memory area of the one storage unit. When the request is output, the data stored at the address in the memory area where the data is written is read, a difference between the read data and the write data is generated, and the difference is combined with the address. Means for storing the write data in the buffer area of the storage unit and writing the write data in the address in the memory area, and the corresponding checksum based on the difference and the address stored in the buffer. And a means for updating the computer. 7. A plurality of processors and a plurality of storage sections each having a buffer area and a memory area are connected to each other, and one address of the memory areas of one storage section is stored in another storage section. An electronic computer that forms one address and one memory group in each memory area, and a plurality of addresses other than one of the memory areas of the memory areas of each memory section that belong to the same memory group. Generate a checksum based on the data stored at the corresponding address in the memory area of
Means for storing the checksum at a corresponding address in a memory area of the one storage unit, and write data including write data and a write address from one of the processors to a memory area of the one storage unit. When the request is output, the data stored in the address in the memory area where the data is written is read, and the read data and the address are paired and stored in the buffer area of the storage unit. Means for writing write data to the address in the memory area, and updating a corresponding checksum based on the read data and the address stored in the buffer and the write data stored in the memory area. An electronic computer having means.