JP2015138275A - Error correction detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve trade-off between efficient memory access and redundancy of user data.SOLUTION: An error correction detection device 2, in each generation of partial rewriting of user data, stores differential data caused by the partial rewriting in a table correspondingly to an address in which the partial rewriting is generated. When performing error correction detection of the user data, the error correction detection device 2 reflects the differential data to the partially rewritten user data and applies parity data before the partial rewriting to the user data to which the differential data is reflected to perform error correction detection of the user data. Since it is unnecessary to perform recalculation of ECC parity in the partial rewriting of the user data, memory access can be efficiently performed. In addition, since a period in which the ECC parity is invalidated is not generated, performance reduction due to the redundancy of the user data can be prevented.

Description

  The present invention relates to an error correction detection apparatus that applies parity data to user data and performs error correction detection of the user data.

  Conventionally, as a technique for preventing a decrease in memory access throughput for a nonvolatile random access memory, there is a technique of dynamically controlling ECC (Error Check and Correct) parity calculation in accordance with an access unit. Specifically, this is a method of defining a flag (valid flag) indicating whether the ECC parity is valid or invalid and periodically recalculating the ECC parity according to the flag. In this method, by recalculating ECC parity periodically, it is not necessary to recalculate ECC parity at the time of partial rewriting of user data. As a result, efficient memory access can be realized (see, for example, Patent Document 1).

JP 2013-134595 A

  However, in the method of Patent Document 1, since the ECC parity is recalculated using a periodic timer interrupt as a trigger, the ECC parity is invalid in the period from the timing after partial rewriting of user data to the timing of the next timer interrupt. It becomes. As a result, there has been a problem that the performance is lowered in terms of user data redundancy.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an error correction detection apparatus capable of eliminating the trade-off between efficient memory access and user data redundancy. is there.

  According to the first aspect of the present invention, the nonvolatile random access memory has a plurality of memory cells each capable of random access. The parity data generating means generates parity data by calculating ECC parity for user data stored in the memory cell. The error correction detection means applies parity data to the user data and detects error correction of the user data. The difference data generation means generates difference data indicating a difference between the user data before the partial rewrite and the user data after the partial rewrite in response to the partial rewrite of the user data stored in the memory cell. . The table holding unit holds a table capable of storing the difference data generated by the difference data generating unit.

  Each time the partial rewriting of the user data stored in the memory cell occurs, the error correction detection means stores the difference data by the partial rewriting in the table in association with the address where the partial rewriting occurs. When the error correction detection means performs error correction detection of user data, the difference data stored in the table is reflected on the user data after partial rewriting, and the user data reflecting the difference data is reflected. On the other hand, the parity data generated by the parity data generating means is applied before partial rewriting to detect error correction of the user data.

  That is, the difference data indicating the difference from the user data at the time of calculating the ECC parity is held, and the difference data can be always reflected on the user data after the partial rewriting, so that the user data before the partial rewriting can be reflected. Can always be generated. As a result, it is not necessary to recalculate ECC parity at the time of partial rewriting of user data, so that memory access can be performed efficiently. In addition, since a period in which the ECC parity is invalid does not occur, it is possible to prevent performance degradation due to user data redundancy. As a result, the trade-off between efficient memory access and user data redundancy can be eliminated.

Functional block diagram showing a first embodiment of the present invention Figure showing a table flowchart The figure which shows transition of the memory cell when partial rewriting of user data occurs The figure which shows the transition of the table when partial rewriting of user data occurs The flowchart which shows the 2nd Embodiment of this invention. The flowchart which shows the 3rd Embodiment of this invention.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. The microcomputer 1 includes an error correction detection device 2 and a peripheral circuit 12. The error correction detection apparatus 2 includes a CPU (Central Processing Unit) 3, a ROM (Read Only Memory) 4, a nonvolatile RAM (Random Access Memory) 5 (nonvolatile random access memory), an ECC (Error Check and Memory). Correct) circuit 6 (parity data generating means) and memory data monitoring circuit 7 are provided. The CPU 3, ROM 4, nonvolatile RAM 5, ECC circuit 6, and memory data monitoring circuit 7 are interconnected via a bus 8. The peripheral circuit 12 is also connected to the bus 8 together with the circuits constituting the error correction detection apparatus 2 described above.

  The ROM 4 stores a control program executed by the CPU 3. The CPU 3 controls the overall operation of the microcomputer 1 by reading and executing a control program stored in the ROM 4. The nonvolatile RAM 5 includes a plurality of memory cells that can be accessed randomly. Each of the plurality of memory cells can store user data. When an ECC parity calculation command is input from the CPU 3, the ECC circuit 6 calculates ECC parity for the user data stored in the memory cell, generates parity data, and assigns the generated parity data to the user data. To do.

  The memory data monitoring circuit 7 includes an error correction detection circuit 9 (error correction detection means), a difference data generation circuit 10 (difference data generation means), and a table holding circuit 11 (table holding means), which are stored in the RAM 5. The user data and parity data being monitored are monitored. When an error correction detection command is input from the CPU 3, the error correction detection circuit 9 applies parity data to user data and performs error correction detection of the user data. Error correction detection refers to detecting and correcting a 1-bit error in user data, or detecting an error of 2 bits or more in user data. When the difference data generation circuit 10 receives a difference data creation command from the CPU 3 every time partial rewrite (partial update) of user data occurs, the difference data generation circuit 10 indicates a difference between user data before partial rewrite and user data after partial rewrite. Generate difference data.

  The table holding circuit 11 holds the table shown in FIG. 2 using a part of the storage area of the RAM 5. The table holding circuit 11 adds one record when a record addition command is input from the CPU 3 every time partial rewriting of user data occurs. One record includes difference data (0b0000) indicating a difference between user data before partial rewriting and user data after partial rewriting, an address (0x0000) indicating an area where the partial rewriting has occurred, and a time when the table is initialized. The number of times of rewriting (n (n is a natural number), the number of times of partial rewriting) indicating the number of times of rewriting. The peripheral circuit 12 is, for example, an AD conversion circuit that AD converts data, a data communication circuit that controls data communication, and the like.

  Next, the operation of the above configuration will be described with reference to FIGS. The CPU 3 executes processing shown in FIG. 3 in relation to the present invention. For example, the CPU 3 outputs an ECC parity calculation command to the ECC circuit 6 at a predetermined ECC parity calculation timing, and calculates the ECC parity for all user data stored in the memory cell. Generate parity data. Then, the CPU 3 gives the generated parity data to the corresponding user data (S1).

  Next, the CPU 3 initializes the table shown in FIG. 2 (S2), and determines whether or not partial rewriting of user data has occurred (S3). If the CPU 3 determines that partial rewriting of user data has occurred (S3: YES), the CPU 3 outputs a differential data creation command to the differential data generation circuit 10, and user data before partial rewriting and user data after partial rewriting. Difference data indicating the difference between and is generated. Then, the CPU 3 outputs a record addition command to the table holding circuit 11 and adds one record as partial rewrite information to the table (S4). Specifically, as shown in FIGS. 4 and 5, when the partial rewriting of user data occurs at the address “addr1”, the CPU 3 calculates the difference between the user data before the partial rewriting and the user data after the partial rewriting. The difference data “Δd1”, the address “addr1”, and the number of occurrences “1” from the time when the table is initialized are added to the table as one record. Thereafter, when the partial rewriting of the user data occurs at the address “addr2”, the CPU 3 determines the difference data “Δd2” indicating the difference between the user data before the partial rewriting and the user data after the partial rewriting, the address “addr2”, The number of occurrences “2” from the time when the table is initialized is added to the table as one record. Thereafter, the CPU 3 repeats the same processing every time partial rewriting of user data occurs.

  Next, the CPU 3 determines whether or not an error correction detection check request has been generated (S5), and determines whether or not the number of rewrites reaches a first predetermined number of times defined in advance (S6). . In this case, the CPU 3 counts a timer for checking error correction detection, for example, and determines whether or not the count value has reached a first predetermined value, thereby checking error correction detection. Determine whether a request has occurred. The first predetermined value is set depending on which of memory access throughput (efficient memory access) and error correction detection capability (user data redundancy) is prioritized. That is, if priority is given to memory access throughput over error correction detection capability, the frequency of error correction detection is set relatively low, and the first predetermined value is set to a relatively large value. . On the other hand, if priority is given to error correction detection capability over memory access throughput, the frequency of error correction detection is set relatively high, and the first predetermined value is set to a relatively small value. . The same applies to the first predetermined number of times, and if the memory access throughput is prioritized over the error correction detection capability, the first predetermined number of times is set to a relatively large value. On the other hand, if priority is given to error correction detection capability over memory access throughput, the first predetermined number of times is set to a relatively small value. When the first predetermined number of times is set to “1”, error correction detection is performed every time partial rewriting of user data occurs, and the error correction detection capability can be further enhanced. .

  When the CPU 3 determines that the count value has reached the first predetermined value for the timer for performing the error correction detection check and determines that the error correction detection check request has occurred (S5: YES), at that time It is determined whether or not the partial rewrite information is stored in the table (S7). When determining that the partial rewrite information is stored in the table (S7: YES), the CPU 3 reflects the difference data on the current user data (user data after the partial rewrite) (S8). That is, if the user data before partial rewriting is “A” and the user data after partial rewriting is “B”, the CPU 3 calculates “A−B” as difference data, and “B + (A−B) = A ”is calculated (difference data is written back).

  Then, the CPU 3 outputs an error correction detection command to the error correction detection circuit 9 and applies the parity data generated by the ECC circuit 6 before partial rewriting to the user data reflecting the difference data, to the user Data error correction is detected (S9). At this time, the CPU 3 initializes the first predetermined value after performing error correction detection of user data. Thereafter, the CPU 3 returns to step S3 and repeats step S3 and subsequent steps. The CPU 3 determines that an error correction detection check request has been generated (S5: YES), but if it determines that the partial rewrite information is not stored in the table (S7: NO), it detects error correction of user data. Without performing this, the process returns to step S3, and step S3 and subsequent steps are repeated.

  If the CPU 3 determines that the number of rewrites has reached the first predetermined number (S6: YES), the difference data is reflected in the current user data (user data after partial rewrite) (S8). ). Then, the CPU 3 outputs an error correction detection command to the error correction detection circuit 9 and applies the parity data generated by the ECC circuit 6 before partial rewriting to the user data reflecting the difference data, to the user Data error correction is detected (S9). At this time, the CPU 3 initializes the first predetermined number of times after performing error correction detection of user data. Thereafter, the CPU 3 returns to step S3 and repeats step S3 and subsequent steps.

  As described above, according to the first embodiment, each time partial rewriting of user data occurs in the error correction detection apparatus 2, the difference data by the partial rewriting corresponds to the address where the partial rewriting occurs. And store it in a table. When error correction detection of user data is performed, the difference data is reflected on the user data after the partial rewrite, and the parity data before the partial rewrite is applied to the user data reflecting the difference data. Thus, error correction detection of the user data is performed. That is, the difference data indicating the difference from the user data at the time of calculating the ECC parity is held, and the difference data can be always reflected on the user data after the partial rewriting, so that the user data before the partial rewriting can be reflected. Can always be generated. As a result, it is not necessary to recalculate ECC parity at the time of partial rewriting of user data, so that memory access can be performed efficiently. In addition, since a period in which the ECC parity is invalid does not occur, it is possible to prevent performance degradation due to user data redundancy. As a result, the trade-off between efficient memory access and user data redundancy can be eliminated.

  Further, the user data error correction detection is performed on condition that a request for error correction detection of user data has occurred or the number of rewrites reaches the first predetermined number of times. Thereby, the frequency of performing error correction detection of user data can be adjusted by the request for error correction detection and the first predetermined number of times. In other words, if priority is given to the memory access throughput over the error correction detection capability, the error correction detection request and the first predetermined number of times may be set so that the frequency of error correction detection is relatively low. good. On the other hand, if priority is given to the error correction detection capability over the memory access throughput, the error correction detection request and the first predetermined number of times may be set so that the frequency of error correction detection is relatively high. good.

  In the above description, it is determined whether or not a request for error correction detection of user data has occurred and whether or not the number of rewrites reaches the first predetermined number. Only a determination as to whether a request for error correction detection has occurred may be made. That is, the request for error correction detection of user data may be prioritized over the number of times of rewriting reaching the first predetermined number. If comprised in this way, error correction detection of user data can be performed without depending on the frequency | count of rewriting.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. In addition, description is abbreviate | omitted about the same part as above-mentioned 1st Embodiment, and a different part is demonstrated. In the second embodiment, in addition to performing error correction detection of user data, ECC parity recalculation is performed.

  The CPU 3 determines that partial rewriting of user data has occurred (S3: YES), and adds one record to the table as partial rewriting information (S4), whether or not a request for recalculation of ECC parity has occurred. It is determined (S11), and it is determined whether or not the number of times of rewriting has reached a second predetermined number of times defined in advance (S12), and whether or not a check request for error correction detection has occurred is determined (S5). ). In this case, for example, the CPU 3 counts a timer for recalculating the ECC parity and determines whether or not the count value has reached a second predetermined value defined in advance, thereby recalculating the ECC parity. Determine whether a request has occurred. The second predetermined value is set according to the size of the table and the frequency at which partial rewriting of user data occurs. That is, if the table size is relatively small or the frequency of partial rewriting of user data is relatively high, the frequency of recalculating ECC parity is set to be relatively high. The predetermined value is set to a relatively small value. On the other hand, if the table size is relatively large or the frequency of partial rewriting of user data is relatively low, the frequency of recalculating ECC parity is set to be relatively low. The predetermined value is set to a relatively large value. The same applies to the second predetermined number of times, and if the table size is relatively small or the frequency of partial rewriting of user data is relatively high, the second predetermined number of times is relatively small. Set to a value. On the other hand, if the table size is relatively large or the frequency of partial rewriting of user data is relatively low, the second predetermined number of times is set to a relatively large value. When the second predetermined number of times is set to “1”, the ECC parity is recalculated every time partial rewriting of user data occurs. In this case as well, error correction detection capability Can be further enhanced.

  When the CPU 3 determines that the count value of the timer for recalculating the ECC parity has reached the second predetermined value and determines that a request for recalculation of the ECC parity has occurred (S11: YES), at that time In step S13, it is determined whether the partial rewrite information is stored in the table. If the CPU 3 determines that the partial rewrite information is stored in the table (S13: YES), it outputs an ECC parity calculation command to the ECC circuit 6, and re-creates the ECC parity for the user data that has undergone the partial rewrite. Calculate and regenerate parity data. Then, the CPU 3 gives the regenerated parity data to the user data that has undergone the partial rewrite (S14). At this time, the CPU 3 initializes the second predetermined value after recalculating the ECC parity. Thereafter, the CPU 3 returns to step S2, initializes the table shown in FIG. 2, and then repeats step S3 and subsequent steps. The CPU 3 determines that an ECC parity recalculation request has occurred (S11: YES), but determines that the partial rewrite information is not stored in the table (S13: NO), causes the ECC parity to be recalculated. Without returning to step S3, step S3 and subsequent steps are repeated.

  If the CPU 3 determines that the number of rewrites has reached the second predetermined number (S12: YES), the CPU 3 also outputs an ECC parity calculation command to the ECC circuit 6 to the user data in which the partial rewrite has occurred. On the other hand, the ECC parity is recalculated to regenerate the parity data. Then, the CPU 3 gives the regenerated parity data to the user data that has undergone the partial rewrite (S14). At this time, the CPU 3 initializes the second predetermined number of times after recalculating the ECC parity. Thereafter, the CPU 3 returns to step S2, initializes the table shown in FIG. 2, and then repeats step S3 and subsequent steps.

  As described above, according to the second embodiment, ECC data is recalculated for user data that has undergone at least partial rewriting among user data, parity data is regenerated, and the table is initialized. I made it. As a result, the trade-off between efficient memory access and user data redundancy can be eliminated, and a table having a finite storage area can be used efficiently.

  Further, the ECC parity is recalculated on the condition that a request for recalculation of the ECC parity occurs or the number of rewrites reaches the second predetermined number of times. Thereby, the frequency of performing ECC parity recalculation can be adjusted by the ECC parity recalculation request or the second predetermined number of times. That is, if the table size is relatively small or the frequency of partial rewriting of user data is relatively high, the ECC parity is set so that the frequency of recalculating the ECC parity is relatively high. The recalculation request and the second predetermined number of times may be set. On the other hand, if the table size is relatively large or the frequency of partial rewriting of user data is relatively low, the ECC parity is set so that the frequency of recalculating ECC parity is relatively low. The recalculation request and the second predetermined number of times may be set.

  In the above, the determination whether or not the ECC parity recalculation request has occurred and the determination whether or not the number of rewrites reaches the second predetermined number are performed. Only a determination as to whether a calculation request has occurred may be made. That is, the request for recalculation of the ECC parity may be given priority over the fact that the number of rewrites reaches the second predetermined number. With this configuration, the ECC parity can be recalculated without depending on the number of rewrites.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. In addition, description is abbreviate | omitted about the same part as above-mentioned 1st Embodiment, and a different part is demonstrated. The third embodiment is a combination of the first embodiment and the second embodiment.

  The CPU 3 determines that partial rewriting of user data has occurred (S3: YES), and adds one record to the table as partial rewriting information (S4), whether or not a request for recalculation of ECC parity has occurred. It is determined (S11), it is determined whether the number of rewrites reaches the second predetermined number (S12), it is determined whether a check request for error correction detection has occurred (S5), and the number of rewrites is It is determined whether or not the first predetermined number of times has been reached (S6).

  The CPU 3 determines that a request for recalculation of the ECC parity has occurred (S11: YES), and determines that the partial rewrite information is stored in the table at that time (S13: YES), or the rewrite count is the second. If it is determined that the predetermined number of times has been reached (S12: YES), an ECC parity calculation command is output to the ECC circuit 6, and the parity data is reproduced by recalculating the ECC parity for the user data that has undergone partial rewriting. Make it happen. Then, the CPU 3 gives the regenerated parity data to the user data that has undergone the partial rewrite (S14). Thereafter, the CPU 3 returns to step S2, initializes the table shown in FIG. 2, and then repeats step S3 and subsequent steps.

  The CPU 3 determines that a check request for error correction detection has occurred (S5: YES), and determines that the partial rewrite information is stored in the table at that time (S7: YES), or the number of rewrites is the first. If it is determined that the predetermined number of times 1 has been reached (S6: YES), the difference data is reflected on the current user data (user data after partial rewriting) (S8). Then, the CPU 3 outputs an error correction detection command to the error correction detection circuit 9 and applies the parity data generated by the ECC circuit 6 before partial rewriting to the user data reflecting the difference data, to the user Data error correction is detected (S9). Thereafter, the CPU 3 returns to step S3 and repeats step S3 and subsequent steps.

  As described above, according to the third embodiment, the same operational effects as those of the second embodiment described above can be obtained. That is, in addition to eliminating the trade-off between efficient memory access and user data redundancy, a table having a finite storage area can be used efficiently.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and can be modified or expanded as follows. A plurality of modified examples may be combined.
By providing the ECC circuit for calculating the ECC parity, the processing for calculating the ECC parity is not limited to the configuration that implements the hardware, but the program for calculating the ECC parity is incorporated into the control program executed by the CPU 3, Processing for calculating the ECC parity may be realized by software.
Not only the configuration in which the table is held in a part of the storage area of the RAM 5, a storage unit different from the RAM 5 may be provided, and the table may be held in the other storage unit.

  In the drawing, 2 is an error correction detection device, 5 is a nonvolatile RAM (nonvolatile random access memory), 6 is an ECC circuit (parity data generation means), 9 is an error correction detection circuit (error correction detection means), 10 Is a difference data generation circuit (difference data generation means), and 11 is a table holding circuit (table holding means).

Claims (6)

A non-volatile random access memory (5) each having a plurality of randomly accessible memory cells;
Parity data generating means (6) for calculating ECC parity for user data stored in the memory cell and generating parity data;
In an error correction detection device (2) comprising error correction detection means (9) for applying error correction to the user data by applying the parity data to the user data,
In response to the occurrence of partial rewriting of user data stored in the memory cell, difference data generating means for generating difference data indicating a difference between user data before the partial rewriting and user data after the partial rewriting ( 10) and
Table holding means (11) for holding a table capable of storing the difference data generated by the difference data generating means,
The error correction detection means stores the difference data resulting from the partial rewriting in the table in association with the address at which the partial rewriting occurs every time the user data is partially rewritten, thereby correcting the error of the user data. When performing the detection, the difference data is reflected on the user data after the partial rewriting, and the parity data generated by the parity data generating unit before the partial rewriting is applied to the user data reflecting the difference data. Is applied to perform error correction detection of the user data. In the error correction detection apparatus according to claim 1,
The error correction detection means is conditional on at least one of the occurrence of a request for error correction detection of the user data and the number of occurrences of partial rewriting of the user data reaching a first predetermined number of times. An error correction detection apparatus for performing error correction detection of user data. In the error correction detection apparatus according to claim 2,
The error correction detection means prioritizes occurrence of a request for error correction detection of the user data over that the number of occurrences of partial rewriting of the user data has reached a first predetermined number of times, and An error correction detection apparatus that performs error correction detection. In the error correction detection apparatus according to any one of claims 1 to 3,
The parity data generation means recalculates ECC parity for user data that has undergone at least partial rewriting of the user data, and regenerates parity data.
The table holding means initializes a table, and an error correction detection apparatus. In the error correction detection apparatus according to claim 4,
The parity data generation means is conditioned on at least one of the occurrence of a request for recalculation of the ECC parity and the occurrence of the number of partial rewrites of the user data reaching a second predetermined number of times. An error correction detection apparatus characterized by recalculating ECC parity and regenerating parity data for at least partial rewriting of user data among data. In the error correction detection apparatus according to claim 5,
The parity data generation means prioritizes the occurrence of the ECC parity recalculation request over the second predetermined number of occurrences of partial rewrite of the user data, An error correction detection apparatus characterized by recalculating ECC parity for user data having undergone at least partial rewriting to regenerate parity data.

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