JP4146045B2 - Electronic computer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention greatly reduces the overhead of checkpoint processing and rollback processing by the high reliability mechanism of the checkpoint / rollback method.RudenConcerning child computers.
[0002]
[Prior art]
In recent years, business processing has been digitized in various fields, and demands for computer reliability and fault tolerance are increasing day by day. And what is called a fault tolerant type computer exists as a computer which implement | achieves this fault tolerance.
[0003]
This fault-tolerant computer uses a multiplexing method that multiplexes hardware and compares the results of operations to improve reliability, and takes a stable state called a checkpoint periodically. Two methods, the checkpoint / rollback method, which obtains a correct operation result by returning the state of the computer to the above are well known.
[0004]
Among these, the multiplexing method is represented by Tandem NonStop Cyclone series, Stratus XA series, etc. described in “Books that understand the mechanism of non-stop computers” (edited by Sakaimachi FTC Research Committee, Industrial Research Committee: 1992). Thus, it is widely put to practical use in a highly reliable computer using a loosely coupled or tightly coupled multiprocessor.
[0005]
On the other hand, the checkpoint / rollback method is, for example, a memory state restoration device described in JP-A-9-6731, a cache controller, a fault-tolerant computer, and its data transfer method described in JP-A-5-6308. It is the construction method of the high reliability computer system shown.
[0006]
[Problems to be solved by the invention]
However, a fault-tolerant computer using a multiplexing method is expensive because a plurality of resources such as processors are necessary, and a fault-tolerant computer using a checkpoint / rollback method requires overhead for taking a checkpoint. There is a problem that it is difficult to obtain high performance as compared with the multiplexing method.
[0007]
  The present invention has been made in consideration of such circumstances, and greatly reduces the overhead of checkpoint processing and rollback processing by the high-reliability mechanism of the checkpoint / rollback method.RudenThe purpose is to provide a child computer.
[0008]
[Means for Solving the Problems]
  In order to achieve the above-described object,Electronic computerIsIn an electronic computer having a checkpoint / rollback type high reliability mechanism, a buffer to which the first and second memory cell groups constituting the same address space and the first and second memory cell groups are connected A first selecting means for selecting a memory cell group for reading data from the buffer from the first and second memory cell groups; and a memory cell group for writing data in the buffer as the first and second memory cells. A data storage element having a second selection means for selecting from among the memory cell groups, and during normal operation, the data of the first memory cell group is transferred only to the first memory cell group via the buffer. And data protection means for writing back the data of the second memory cell group only to the second memory cell group via the buffer, and at the time of checkpoint, the first memory cell Data replicating means for simultaneously writing the data of the group to the first memory cell group and the second memory cell group via the buffer, and at the time of rollback, the data of the second memory cell group via the buffer Data restoring means for simultaneously writing back to the second memory cell group and the first memory cell group;It is characterized by comprising.
[0009]
  According to another aspect of the present invention, there is provided an electronic computer having a checkpoint / rollback type high reliability mechanism, the first and second memory cell groups constituting the same address space, and the first memory cell at the input. A first buffer for storing data read from the first memory cell group, connected to the memory cell group and connected to the first and second memory cell groups at an output; A second buffer for storing data read from the second memory cell group, to which two memory cell groups are connected, and to which the first and second memory cell groups are connected; A first selecting means for selecting a memory cell group to which data of one buffer is written from the first and second memory cell groups; and a memory cell group to which data of the second buffer is written are said first and second memory cells. Second memory cell A data storage element having a second selection means for selecting from among the group; and during normal operation, only the first storage cell group receives data of the first storage cell group via the first buffer. Data protection means for writing back the data of the second memory cell group only to the second memory cell group via the second buffer, and at the time of checkpoint, the first memory cell group Data replicating means for simultaneously writing the data of the second memory cell group to the first memory cell group and the second memory cell group via the first buffer, and the data of the second memory cell group at the time of rollback Data restoring means for simultaneously writing back to the second memory cell group and the first memory cell group via two buffers.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
(First embodiment)
First, a first embodiment of the present invention will be described.
[0020]
FIG. 1 is a diagram showing a schematic configuration of a fault-tolerant computer of a checkpoint / rollback system according to the first embodiment of the present invention.
[0021]
As shown in FIG. 1, a system bus A is laid in the fault tolerant computer of the first embodiment, and a plurality of CPUs 1 and a memory controller 2 are connected to the system bus A. . A system memory 3 is connected to the memory controller 2.
[0022]
The CPU 1 constitutes a tightly coupled pair type multiprocessor (SMP). All the CPUs 1 are synchronized at checkpoints, and internal information is written in a predetermined area of the system memory 3. Further, the dirty area of the cache memory of the CPU 1 is written into the system memory 3 to create a stable system state (checkpoint acquisition state) in the system memory 3.
[0023]
When the checkpoint acquisition state is confirmed, a command for copying the primary area of the system memory 3 to the secondary area is sent to the memory controller 2, and when it is confirmed that the copying is completed, the normal operation state is restored.
[0024]
The memory controller 2 drives and controls the system memory 3 and executes reading of data from the system memory 3 and writing of data to the system memory 3 in accordance with instructions from the CPU 1. The memory controller 2 also executes and controls protection of data stored in the system memory 3, such as a refresh operation in a DRAM.
[0025]
The system memory 3 is a memory device that is shared by a plurality of CPUs 1 and serves as a main memory of the fault-tolerant computer, and stores programs and processing data that are controlled by the CPU 1. In the fault tolerant computer, the system memory 3 is constituted by a DRAM.
[0026]
According to the present invention, the data storage element (in this case, the DRAM) constituting the system memory 3 is provided with a plurality of storage cell groups constituting the same address space in the data storage element. It is possible to have two storage areas of the primary memory 3a and the secondary memory 3b, and as a result, checkpoint processing and rollback processing can be performed without using the system bus A which is a shared resource. The feature is that these overheads are greatly reduced.
[0027]
Therefore, in this fault-tolerant computer, the DRAM constituting the system memory 3 has a function of designating a memory cell (primary or secondary) to be read at the time of refresh, and write-back by refresh is performed only on the read source cell. Or a function for designating whether to perform both of the cells.
[0028]
FIG. 2 schematically shows two memory cells and sense amplifiers of the DRAM constituting the system memory 3 and their operations. Although not shown in FIG. 2, designation of a memory cell to be read into the sense amplifier 30 at the time of refresh is performed by an external pin of the DRAM. This external pin has a function equivalent to that of a DRAM row address selection pin. For convenience, this pin will be referred to as a “sense amplifier / lead / selector pin”. In addition, it is assumed that a separate pin is provided for designating whether the write-back by refresh is performed only on the read cell side or on both (primary and secondary) cells. For convenience, this pin will be referred to as a “sense amplifier / write / selector pin”. Here, for the sake of simplicity, it is assumed that “sense amplifier / write / selector / pin” is assigned to each memory cell by one bit.
[0029]
In this DRAM, two DRAM cells (10, 20) are connected to one sense amplifier 30, and data is normally read / written to / from the memory cell 10 on the primary side. During normal reading, the “sense amplifier read selector pin” selects the primary cell 10 side. In normal writing, the “sense amplifier / write / selector pin” is set to write only to the primary side.
[0030]
First, the normal operation of this DRAM will be described.
[0031]
This DRAM is different from a normal DRAM in the data update operation during refresh. FIG. 3 shows the refresh operation on the primary side, and FIG. 4 shows the refresh operation on the secondary side.
[0032]
If the refresh cycle comes before the checkpoint, the DRAM refreshes in the same way as a standard DRAM. That is, the refresh on the primary side 10 and the refresh on the secondary side 20 are performed independently, and the write-back is performed only on the read side cell.
[0033]
When the primary cell 10 shown in FIG. 3 is refreshed, the data on the primary cell 10 side is read into the sense amplifier 30 by the “sense amplifier read selector pin”, and the “sense amplifier write selector pin” is sensed. Each is set so that the contents of the amplifier 30 are written only to the primary side.
[0034]
On the other hand, when the secondary side cell 20 shown in FIG. 4 is refreshed, the “sense amplifier read selector pin” reads the secondary cell 20 side, and the “sense amplifier write selector pin” enters the secondary side cell 20. Each is set to write only.
[0035]
The row address is generated inside the DRAM in the same way as the normal CAS before RAS refresh, and the same value is supplied to the primary side row address (PRn) and the secondary side row address (SRn).
[0036]
Next, the checkpoint operation of this DRAM will be described.
[0037]
FIG. 5 shows the refresh operation of the DRAM at the checkpoint. In this DRAM, at the time of a check point, data on the primary side 10 is read to the sense amplifier 30 and a refresh operation is performed to write data on both the primary side 10 and the secondary side 20. Thereby, since the checkpoint operation can be concealed in the refresh operation, the overhead of the checkpoint process can be reduced.
[0038]
In the refresh at the checkpoint where the contents of the primary side cell 10 shown in FIG. 5 are copied to the secondary side cell, the “sense amplifier read selector pin” indicates the primary cell 10 side as “sense amplifier write selector”. “Pin” is set to write to both the primary side cell 10 and the secondary side cell 20. Further, the row address is generated inside the DRAM as in the normal CAS before RAS refresh, and the same value is supplied to the primary side row address (PRn) and the secondary side row address (SRn).
[0039]
Next, the rollback operation of this DRAM will be described.
[0040]
FIG. 6 shows the refresh operation of the DRAM during rollback. In this case, data is read from the secondary side cell 20 to the sense amplifier 30 and a refresh operation is performed to write back the data to both the secondary side 20 and the primary side 10. This action allows the memory to quickly return to the previous checkpoint state.
[0041]
In the refresh of the rollback process for copying the contents of the secondary side cell 20 shown in FIG. 6 to the primary side cell 10, the “sense amplifier read selector pin” moves the secondary side cell 20 side to “sense amplifier write write”. The “selector pin” is set so as to write to both the primary side cell 10 and the secondary side cell 20. Further, the row address is generated inside the DRAM as in the normal CAS before RAS refresh, and the same value is supplied to the primary side row address (PRn) and the secondary side row address (SRn).
[0042]
The operation in each of the above refresh operations is shown in FIG. In FIG. 7, “sense amplifier write selector pin” is described in the form of “(selection of primary side cell, selection of secondary side cell)”, and is active when “1” and inactive when “0”. Active.
[0043]
FIG. 8 shows a refresh timing of a general computer, and FIG. 9 shows a refresh timing of a fold tolerant computer to which the DRAM of the first embodiment is applied. In these figures, the refresh timing is simply indicated by vertical lines.
[0044]
In a general computer, each row address must be accessed at a frequency of once or more in 64 ms according to the regulations of DRAM. For this reason, the memory controller normally issues a refresh interrupt with a frequency of about once every 15 us and refreshes the DRAM at regular intervals (FIG. 8).
[0045]
On the other hand, a checkpoint rollback computer takes checkpoints at a rate of about once every 10 ms. That is, since the checkpoint interval and the refresh interval are substantially equal, in the DRAM according to the first embodiment, the refresh is basically performed during the checkpoint process as shown in FIG. 9A. As a result, an interrupt due to refresh does not occur during normal operation, and memory access can be executed at high speed.
[0046]
However, when the checkpoint interval becomes longer than the specified refresh interval as shown in FIG. 9B, refresh is executed with a refresh interrupt as in a general computer storage device. For this reason, for example, when 48 ms, which is 3/4 of the prescribed refresh cycle 64 ms, is exceeded, the refresh operation is performed with a refresh interrupt at a rate four times the normal refresh cycle 15 us, that is, once every 3.75 us. Guaranteed DRAM data. If the checkpoint is taken between 48 ms and less than 64 ms, checkpoint processing is entered. On the other hand, if the checkpoint is not taken within 64 ms, the refresh interrupt 48 ms counter is reset to check whether the next checkpoint interrupt exceeds the refresh interrupt.
[0047]
Here, the selection procedure of the refresh method of the DRAM will be described with reference to the flowchart of FIG.
[0048]
First, it is checked whether rollback is executed (step A1). If rollback is executed (YES in step A1), a refresh method for copying the contents of the secondary cell to the primary cell is selected (step A2). If rollback is not executed (NO in step A1), then it is checked whether or not checkpoints are collected (step A3). If checkpoints are collected (YES in step A3), the contents of the primary cell are changed to secondary. A refresh method to be copied to the cell is selected (step A4).
[0049]
If the check point is not collected (NO in step A3), it is checked whether the refresh time is within the prescribed refresh time (step A5). If not within the refresh prescribed time (NO in step A5), the refresh is completed. Whether it is present (step A6). If the refresh has already been completed (YES in step A6), the refresh timer is reset to “0” (step A7). On the other hand, if the refresh has not been completed (NO in step A6), a normal refresh is performed. A method is selected (step A8).
[0050]
As described above, in this fault tolerant computer, the DRAM constituting the system memory 3 constitutes two storage areas of the primary memory 3a and the secondary memory 3b representing the same address space. It is possible to perform checkpoint processing and rollback processing without using, and to significantly reduce these overheads.
[0051]
(Second Embodiment)
Next, a second embodiment of the present invention will be described.
[0052]
The fault tolerant computer according to the second embodiment is characterized by an error detection / correction circuit (single error correction double error detection ECC) and an error in the DRAM of the fault tolerant computer of the first embodiment. A detection / correction enable register and an error notification unit (error flag, error address register) are added.
[0053]
Here, the error detection / correction circuit is a single error correction double error detection ECC (SEC-DSD ECC). The column address (Column Address) of the DRAM is 1 Gbit (= 20³⁰√20 for a bit) DRAM³⁰= 2¹⁵Since there are about bits, 64 (= 2⁶) Check bits can be created more efficiently than a memory bus of about a bit. In fact, 2 in theory⁶Check bits for 8 bits of data require 8 bits, which occupies 12% of the total data.¹⁵The check bit for the bit data is 17 bits, which is only 0.5% of the total data (see “Guide to Error Coding Technology”, Chapter 4 Application to Computers, Supervised by Hideki Imai, Japan Industrial Technology Center).
[0054]
The error detection / correction enable register is composed of, for example, 2 bits. When bit 0 is set to “1”, error detection by ECC is performed, and when “0” is set, error detection is not performed. When bit 1 is set to “1”, single error correction by ECC is performed, and when it is set to “0”, error correction is not performed.
[0055]
The error notification unit holds whether or not an error has occurred, whether or not the error can be corrected, and the row address (Row Address) where the error has occurred.
[0056]
In the DRAM of the second embodiment, an ECC check bit is generated and written to the memory cell when data is written back from the sense amplifier to the memory cell, and an ECC check is performed when data is read from the memory cell to the sense amplifier. At this time, error detection and correction are performed according to the error detection / correction enable register. That is, if error detection is enabled, the error flag is set to “1” when an error occurs, and the error address is stored in the error address register. If error detection is disabled, the error flag and error are also detected when an error occurs. Do not update the address register. Note that if the double bit error detection register is set, as is done in the ECC of a normal high reliability computer, the error flag and error address register may not be updated during single bit error correction. Good.
[0057]
When a single error is detected in the refresh operation of the checkpoint process or rollback process, the error is corrected and then written to both memory cells. If a double error is detected, data is written back only to the read cell, and data is not written back to the opposite cell. The error detection / correction enable register may not be provided.
[0058]
FIG. 11 shows a configuration of a DRAM having an error check bit. Although omitted in FIG. 11, when the data 100 and the check bit 110 of the row address (PRn) are read out to the sense amplifier 30, an error check is performed through the ECC check circuit. If a single bit error has occurred, the bit is inverted and written to the sense amplifier 30. When writing from the sense amplifier to the memory cell at the row address (PRn) on the primary 10 side and the memory cell at the row address (SRn) on the secondary 20 side, the check bit 110 is generated from the data portion 100 of the sense amplifier 30 and written. That is, if no error information is left, the check bit 110 is not necessary for the sense amplifier 30. The reason why the check bit 110 is generated from the data part 100 is that it is necessary to regenerate the check bit 110 based on the new data 100 when writing to the memory from the outside occurs.
[0059]
(Third embodiment)
Next, a third embodiment of the present invention will be described.
[0060]
The feature of the fault tolerant computer of the third embodiment is that an update bit is provided for each row address of the DRAM of the fault tolerant computer of the first embodiment described above. Only the standing DRAM address is refreshed to speed up the checkpoint process.
[0061]
FIG. 12 shows a configuration of a DRAM having an update bit.
[0062]
As is well known, in a computer memory, memory addresses accessed in a short time have locality of reference concentrated in a small area. Therefore, when the addresses of the DRAM are mapped to the real addresses so that the row addresses are continuous, the row addresses referred to in a short time are concentrated in a small area. Therefore, if an update bit (or an update management table: Modified Block Table) 120 is provided and only the necessary part is updated by the above-described refresh operation, the checkpoint process can be performed in a very short time.
[0063]
(Fourth embodiment)
Next explained is the fourth embodiment of the invention.
[0064]
The feature of the fault-tolerant computer of the fourth embodiment is that the update bits of the DRAM of the fault-tolerant computer of the third embodiment are provided outside the DRAM. Here, the outside of the DRAM may be inside the memory controller or may be independent of the memory controller. Further, since the update bit is set when writing to the memory occurs, it can be placed outside the memory element. In this case, since the degree of freedom in selecting the management method is increased, for example, when applied to the memory state restoration device described in Japanese Patent Laid-Open No. 9-6731, for example, a highly reliable computer can be realized with a small overhead. .
[0065]
(Fifth embodiment)
Next explained is the fifth embodiment of the invention.
[0066]
The feature of the fault tolerant computer of the fifth embodiment is that a refresh completion flag is provided at each row address of the DRAM of the fault tolerant computer of the second embodiment. FIG. 13 shows the configuration of a DRAM having a refresh completion flag.
[0067]
If there is a normal refresh operation, refresh by checkpoint processing or rollback processing, or normal read / write access, this refresh completion flag 130 is set. When all the refresh completion flags are set, the refresh completion flag 130 is reset.
[0068]
With respect to the row address where the refresh completion flag 130 is set, the refresh efficiency can be increased by not performing CAS Before RAS refresh.
[0069]
(Sixth embodiment)
Next, a sixth embodiment of the invention will be described.
[0070]
The feature of the fault-tolerant computer of the sixth embodiment is that two sets of sense amplifiers for the DRAM of the fault-tolerant computer of the third embodiment are provided.
[0071]
FIG. 14 shows the configuration of a DRAM when two sets of sense amplifiers are provided.
[0072]
The input of one set of sense amplifiers 31 a is fixed to the primary cell 10, and the input of the other set of sense amplifiers 31 b is fixed to the secondary cell 20. Therefore, the “sense amplifier read selector pin” described in the first embodiment is not necessary. Instead, there is provided means for designating a sense amplifier that holds data to be written back to the memory cell, as will be described later.
[0073]
In the normal read / write access to the primary memory 10, the primary side sense amplifier 31a is used, while in the normal read / write access to the secondary memory 20, the secondary side sense amplifier 31b is used.
[0074]
First, the normal operation of this DRAM will be described.
[0075]
FIG. 14 shows a normal DRAM refresh operation. In normal refresh, the data in the primary memory 10 at the row address (PRn) is read to the primary sense amplifier 31a and written back to the primary memory 10. At the same time, the data in the secondary memory 20 at the corresponding row address (SRn) is read out to the secondary sense amplifier 31b and written back to the secondary memory 20. For simplicity, a “normal refresh pin” indicating that the default sense amplifier is used will be provided.
[0076]
When the “normal refresh pin” is active, the data of the default sense amplifier is written into the memory cell group in which the “sense amplifier write selector pin” is active. As for the default sense amplifier, the primary memory 10 is a primary-side sense amplifier 31a, and the secondary memory 20 is a secondary-side sense amplifier 31b. When the “normal refresh pin” is not active, a means for determining which sense amplifier value is written back to the memory cell is required. In this case, since there are only two primary and secondary memory cell groups, one bit is sufficient. This will be referred to as a “write-back sense amplifier selector pin”.
[0077]
If the “normal refresh pin” is not active and the “write-back sense amplifier selector pin” is “primary”, the contents of the primary sense amplifier 31a are changed to “sense amplifier write selector pin”. ”Is written in the memory cell in which“ is active ”.
[0078]
In this DRAM configuration, since there are only two memory cells and the setting of the “sense amplifier / write selector / pin” is obvious, the “sense amplifier / write / selector / pin” need not be provided.
[0079]
Next, the checkpoint operation of this DRAM will be described.
[0080]
FIG. 15 shows the refresh operation of the DRAM at the time of checkpoint. At the time of checkpoint processing, after performing cache flush and writing and saving information such as processor registers in the primary memory, the data of the row address (PRn) of the primary memory 10 in which the update bit 130 is set is transferred to the primary sense amplifier 31a. Read to. At the same time, the data in the secondary memory 20 at the corresponding row address (SRn) is read out to the secondary sense amplifier 31b. At the time of writing, the contents of the primary sense amplifier 31 a are written not only to the cell group of the row address (PRn) of the primary memory 10 but also to the cell group of the corresponding row address (SRn) of the secondary memory 20. The contents of the secondary sense amplifier 31b are discarded. For this purpose, the “normal refresh pin” is made inactive, and the “write back sense amplifier selector pin” is made “primary”. Thereby, the data of the updated row address (PRn) of the primary memory 10 is copied to the memory cell of the corresponding row address (SRn) of the secondary memory 20.
[0081]
Next, the rollback operation of this DRAM will be described.
[0082]
When a failure occurs, the data of the row address (PRn) of the primary memory 10 in which the update bit 130 is set is read to the primary sense amplifier 31a. At the same time, the data in the secondary memory 20 at the corresponding row address (SRn) is read into the secondary sense amplifier 32. At the time of writing, the contents of the secondary sense amplifier 31b are written not only to the cell group of the row address (SRn) of the secondary memory 20, but also to the cell group of the corresponding row address (PRn) of the primary memory 10. The contents of the primary sense amplifier 31 are discarded. For this purpose, the “normal refresh pin” is made inactive, and the “write back sense amplifier selector pin” is made “secondary”. Thereby, the data of the updated row address (SRn) of the secondary memory 10 is copied to the memory cell of the corresponding row address (PRn) of the primary memory 10.
[0083]
When a failure occurs, the refresh bit 130 may be ignored and a refresh operation may be performed on all row addresses to copy the contents of the secondary memory to the primary memory.
[0084]
The operation in each of the above refresh operations is shown in FIG. In FIG. 16, “sense amplifier write selector pin” is described in the form of “(primary side cell selection, secondary side cell selection)”. When “1”, it is active, and when it is “0” Inactive.
[0085]
In the fault-tolerant computers of the first to sixth embodiments described above, the example in which the checkpoint process and the rollback process are performed using the refresh of the DRAM is shown, but the data storage element is not limited to the DRAM. For example, an SRAM may be used instead of a DRAM, or a nonvolatile memory such as a DRAM may be used on the primary side and a flash memory on the secondary side.
[0086]
In particular, when a non-volatile element is used on the secondary side, it is effective even if used as a means for realizing a resume function by being used not only in a highly reliable computer but also in a general computer. Further, it is possible to achieve high reliability by using the disk cache instead of the main memory.
[0087]
Further, when the processor and the memory are mounted on the same LSI chip by the system on chip technology, the present invention can be applied to the memory control circuit.
[0088]
【The invention's effect】
As described in detail above, according to the present invention, by providing a plurality of sets of storage cell groups that constitute the same address space, a primary storage area and a secondary storage area are provided in a single data storage element. Since it is possible to have two storage areas, checkpoint processing is executed by copying the data of the memory cell group that is used as the primary to the memory cell group that is used as the secondary, without using the external bus that is a shared resource. In addition, since the rollback process can be executed by copying the data of the memory cell group used as the secondary to the memory cell group used as the primary, the overhead of the checkpoint process and the rollback process can be greatly reduced. Make it possible.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic configuration of a fault-tolerant computer of a checkpoint / rollback method according to a first embodiment of the invention.
FIG. 2 is a diagram schematically showing two memory cells and a sense amplifier of a DRAM constituting the system memory 3 of the first embodiment and their operations.
FIG. 3 is a view showing a refresh operation on the primary side of the DRAM of the first embodiment;
FIG. 4 is a diagram showing a refresh operation on the secondary side of the DRAM of the first embodiment;
FIG. 5 is a diagram showing a refresh operation of the DRAM at a check point in the first embodiment.
6 is a diagram showing a refresh operation of the DRAM at the time of rollback in the first embodiment. FIG.
FIG. 7 is a view showing operations in each refresh operation of the first embodiment;
FIG. 8 is a diagram showing refresh timing of a general computer.
FIG. 9 is a diagram showing refresh timing of the fold tolerant computer to which the DRAM of the first embodiment is applied;
FIG. 10 is an exemplary flowchart for explaining a DRAM refresh method selection procedure according to the first embodiment;
FIG. 11 is a diagram showing a configuration of a DRAM having an error check bit according to the second embodiment.
FIG. 12 is a diagram showing a configuration of a DRAM having an update bit according to the third embodiment.
FIG. 13 is a diagram showing a configuration of a DRAM having a refresh completion flag according to the fifth embodiment.
FIG. 14 is a diagram showing a DRAM configuration and a normal DRAM refresh operation when two sets of sense amplifiers of the sixth embodiment are provided;
FIG. 15 is a view showing a refresh operation of a DRAM at a check point in the sixth embodiment.
FIG. 16 is a diagram showing operations in each refresh operation of the sixth embodiment.
[Explanation of symbols]
1 ... CPU
2 ... Memory controller
3. System memory (DRAM)
10 ... Primary cell
20 ... Secondary cell
30 ... Sense amplifier
31a ... Primary sense amplifier
31b ... Secondary sense amplifier
100 ... Data body
110: Check bit
120: Update bit
130: Refresh completion flag

Claims (20)

In an electronic computer with a highly reliable checkpoint / rollback method,
First and second memory cell groups constituting the same address space;
A buffer to which the first and second memory cell groups are connected;
First selection means for selecting a memory cell group for reading data from the buffer from the first and second memory cell groups;
Second selection means for selecting a memory cell group to which data of the buffer is written from the first and second memory cell groups;
A data storage element comprising:
During normal operation, the data in the first memory cell group is written back to only the first memory cell group through the buffer, and the data in the second memory cell group is written in the second memory through the buffer. Data protection means for writing back only to the memory cell group,
Data duplicating means for simultaneously writing back the data of the first memory cell group to the first memory cell group and the second memory cell group via the buffer at the time of checkpoint;
Data restoring means for simultaneously writing back the data of the second memory cell group to the second memory cell group and the first memory cell group via the buffer at the time of rollback;
An electronic computer characterized by comprising:   2. The computer according to claim 1, wherein the buffer of the data storage element is a sense amplifier for writing back data of the first or second storage cell group for data protection.   2. The first storage cell group of the data storage element is a normal primary cell, and the second storage cell group of the data storage element is a backup secondary cell. Electronic calculator.   The data storage element has means for simultaneously writing back one of the data in the first and second memory cell groups to both the first and second memory cell groups via the buffer at the time of refresh. The electronic computer according to claim 1, wherein the electronic computer is a DRAM. 2. The computer according to claim 1, wherein at least one of the first memory cell group and the second memory cell group of the data storage element is a non-volatile element.   The data storage element includes a redundant bit for error checking in the first and second memory cell groups, and means for performing error detection or error correction using the redundant bit. The electronic computer according to claim 1.   The electronic computer according to claim 6, wherein the data storage element includes means for storing error information.   7. The computer according to claim 6, wherein the data storage element comprises means for designating whether or not to perform error detection or error correction.   2. The electronic computer according to claim 1, wherein said data storage element is provided with means for indicating a reference history of each storage cell corresponding to at least one of said first and second storage cell groups.   10. The electronic computer according to claim 9, wherein the data duplicating unit only writes back data having a reference history. In an electronic computer with a highly reliable checkpoint / rollback method,
First and second memory cell groups constituting the same address space;
A first buffer for storing data read from the first memory cell group, wherein the first memory cell group is connected to an input and the first and second memory cell groups are connected to an output When,
A second buffer for storing data read from the second memory cell group, wherein the second memory cell group is connected to an input and the first and second memory cell groups are connected to an output When,
First selection means for selecting a storage cell group to which data of the first buffer is written from the first and second storage cell groups;
Second selection means for selecting a storage cell group to which data of the second buffer is written from the first and second storage cell groups;
A data storage element comprising:
During normal operation, the data of the first memory cell group is written back to the first memory cell group only via the first buffer, and the data of the second memory cell group is written to the second buffer. Data protection means for writing back only to the second memory cell group via
Data duplicating means for simultaneously writing data of the first memory cell group to the first memory cell group and the second memory cell group via the first buffer at the time of a checkpoint;
Data restoring means for simultaneously writing back the data of the second memory cell group to the second memory cell group and the first memory cell group via the second buffer at the time of rollback;
An electronic computer characterized by comprising:   The first buffer of the data storage element is a sense amplifier for writing back data of the first storage cell group for data protection, and the second buffer of the data storage element is data protection 12. The electronic computer according to claim 11, wherein the electronic computer is a sense amplifier for writing back data of the second memory cell group.   The first storage cell group of the data storage element is a normal primary cell, and the second storage cell group of the data storage element is a backup secondary cell. 11. The electronic computer according to 11.   At the time of refresh, the data storage element transfers either one of the data in the first and second memory cell groups via the first or second buffer to both the first and second memory cell groups. 12. The electronic computer according to claim 11, wherein the electronic computer is a DRAM provided with means for simultaneously writing back to the computer.   12. The electronic computer according to claim 11, wherein at least one of the first and second memory cell groups of the data storage element is a non-volatile element.   The data storage element includes a redundant bit for error checking in the first and second memory cell groups, and means for performing error detection or error correction using the redundant bit. The electronic computer according to claim 11.   17. The computer according to claim 16, wherein the data storage element includes means for storing error information.   17. The computer according to claim 16, wherein the data storage element comprises means for designating whether or not to perform error detection or error correction.   12. The electronic computer according to claim 11, wherein the data storage element is provided with means for indicating a reference history of each storage cell corresponding to at least one of the first and second storage cell groups.   20. The electronic computer according to claim 19, wherein the data duplicating unit only writes back data having a reference history.

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