CN100464290C - Caching management system - Google Patents
Caching management system Download PDFInfo
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- CN100464290C CN100464290C CNB200710121573XA CN200710121573A CN100464290C CN 100464290 C CN100464290 C CN 100464290C CN B200710121573X A CNB200710121573X A CN B200710121573XA CN 200710121573 A CN200710121573 A CN 200710121573A CN 100464290 C CN100464290 C CN 100464290C
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Abstract
The present invention provides a cache management system which is used in an internet storage control system. The internet storage control system comprises a host processor which faces the user host and a disk controller which faces the disk; the cache management system comprises a cache, a first cache controller and a second cache controller, wherein, the first cache controller has one or more than one interface which is connected with the host processor as well as one or more than one interface which is connected with the disk controller, the two interfaces are used to process the cache accessing requests of one or more than one host processor as well as one or more than one disk controller; the second cache controller has one or more than one interface which is connected with the host processor as well as one or more than one interface which is connected with the disk controller, the two interfaces are used to process the cache accessing request of one or more than one host processor as well as one or more than one disk controller. The present invention can improve the reliability and the usability of the cache management system.
Description
Technical field
The present invention relates to the network data memory technology, relate in particular to a kind of buffer memory (Cache) management system.
Background technology
In communication system, when between two parts owing to frequency of operation differs too when greatly system performance being affected, usually the Cache element of frequency of operation between these two parts frequency of operation can added between these two parts, improve two work efficiencies between the parts, optimization system performance by certain Cache algorithm.In storage control system, the interpolation of Cache also has very big contribution to the raising of system performance.Fig. 1 shows the Cache management system structural representation in the network storage control system.Referring to Fig. 1, this system mainly comprises: host-processor, buffer memory, cache controller and disk storage part, wherein, the disk storage part is made up of Magnetic Disk Controller and disk.Because the frequency of operation of disk is lower, and the frequency of operation of host-processor is higher, therefore, in order to improve the read-write efficiency of host-processor, Fig. 1 has added cache controller and the Cache of frequency of operation between the two frequency of operation between host-processor and disk storage part.
As seen from Figure 1, a cache controller is only arranged in the existing C ache management system, this will make system have the single fault point, that is to say, when this unique cache controller breaks down can not work the time, whole C ache management system can't normally be moved, thereby cause the reduction of Cache management system reliability.And, in existing C ache management system, a cache controller is only served a host-processor and a Magnetic Disk Controller, can only handle the Cache request of access of a host-processor and a Magnetic Disk Controller, when having a plurality of host-processors or a plurality of Magnetic Disk Controller in the system, the Cache request of access of a plurality of host-processors or a plurality of Magnetic Disk Controllers can't obtain handling, thereby reduce the availability of Cache management system.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of cache management system, to improve the reliabilty and availability of Cache management system.
For achieving the above object, technical scheme provided by the invention is as follows:
A kind of cache management system, be used for network storage control system, described network storage control system comprises the host-processor of user oriented main frame and towards the Magnetic Disk Controller of disk, this cache management system comprises: buffer memory, first cache controller and second cache controller, wherein
First cache controller, have one or more interfaces that link to each other with host-processor and one or more interfaces that links to each other with Magnetic Disk Controller, be used to handle the cache access request of described one or more host-processors and one or more Magnetic Disk Controllers;
Second cache controller, have one or more interfaces that link to each other with host-processor and one or more interfaces that links to each other with Magnetic Disk Controller, be used to handle the cache access request of described one or more host-processors and one or more Magnetic Disk Controllers.
Connect by backup path between described first cache controller and second cache controller, among described first cache controller and second cache controller, have one lost efficacy and another just often, take over the work of the cache controller of inefficacy by normal cache controller.
Connect by backup path between described first cache controller and second cache controller, when described first cache controller and second cache controller all just often,
By the cache access request of first cache controller processing All hosts processor and all Magnetic Disk Controllers, second cache controller is not handled;
Perhaps, by the cache access request of second cache controller processing All hosts processor and all Magnetic Disk Controllers, first cache controller is not handled;
Perhaps, first cache controller and second cache controller are shared the cache access request of All hosts processor and disk processor according to load balancing mode.
Connect by backup path between described first cache controller and second cache controller, and carry out data sync by this backup path.
Described first cache controller is connected with described one or more host-processors and described one or more Magnetic Disk Controllers by high-speed channel; Perhaps, described first cache controller is connected with described one or more host-processors and described one or more Magnetic Disk Controllers by bus mode;
Described second cache controller is connected with described one or more host-processors and described one or more Magnetic Disk Controllers by high-speed channel; Perhaps, described second cache controller is connected with described one or more host-processors and described one or more Magnetic Disk Controllers by bus mode.
Described first cache controller is connected with buffer memory respectively with second cache controller, and described one or more host-processors and described one or more Magnetic Disk Controllers are by described first cache controller or the second cache controller access cache.
Perhaps, described one or more host-processors and described one or more Magnetic Disk Controllers are connected with buffer memory respectively, described one or more host-processors and the direct access cache of described one or more Magnetic Disk Controllers.
Described cache controller comprises: be used to manage the memory management unit of buffer memory and the discrepancy crosspoint that is connected with memory management unit,
Described discrepancy crosspoint has the interface that one or more link to each other with host-processor, and has the interface that one or more link to each other with Magnetic Disk Controller.
Described discrepancy crosspoint also has the interface that links to each other with buffer memory.
Described memory management unit is connected with another cache controller by backup path, and realizes data sync by this backup path and described another cache controller.
This shows, the present invention is by being provided with the mode of two cache controllers, during cache controller inefficacy therein, take over business by another normal cache controller, the normal operation of assurance system, thereby avoided the generation of single fault point phenomenon, improved the reliability of Cache management system.And, by a plurality of interfaces that link to each other with host-processor and a plurality of interface that links to each other with Magnetic Disk Controller are set on cache controller, can make cache controller handle the Cache request of access of a plurality of host-processors and a plurality of Magnetic Disk Controllers, thereby improve the availability of Cache management system.
Description of drawings
Fig. 1 is a Cache management system structural representation of the prior art.
Fig. 2 is the Cache management system structural representation one in the embodiment of the invention.
Fig. 3 is the Cache management system structural representation two in the embodiment of the invention.
Fig. 4 is the Cache management system structural representation three in the embodiment of the invention.
Fig. 5 is the Cache management system structural representation four in the embodiment of the invention.
Fig. 6 is the Cache management system structural representation five in the embodiment of the invention.
Fig. 7 is the Cache management system structural representation six in the embodiment of the invention.
Fig. 8 is the cache controller structural representation in the embodiment of the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, the embodiment that develops simultaneously with reference to the accompanying drawings is described in further detail the present invention.
The defective that has single fault point at existing C ache management system, the invention provides a solution, its basic thought is: two cache controllers are set in the Cache management system: first cache controller and second cache controller, wherein, first cache controller is connected with Magnetic Disk Controller with host-processor respectively, and second cache controller also is connected with Magnetic Disk Controller with host-processor respectively.And, a backup path is arranged between first cache controller and second cache controller, realize data sync by this backup path between first cache controller and second cache controller, mutually telepathy hop-information and need backed up data information etc.
When two cache controllers all just often, can select to handle the Cache request of access of All hosts processor and Magnetic Disk Controller by first cache controller, second cache controller is not handled; Perhaps, by the Cache request of access of second cache controller processing All hosts processor and Magnetic Disk Controller, first cache controller is not handled; Perhaps, share the Cache request of access of All hosts processor and disk processor according to load balancing mode by first cache controller and second cache controller.Another cache controller just often just is responsible for handling the Cache request of access of All hosts processor and Magnetic Disk Controller by normal cache controller when wherein there being a cache controller to lose efficacy.
As seen, by the mode of two cache controllers is set, in the time of can a cache controller lost efficacy therein, take over business by another normal cache controller, the normal operation of assurance system, thus the generation of single fault point phenomenon avoided, improved the reliability of Cache management system.
Only connect the situation of a host-processor and a Magnetic Disk Controller at a cache controller, Fig. 2 shows a kind of Cache management system structural representation that adopts two cache controllers.Referring to shown in Figure 2, first cache controller is connected with Magnetic Disk Controller with host-processor respectively, second cache controller also is connected with disk processor with host-processor respectively, and, first, second cache controller is connected with Cache respectively, and host-processor and Magnetic Disk Controller are by first cache controller or second cache controller visit Cache.Such as, Magnetic Disk Controller writes Cache by first cache controller with the data that host-processor need read from disk; Host-processor reads data in buffer by first cache controller from Cache.
Only connect the situation of a host-processor and a Magnetic Disk Controller at a cache controller, Fig. 3 shows the another kind of Cache management system structural representation that adopts two cache controllers.Referring to shown in Figure 3, first cache controller is connected with Magnetic Disk Controller with host-processor respectively, second cache controller also is connected with disk processor with host-processor respectively, and, host-processor is connected with Cache respectively with Magnetic Disk Controller, the master is reading of data from Cache directly, and Magnetic Disk Controller also can directly write Cache with the data in the disk.
Wherein, first cache controller both can be connected with Magnetic Disk Controller with host-processor by independent high-speed channel mode, also can be connected with Magnetic Disk Controller with host-processor by bus mode.Second cache controller can be set up by high-speed channel mode or bus mode with being connected equally of host-processor and Magnetic Disk Controller.
In addition, in order further to solve in the prior art, a cache controller can only connect a host-processor and a disk control e management system structural representation.Referring to shown in Figure 4, all there is one to connect at a high speed between each host-processor and each cache controller, also there is one to connect at a high speed between each Magnetic Disk Controller and each cache controller; Simultaneously, also have one to be connected at a high speed between each cache controller and the Cache, all host-processors and Magnetic Disk Controller are all visited Cache by cache controller.
Fig. 5 shows another and has many interfaces, and adopts the Cache management system structural representation of two cache controllers.Referring to shown in Figure 5, all there is one to connect at a high speed between each host-processor and each cache controller, also there is one to connect at a high speed between each Magnetic Disk Controller and each cache controller; Simultaneously, all have one to connect at a high speed between each host-processor and the Cache, also have one to connect at a high speed between each Magnetic Disk Controller and the Cache, host-processor and Magnetic Disk Controller can directly be visited Cache.
Fig. 6 shows another kind and has many interfaces, and adopts the Cache management system structural representation of two cache controllers.Referring to shown in Figure 6, all there is one to connect at a high speed between each host-processor and the Cache, also there is one to connect at a high speed between each Magnetic Disk Controller and the Cache.Different is with Fig. 4 and Fig. 5, in Fig. 6, between the host-processor, between the Magnetic Disk Controller, between host-processor and the cache controller and all be to connect between Magnetic Disk Controller and the cache controller by bus mode, rather than by independent high speed by connection.
Fig. 7 also shows a kind of many interfaces that have in addition, and adopts the Cache management system structural representation of two cache controllers.Referring to shown in Figure 7, between the host-processor, between the Magnetic Disk Controller, between host-processor and the cache controller and all connect between Magnetic Disk Controller and the cache controller by bus mode; And, all have one to be connected at a high speed between each cache controller and the Cache.
In Fig. 4,5,6 and 7, each cache controller can both be handled the Cache request of access of a plurality of host-processors and a plurality of Magnetic Disk Controllers, thereby has improved the availability of Cache management system.
The two cache controller schemes of above combination are set forth the Cache management system with many interfaces, need to prove that the Cache management system with many interfaces (interface of a plurality of and host-processor and/or the interface of a plurality of Magnetic Disk Controllers) also can be separated independent use with two cache controller schemes.
In addition, the present invention also provides a kind of cache controller, and its structure mainly comprises referring to shown in Figure 8: memory management unit and the discrepancy crosspoint that is connected with memory management unit by internal bus.Wherein, memory management unit is used to manage Cache, finishes as functions such as Cache distribution, recovery, initialization.And memory management unit is connected with another cache controller by a backup path, and by this backup path and described another cache controller realization data sync, mutual telepathy hop-information and need backed up data information etc.
Wherein, the crosspoint of coming in and going out has the interface that one or more link to each other with host-processor, and has the interface that one or more link to each other with Magnetic Disk Controller.In addition, the discrepancy crosspoint also has the interface that links to each other with Cache.
The above has carried out further detailed description to purpose of the present invention, technical scheme and beneficial effect; institute is understood that; the above is not in order to restriction the present invention; within the spirit and principles in the present invention all; any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. cache management system, be used for network storage control system, described network storage control system comprises the host-processor of user oriented main frame and towards the Magnetic Disk Controller of disk, it is characterized in that, this cache management system comprises: buffer memory, first cache controller and second cache controller, wherein
First cache controller, have one or more interfaces that link to each other with host-processor and one or more interfaces that links to each other with Magnetic Disk Controller, be used to handle the cache access request of described one or more host-processors and one or more Magnetic Disk Controllers;
Second cache controller, have one or more interfaces that link to each other with host-processor and one or more interfaces that links to each other with Magnetic Disk Controller, be used to handle the cache access request of described one or more host-processors and one or more Magnetic Disk Controllers;
Connect by backup path between described first cache controller and second cache controller, and carry out data sync by this backup path, among first cache controller and second cache controller, have one lost efficacy and another just often, take over the work of the cache controller of inefficacy by normal cache controller.
2. system according to claim 1 is characterized in that, connect by backup path between described first cache controller and second cache controller, when described first cache controller and second cache controller all just often,
By the cache access request of first cache controller processing All hosts processor and all Magnetic Disk Controllers, second cache controller is not handled;
Perhaps, by the cache access request of second cache controller processing All hosts processor and all Magnetic Disk Controllers, first cache controller is not handled;
Perhaps, first cache controller and second cache controller are shared the cache access request of All hosts processor and disk processor according to load balancing mode.
3. system according to claim 1 is characterized in that,
Described first cache controller is connected with described one or more host-processors and described one or more Magnetic Disk Controllers by high-speed channel; Perhaps, described first cache controller is connected with described one or more host-processors and described one or more Magnetic Disk Controllers by bus mode;
Described second cache controller is connected with described one or more host-processors and described one or more Magnetic Disk Controllers by high-speed channel; Perhaps, described second cache controller is connected with described one or more host-processors and described one or more Magnetic Disk Controllers by bus mode.
4. system according to claim 1 is characterized in that,
Described first cache controller is connected with buffer memory respectively with second cache controller, and described one or more host-processors and described one or more Magnetic Disk Controllers are by described first cache controller or the second cache controller access cache.
5. system according to claim 1 is characterized in that,
Described one or more host-processors and described one or more Magnetic Disk Controllers are connected with buffer memory respectively, described one or more host-processors and the direct access cache of described one or more Magnetic Disk Controllers.
6. according to each described system of claim 1 to 5, it is characterized in that described cache controller comprises: be used to manage the memory management unit of buffer memory and the discrepancy crosspoint that is connected with memory management unit,
Described discrepancy crosspoint has the interface that one or more link to each other with host-processor, and has the interface that one or more link to each other with Magnetic Disk Controller.
7. system according to claim 6 is characterized in that, described discrepancy crosspoint also has the interface that links to each other with buffer memory.
8. system according to claim 6 is characterized in that, described memory management unit is connected with another cache controller by backup path, and realizes data sync by this backup path and described another cache controller.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB200710121573XA CN100464290C (en) | 2007-09-10 | 2007-09-10 | Caching management system |
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| CNB200710121573XA CN100464290C (en) | 2007-09-10 | 2007-09-10 | Caching management system |
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| CN100464290C true CN100464290C (en) | 2009-02-25 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8069300B2 (en) * | 2008-09-30 | 2011-11-29 | Micron Technology, Inc. | Solid state storage device controller with expansion mode |
| CN102215245A (en) * | 2010-04-06 | 2011-10-12 | 英业达股份有限公司 | Configuration information synchronization method of dual-controller of storage area network |
| CN102567227B (en) * | 2012-01-13 | 2014-12-03 | 北京邦诺存储科技有限公司 | Double-controller memory system and method for sharing cache equipment |
| CN102782661B (en) * | 2012-05-18 | 2015-06-17 | 华为技术有限公司 | Data storage system and method |
| CN105045531B (en) * | 2015-07-01 | 2018-01-02 | 山东超越数控电子有限公司 | Cache synchronization mechanism between one kind storage dual controller |
| CN106527978B (en) * | 2016-10-19 | 2019-07-09 | 华中科技大学 | A kind of multi-controller implementation method based on cyclic annular virtual dual control |
| CN111415291B (en) * | 2020-02-21 | 2021-09-21 | 华为技术有限公司 | Multi-core chip and scheduling method thereof |
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| US5784548A (en) * | 1996-03-08 | 1998-07-21 | Mylex Corporation | Modular mirrored cache memory battery backup system |
| CN1302017A (en) * | 1999-12-24 | 2001-07-04 | 仁宝电脑工业股份有限公司 | High speed buffer storage system with double high speed buffer mapping storage |
| CN1490730A (en) * | 2002-10-16 | 2004-04-21 | 国际商业机器公司 | Reconstructable cache memory in nonuniform memory access computer system |
| CN1499381A (en) * | 2002-11-11 | 2004-05-26 | 松下电器产业株式会社 | High speed buffer storage controller, its control method and computer system |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5784548A (en) * | 1996-03-08 | 1998-07-21 | Mylex Corporation | Modular mirrored cache memory battery backup system |
| JPH1078914A (en) * | 1996-09-04 | 1998-03-24 | Nec Corp | Cache control circuit |
| CN1302017A (en) * | 1999-12-24 | 2001-07-04 | 仁宝电脑工业股份有限公司 | High speed buffer storage system with double high speed buffer mapping storage |
| CN1490730A (en) * | 2002-10-16 | 2004-04-21 | 国际商业机器公司 | Reconstructable cache memory in nonuniform memory access computer system |
| CN1499381A (en) * | 2002-11-11 | 2004-05-26 | 松下电器产业株式会社 | High speed buffer storage controller, its control method and computer system |
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Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: Xinhua three Technology Co., Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Patentee before: Huasan Communication Technology Co., Ltd. |
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