JPH1074774A - Manufacture of field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method by which a field effect transistor having a low gate resistance can be manufactured with high reproducibility. SOLUTION: After a gate electrode 14, an n' layer 15, a through film 16, and an n layer 17 are formed on a GaAs substrate 11 and the through film 16 is removed, a protective film 18 is deposited and annealed so as to activate an ion implanted layer. Then the thickness of a first insulating film 19 is set so that the thickness of the film 19 can become equal to that of source and drain electrodes 20 formed in the next process. Then an opening is selectively formed in the insulating film 19 on the n layer 17 and an Sin, film is deposited as a second insulating film 21. At the time of depositing the film 21, the thickness of the film 21 is set so that the total thickness of the insulating films 19 and 21 can become equal to the thickness of the gate electrode 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a compound semiconductor, and more particularly to a method for manufacturing a field effect transistor for a high-speed compound semiconductor IC used in communication equipment and computers.

[0002]

2. Description of the Related Art Conventionally, in a manufacturing process of a field effect transistor (hereinafter referred to as FET) using a compound semiconductor such as GaAs, a parasitic source-drain resistance between a gate and a source and a gate and a drain is reduced, and In order to increase the breakdown voltage between the source and the gate / drain,
LDD (Lightly Doped Drai) using refractory metal gate
n) The refractory metal gate self-alignment process is widely used.

[0003] Hereinafter, the manufacturing method will be described with reference to FIG. First, as shown in FIG. 2A, a photoresist is applied on a semi-insulating GaAs substrate 11, and selective ion implantation is performed using a photolithography process to form a channel layer (n layer 12). Next, the n-layer 1
After depositing a high-melting point metal film on 2, an etching mask made of Al or the like is formed using a photolithography process. Next, as shown in FIG. 2B, a refractory metal gate electrode 14 is formed on the n-layer 12 by dry etching.

[0004] Next, as shown in FIG. 2 (c), a photoresist is applied, and selective ion implantation is performed by using a photolithography process. The layer 15 is formed. At this time, the refractory metal gate electrode 14 also functions as a mask for ion implantation, and the positions of the n layer 12 and the n ′ layer 15 are formed in a self-aligned manner.

[0005] Next, as shown in FIG. ₂ (d), SiO 2
After depositing an insulating film (through film 16) such as
As shown in (e), a photoresist is applied, and selective ion implantation using a photolithography process is performed.
The source / drain region (n ⁺ layer 17) of the FET is formed. At this time, the refractory metal gate electrode 14 also serves as a mask for ion implantation, and the positions of the n ′ layer 15 and the n ⁺ layer 17 are formed in a self-aligned manner. Next, as shown in FIG. 2F, an insulating film (protective film 18) such as SiO ₂ is deposited, and an annealing process is performed using the film as a protective film to activate implanted ions to form an active layer of the FET. I do. Next, as shown in FIG. 2G, a source / drain electrode 20 is formed on the n ⁺ layer 17.

In order to operate the FET at a higher frequency, it is necessary to shorten the gate length to shorten the travel distance of electrons in the active layer, reduce the gate resistance, and reduce the input resistance of an input signal. It is. However, since the refractory metal generally has a high resistance, the FET thus manufactured has a high gate resistance and is not suitable for high-frequency operation. FET
In order to perform high-frequency operation, it is necessary to reduce the gate length and to form a low-resistance metal layer such as gold on the high-melting-point gate metal to reduce the gate resistance.

Therefore, as a method of forming a low-resistance metal layer on a fine gate having a gate length of 0.5 μm or less, a method using an etch-back method is used. Less than,
The manufacturing method will be described with reference to FIG.

First, a gate electrode forming step, an ion implantation step, and an annealing step are performed on a semi-insulating GaAs substrate 11 using a conventional LDD refractory metal gate self-alignment process. Next, as shown in FIG. 3A, an insulating film is deposited so that the total thickness of the protective film 18 and the gate electrode 14 becomes the same. Hereinafter, it is referred to as a first insulating film 19 together with the protective film 18.

Next, as shown in FIG. 3 (b), a flattening resist 22 is applied and then heated to flatten the surface of the flattening resist 22 as shown in FIG. 3 (c). Next, as shown in FIG. 3D, dry etching (hereinafter referred to as etch back) is performed under the condition that the etching rates of the planarizing resist 22 and the first insulating film 19 on the gate electrode 14 become equal. Then, the surface of the gate electrode 14 is exposed while the surfaces of the gate electrode 14 and the first insulating film 19 are flat.

Next, as shown in FIG. 3E, the n ⁺ layer 1
An opening is selectively formed in the first insulating film 19 on the top 7 by using photolithography, and a source / drain electrode 20 is formed by vapor deposition and a lift-off method. Finally, FIG.
As shown in (f), a low-resistance metal layer 24 such as gold is formed on the gate electrode 14 and the source / drain electrodes 20.

According to this manufacturing method, a low-resistance metal layer can be formed on a fine gate electrode.

[0012]

However, in this manufacturing method, as shown in FIG. 3E, when the low resistance metal layer 24 is formed, the slit 25 exists around the source / drain electrode 20. , A portion drawn from the source / drain electrode 20 (the source / drain electrode lead portion 2).
In 6), there is a possibility that a crack 27 is formed in the low-resistance metal layer 24.

Therefore, in forming the low resistance metal layer 24, the following method is used to prevent the slit 25 from being present around the source / drain electrode 20. Hereinafter, the manufacturing method will be described with reference to FIG.

First, a gate electrode forming step, an ion implantation step, and an annealing step are performed on a semi-insulating GaAs substrate 11 using a conventional LDD refractory metal gate self-alignment process. Next, as shown in FIG.
^An opening is selectively formed in the protective film 18 on the ⁺ layer 17 by using photolithography, and a source / drain electrode 20 is formed by vapor deposition and a lift-off method. Next, FIG.
As shown in FIG. 7, an insulating film is deposited. Hereinafter, it is referred to as a first insulating film 19 together with the protective film 18. At this time, the protective film 18
The first insulating film 19 is formed such that the sum of the thickness of the insulating film and the thickness of the insulating film (that is, the thickness of the first insulating film 19) is the same as that of the gate electrode 14. Next, as shown in FIG. 4C, a flattening resist 22 is applied and heated, and
As shown in (d), the surface of the planarizing resist 22 is planarized. Next, as shown in FIG. 4E, etch-back is performed under the condition that the etching rates of the planarization resist 22 and the first insulating film 19 on the gate electrode 14 are equal to each other. The gate electrode 14 is exposed while the surface of the first insulating film 19 is flat. Next, FIG.
As shown in FIG. 4F, after selectively forming openings 23 in the first insulating film 19 on the source / drain electrodes 20 by using photolithography, finally, as shown in FIG. , Gate electrode 14 and source / drain electrode 20
A low resistance metal layer 24 such as gold is formed thereon.

According to this manufacturing method, the low resistance metal layer 24
In the step of forming a low-resistance metal layer on the fine gate electrode, no crack is formed in the source-drain electrode lead-out portion 26 because no slit exists around the source / drain electrode 20. Can be formed.

However, in this manufacturing method, in the step of applying the flattening resist 22, there is a step not only on the gate electrode 14 but also on the source / drain electrode 20 as shown in FIG. Therefore, when the planarizing resist 22 is heated, the planarizing resist 22 on the gate electrode 14 and the source / drain electrodes 20 peels off as shown in FIG. There is a problem that voids (planarization resist voids 28) are generated and the active layers around the gate electrode 14 and the source / drain electrodes 20 are damaged when etched back.

The present invention has been made in view of the above points, and an object of the present invention is to form a flattening photoresist and to form a low-resistance metal layer on source / drain electrodes with good reproducibility in a flattening step. It is another object of the present invention to provide an FET having a low gate resistance and good reproducibility and a method for manufacturing the same.

[0018]

In order to achieve the above object, means relating to a method of manufacturing a field effect transistor according to claims 1, 2, 3, 4 and 5 are taken.

According to the first aspect of the present invention, there is provided a first step of forming a gate electrode on a substrate, and a second step of forming a first insulating film on the substrate including the gate electrode. A third step of selectively providing an opening in the first insulating film to form a source / drain electrode on the substrate, and a fourth step of forming a second insulating film on the substrate; A fifth step of applying a resist on the substrate, and a sixth step of exposing the gate electrode surface by etching the resist, the second insulating film and the first insulating film,
A method comprising a seventh step of selectively providing an opening in an insulating film on the source / drain electrodes, and an eighth step of forming a metal layer on the gate electrode and the source / drain electrodes. .

Means taken by the invention of claim 2 is claim 1
The method according to the above aspect, wherein a difference between the thicknesses of the first insulating film and the source / drain electrodes is within 150 nm.

Means taken by the invention of claim 3 is claim 1
Alternatively, in the invention according to the second aspect, a difference that a difference between a total thickness of the first insulating film and the second insulating film and a thickness of the gate electrode is 100 nm or less is added.

Means taken by the invention of claim 4 is claim 1
Alternatively, in the invention according to the second or third aspect, a method is provided in which the first insulating film and the second insulating film are SiO ₂ films.

Means taken by the invention of claim 5 is claim 1
Alternatively, in the invention according to 3 or 4, the first insulating film and the source are so formed as to flatten the second insulating film on the source / drain electrodes in a fifth step of applying a resist on the substrate. A method in which the formation of a drain electrode is added.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing an FET according to the present invention will be described below with reference to FIG. FIG.
FIG. 3 is a cross-sectional view showing a structure in each manufacturing process of the FET according to the present invention.

First, as shown in FIG. 1A, a semi-insulating GaAs substrate 11 is used as a substrate, and the semi-insulating GaAs substrate 11 is used.
The photoresist is used as a mask on an As substrate 11 at an acceleration voltage of 20 keV and a dose of about 1.0 × 10 ¹³ cm ⁻² to form S.
I channel ions are implanted to form a channel layer (n layer 12). Subsequently, an acceleration voltage of 180 keV and a dose of 2.0 ×
Mg ions are implanted at about 10 ¹² cm ^-2 to form a buried p-layer (BP layer 13).

Next, as shown in FIG. 1B, a 400 nm thick gate metal is formed on the surface of the semi-insulating GaAs substrate 11.
After depositing a WSi film of about m, the gate electrode 14 is formed by anisotropic dry etching by RIE using Al or the like as a mask.

Next, as shown in FIG. 1C, Si ions are implanted on the semi-insulating GaAs substrate 11 using a photoresist as a mask at an acceleration voltage of 30 keV and a dose of about 3.0 × 10 ¹² cm ^−2. Then, an n ′ layer 15 is formed.

Next, as shown in FIG. 1D, a through film 1 is formed on a semi-insulating GaAs substrate 11 including a gate electrode 14.
As 6, a SiO ₂ film having a thickness of about 200 nm is deposited.

Next, as shown in FIG. 1E, the photoresist is used as a mask on the semi-insulating GaAs substrate 11 through the through film 16 at an acceleration voltage of 150 keV and a dose of about 5.0 × 10 ¹³ cm ⁻² . Si ions are implanted and n ⁺
The layer 17 is formed.

Next, as shown in FIG. 1 (f), after removing the through film 16, an SiO ₂ film having a thickness of about 100 nm is deposited as a protective film 18, followed by annealing at 800 ° C. for about 15 minutes. To activate the ion-implanted layer.

Next, as shown in FIG. 1G, an SiO ₂ film having a thickness of about 150 nm is deposited as an insulating film. Hereinafter, it is referred to as a first insulating film 19 together with the protective film 18. At this time, the first insulating film 19 is formed such that the film thickness of the first insulating film 19 (total thickness of the protective film 18 and the insulating film) is equal to the source / drain electrodes 20 formed in the next step. Is set.

Next, as shown in FIG. 1 (h), an opening is selectively formed in the first insulating film 19 on the n ⁺ layer 17 by photolithography, and a film thickness of 2 is formed by vapor deposition and lift-off.
A source / drain electrode 20 made of an AuGe / Ni / Au layer of about 50 nm is formed.

Next, as shown in FIG. 1I, an SiO ₂ film having a thickness of about 150 nm is deposited as the second insulating film 21. At this time, the thickness of the second insulating film 21 is set so that the total thickness of the first insulating film 19 and the second insulating film 21 becomes equal to the gate electrode 14.

Next, as shown in FIG. 1J, after a flattening resist 22 is applied, as shown in FIG.
The surface of the flattening resist 22 is flattened by heating.

Next, as shown in FIG. 1 (l), by using RIE using a mixed gas of CHF ₃ / CF ₄ / O ₂ , the etching rates of the planarizing resist 22 and the SiO ₂ film are almost equal. To expose the surface of the gate electrode 14 while the surface is flat.

Next, as shown in FIG. 1 (m), openings 23 are selectively provided on the source / drain electrodes 20 by using photolithography.

Next, as shown in FIG. 1 (n), a Ti film having a thickness of about 500 nm is deposited at predetermined positions on the gate electrode 14 and the source / drain electrodes 20 by vapor deposition and lift-off.
A low resistance metal layer 24 made of an Au layer is formed.

In this embodiment, as shown in FIG.
After the formation of the source / drain electrodes, the second insulating film 21 is deposited to cover the slits 25 formed around the source / drain electrodes 20 in the source / drain electrode forming step with the second insulating film. In order to perform backing, as shown in FIG. 1 (n), in the step of forming the low-resistance metal layer 24, there is no slit around the source / drain electrode 20 and the low-resistance The cracks are not generated in the metal layer 24 and the fine gate electrode 14 and the source / drain electrode 20
A low resistance metal layer 24 can be formed thereon.

The first and second insulating films 19 and 19 are formed so that the thickness of the source / drain electrodes 20 is equal to the thickness of the first insulating film 19.
Since the thickness of the insulating film 19 is set, as shown in FIG. 1 (j), there is no step on the source / drain electrode 20 in the step of applying the planarizing resist 22, and the planarizing resist The resist 22 for planarization on the gate electrode 14 and the source / drain electrode 20 does not come off when the substrate 22 is heated, and the active layer around the gate electrode 14 and the source / drain electrode 20 is damaged when etched back. There is no danger.

Further, the first insulating film 19 and the second insulating film 2
Since the thickness of the second insulating film 21 is set so that the total thickness of the first insulating film 1 becomes equal to the thickness of the gate electrode 14, the planarizing resist 22 and the SiO 2
By performing the etching under the condition that the etch rates of the _two films are substantially equal, the surface of the gate electrode 14 is exposed when the etching of the planarization resist 22 is completed, and the object to be etched is removed from the planarization resist 22. The end point of the etching can be detected by detecting the change to the insulating film from the change in the light emission intensity in the plasma.

[0041]

As described above, according to the present invention, the following effects can be obtained.

According to the first, second, third, fourth and fifth aspects of the present invention, after forming the source / drain electrodes 20, the second insulating film 2 is formed.
In the source / drain electrode formation step, the slit 25 formed around the source / drain electrode 20 is covered with the second insulating film 21 in the source / drain electrode forming step, and then the low-resistance metal layer 24 is etched back. In the step of forming the gate electrode 14, no slit exists around the source / drain electrode 20, the crack 27 does not occur in the low-resistance metal layer 24 in the source / drain electrode lead-out portion 26, The low resistance metal layer 24 can be formed on the drain electrode 20.

According to the second aspect of the present invention, the thickness of the first insulating film 19 is set so as to be substantially equal to the thickness of the source / drain electrodes 20, so that the planarizing resist 2 is formed.
In the step of applying 2, there is no step on the source / drain electrode 20, and the planarization resist 22 on the gate electrode 14 and the source / drain electrode 20 does not come off when the planarization resist 22 is heated. In addition, it is possible to eliminate the possibility that the active layer around the gate electrode 14 and the source / drain electrodes 20 may be damaged when the etch back is performed.

According to the third aspect of the present invention, the first insulating film 1
9 and the thickness of the second insulating film 21 are set so as to be substantially equal to the thickness of the gate electrode 14. Since the surface of the substrate 14 is exposed, it is possible to detect the end point of the etching by detecting that the object to be etched has changed from the planarizing resist 22 to the insulating film, thereby improving the reproducibility of the etch-back process.

According to the invention of claim 4, the first insulating film 1
9 and the second insulating film 21 are made of a SiO ₂ film, so that a gas mixture of CHF ₃ / CF ₄ / O ₂ can be easily used.
Since the etching rates of the planarizing resist 22, the first insulating film 19, and the second insulating film 21 can be made substantially equal, the surface of the gate electrode 14 can be exposed while the surface is flat.

According to the fifth aspect of the present invention, in the step of applying the flattening resist 22, the source / drain electrodes 20 are formed.
By forming the first insulating film 19 and the source / drain electrodes 20 so that the upper insulating film becomes flat, the same effect as the invention of claim 2 can be exerted.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a structure in each manufacturing step of a field-effect transistor according to the present invention.

FIG. 2 is a cross-sectional view showing a structure in each manufacturing process of a conventional field-effect transistor.

FIG. 3 is a cross-sectional view showing a structure in each manufacturing process of a conventional field-effect transistor.

FIG. 4 is a cross-sectional view showing a structure in each manufacturing process of a conventional field-effect transistor.

FIG. 5 is a sectional view showing a structure of a part of a conventional field effect transistor in a manufacturing process.

[Explanation of symbols]

Reference Signs List 11 substrate (semi-insulating GaAs substrate) 12 n layer 13 BP layer 14 gate electrode 15 n 'layer 16 through film 17 n ⁺ layer 18 protective film 19 first insulating film 20 source / drain electrode 21 second insulating film 22 Planarization resist 23 Opening 24 Low resistance metal layer 25 Slit 26 Source / drain electrode lead-out part 27 Crack 28 Planarization resist void

Claims (5)

[Claims] 1. A first step of forming a gate electrode on a substrate, wherein at least one gate electrode is formed on the substrate including the gate electrode.
A second step of forming a kind of first insulating film; and a third step of selectively providing an opening in the at least one kind of first insulating film to form a source / drain electrode on the substrate. A fourth step of forming at least one type of second insulating film on the substrate, a fifth step of applying a resist on the substrate, the resist, the second insulating film, and the first A sixth step of exposing the surface of the gate electrode by etching the insulating film, a seventh step of selectively providing an opening in the insulating film on the source / drain electrode, 8. A method for manufacturing a field effect transistor, comprising an eighth step of forming a metal layer on a drain electrode. 2. The method according to claim 1, wherein the difference between the thickness of the first insulating film and the thickness of the source / drain electrode is within 150 nm. 3. The difference between the total thickness of the first insulating film and the second insulating film and the thickness of the gate electrode is 100 nm.
3. The method for manufacturing a field effect transistor according to claim 1, wherein: 4. The method according to claim 1, wherein the first insulating film and the second insulating film are SiO ₂ films.
Or the method for manufacturing a field-effect transistor according to 3. 5. The first insulating film and the source / drain electrode so that the second insulating film on the source / drain electrode is flattened in a fifth step of applying a resist on the substrate. The method for manufacturing a field effect transistor according to claim 1, wherein: